CIA II QUESTION BANK
Programme (s) Semester Course Code (s) Course Title
B.E III 22EC302 DIGITAL ELECTRONICS
COURSE OUTCOMES
C301.1 Demonstrate knowledge on canonical forms and their realization using logic gates
C301.2 Applying K- Map and Tabulation method to minimize the Boolean functions.
C301.3 Understand various combinational logic and sequential logic circuits and their implementation
C301.4 Apply synchronous sequential logic for reducing state reduction.
C301.5 Understanding Programmable logic devices and applying for logical function implementation.
C301.6 Apply verilog code for realization of combinational logical circuits.
PART A
1. Analyze the differences between Latch and Flip flop.
2. Build a T Flip-flop from a D Flip-flop.
3. State the difference between Mealy and Moore state machines.
4. Model a NAND based logic diagram of Master Slave JK FF.
5. Derive the characteristic equation for JK Flipflop
6. How state equation will be derived for a synchronous sequential circuit.
7. Sketch the diagram for storing and shifting bit values in PISO.
8. Implement full adder using PLA.
9. State the advantages of HDL.
10. Write the verilog code for half Subtractor using data flow modeling.
11. Define latch? Write the difference between latch and flip flop?
12. Draw the state diagram and characteristics equation of a D FF.
13. How will you convert JK FF into DFF?
14. Show that the characteristic equation for the complement output of a JK flip flop is Q’(t+1)=J’Q’
+KQ
15. How many Flip Flops are required to build a binary counter that counts from 0 to 1023.
16. How state equation will be derived for a synchronous sequential circuit.
17. Consider a register that can store 8 bits. Assume that it has been reset so that it contains zeros in all
positions. If you transfer four alternating bits (0101) serially into the register, beginning with a 1 and
shifting to the right, what will the total content of the register be as soon as the fourth bit is stored?
18. Draw a comparison between PLA and PAL.
19. Give the syntax for package declaration and package body in verilog.
20. Write the verilog code for half adder using behavioral modeling.
PART - B
1 Explain the functions with the state diagram and characteristics equation for T,D and JK Flip Flop.
2 Realize D flip-flop using SR flip-flop.
3 Illustrate with diagram an asynchronous decade counter & its operation with neat waveforms
4 Construct a four bit SISO SIPO, PIPO and PISO shift register and draw its corresponding
waveforms.
5 Find the number of Flip-flops required to generate a sequence 1101011 and design the circuit
using JK flip flop.
6
For the given state equation, analyze the circuit and construct its logic circuit and state diagram.
A(t+1) = A(t) x(t) + B(t) x(t)
B(t+1) = A`(t) x(t)
Y(t) = (A(t) + B(t)) x(t)’
7 Analyze the given synchronous sequential circuit using D flipflop and draw its
corresponding state diagram. The inputs are x and y and the output is A.
8 Implement the following Boolean functions using PAL.
(i) W(A,B,C,D)= Σ (0,2, 6,7,8,9,12,13)
(ii) X(A,B,C,D)= Σ (0, 2, 6, 7, 8, 9, 12, 13, 14)
(iii)Y(A, B, C, D) = Σ ( 2, 3, 8, 9, 10, 12, 13)
(iv) Z(A,B,C,D)= Σ (1, 3, 4, 6, 9, 12, 14)
9 Classify the types of PLDs and write notes on types of PLDs.
10 Implement the following Boolean function using 3×4×2 PLA,
F1(x, y, z) = Σ (0, 1, 3, 5) and F2(x, y, z) = Σ (3, 5, 7).
11 Write the verilog code for a 4 bit parallel adder.
12Write the verilog code for 4 x 1 Multiplexer using dataflow modeling.
13Write the verilog code for 3:8 decoder using behavioral modeling.
14Differentiate between a state table, characteristic table and an excitation table for D Flip Flop
15Realize T flip-flop using SR flip-flop.
16Design a synchronous MOD- 5 counter.
17Explain the working of 4-bit Up Ripple counter.
18Summarize 4-bit SISO SIPO, PIPO and PISO shift register and draw its waveforms.
19 Design a 4 bit Ring Counter and Johnson Counter
A sequential circuit with 2 numbers of D- FF A and B and input X and output Y is
specified by the following next state and output equation
A (t+1) = AX+BX
B (t+1) = A’X
Y = (A+B) X’
(i) Draw the logic diagram of the circuit
(ii) Derive the state table
(iii) Draw the state diagram.
21 Design a clocked synchronous sequential logic circuit for the following state diagram using T
flip flops. Use state reduction if possible.
