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Chap 02 P2 KExamples

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34 views17 pages

Chap 02 P2 KExamples

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arul2005is
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BCD-to-Excess-3 Code converter

 BCD is a code for the decimal digits 0-9


 Excess-3 is also a code for the decimal digits

1
Specification of BCD-to-Excess3

 Inputs: a BCD input, A,B,C,D with A as the most


significant bit and D as the least significant bit.
 Outputs: an Excess-3 output W,X,Y,Z that
corresponds to the BCD input.
 Internal operation – circuit to do the conversion in
combinational logic.

2
Formulation of BCD-to-Excess-3

 Excess-3 code is easily formed by adding a binary


3 to the binary or BCD for the digit.
 There are 16 possible inputs for both BCD and
Excess-3.
 It can be assumed that only valid BCD inputs will
appear so the six combinations not used can be
treated as don’t cares.

3
Placing 1 on K-maps

 Where are the minterms located on a K-Map?

4
Expressions for W X Y Z

 W(A,B,C,D) = Σm(5,6,7,8,9)
+d(10,11,12,13,14,15)
 X(A,B,C,D) = Σm(1,2,3,4,9)
+d(10,11,12,13,14,15)
 Y(A,B,C,D) = Σm(0,3,4,7,8)
+d(10,11,12,13,14,15)
 Z(A,B,C,D) = Σm(0,2,4,6,8)
+d(10,11,12,13,14,15)

5
Optimization – BCD-to-Excess-3

 Lay out K-maps for each output, W X Y Z

 A step in the digital circuit design process.

6
Minimize K-Maps

 W minimization

W = A + BC + BD

7
Minimize K-Maps

 X minimization

X = BC’D’+B’C+B’D
8
Minimize K-Maps

 Y minimization

Y = CD + C’D’

9
Minimize K-Maps

 Z minimization

Z = D’

10
Two level circuit implementation

 Have equations
• W = A + BC + BD = A + B(C+D)
• X = B’C + B’D + BC’D’ = B’(C+D) + BC’D’
• Y = CD + C’D’
• Z = D’
 Factoring out (C+D) and call it T
 Then T’ = (C+D)’ = C’D’
• W = A + BT
• X = B’T + BT’
• Y = CD + T’
• Z = D’

11
Create the digital circuit

 Implementing the
second set of
equations where
T=C+D results in a
lower gate count.
 This gate has a
fanout of 3

12
BCD-to-Seven-Segment Decoder

 Specification
• Digital readouts on many digital products often use LED
seven-segment displays.
• Each digit is created by lighting the appropriate
segments. The segments are labeled a,b,c,d,e,f,g
• The decoder takes a BCD input and outputs the correct
code for the seven-segment display.

13
Specification

 Input: A 4-bit binary value that is a BCD coded


input.
 Outputs: 7 bits, a through g for each of the
segments of the display.
 Operation: Decode the input to activate the
correct segments.

14
Formulation

 Construct a truth table

15
Optimization

 Create a K-map for each output and get


• A = A’C+A’BD+B’C’D’+AB’C’
• B = A’B’+A’C’D’+A’CD+AB’C’
• C = A’B+A’D+B’C’D’+AB’C’
• D = A’CD’+A’B’C+B’C’D’+AB’C’+A’BC’D
• E = A’CD’+B’C’D’
• F = A’BC’+A’C’D’+A’BD’+AB’C’
• G = A’CD’+A’B’C+A’BC’+AB’C’

16
Note on implementation

 Direct implementation would require 27 AND


gates and 7 OR gates.
 By sharing terms, can actualize and implementation
with 14 less gates maintaining just 2 levels.

 Normally decoder in a device name indicates that


the number of outputs is less than the number of
inputs.

17

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