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UNIT 3 Instruction Set Architecture and Assembly Language Programming

The document discusses instruction set architecture and assembly language programming. It covers RISC vs CISC processors, addressing modes, instruction cycles, and stack operations. Subroutines and interrupts on the 8085 microprocessor are also explained.

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30 views120 pages

UNIT 3 Instruction Set Architecture and Assembly Language Programming

The document discusses instruction set architecture and assembly language programming. It covers RISC vs CISC processors, addressing modes, instruction cycles, and stack operations. Subroutines and interrupts on the 8085 microprocessor are also explained.

Uploaded by

kjspa7541
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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UNIT 3 Instruction set Architecture and

Assembly language programming


Self study
What is RISC processor
What is CISC processor
What is difference and applications.
Von Neuman and Harvard Architecture
Addressing Modes:

Purpose of addressing modes:

Phases of Instruction cycle:


1. Opcode Fetch
2. Decode instruction
3. Execution
Addressing modes …

1. Implied mode:
 in this the operand is explicitly
mentioned in opcode, e.g.
complement accumulator,
 also called as zero address instruction
( no address field required,)
 length of instruction is only one word
2. Immediate Mode:
The operand is provided immediately after opcode.
Operand is in instruction only
Useful for initializing the registers with constant value.
3. Register mode:
The operand is in some CPUU register

4. Register indirect:
In this the instruction specifies a CPU register
where operand address is found.
CPU register contains address of operand
5. Direct Addressing:
Address of operand is in copcode only
6. Indirect Addressing:
The effective address of operand is at location pointed by
content of memory location pointed by address field of
instruction
7. Auto Increment- Auto decrement addressing:
Pointing register is automatically incremented or decremented after each
use
8. Base Register Addressing:
EA=base register + Address field
9. Relative addressing:
EA=PC+ Address field of instruction
8085 microprocessor: 8 bit data bus, 16 bit address bus
Demultiplexing of address and data lines
Functional Block Diagram
Stack Pointer

LXI SP, 8000H LXI H, 8000H


LXI H, 1234H SPHL
PUSH H LXI H, 1234H
PUSH H
POP D POP D
HLT HLT
We can Push the content of PSW (Program
Status Word—Accumulator + status register) on
to the stack.
We can pop the content of stack into PSW
we can set the flags as per our requirement
Precaution of using push and pop
1. Push and pop should be used in
opposite order to retain the value
2. There should as many PUSH as POP
(otherwise RET may result in wrong
otcome)
e.g.
PUSH B
PUSH D
---
----
POP D
POP B
Here it is FILO.
Program to clear ALL flags:

LXI SP 5000H
MVI L, 00H
PUSH H
POP PSW /// clear flags
PUSH PSW
POP H
MOV A, L
Out 41H// display at port no 41 (display device connected)
HLT
Subroutine:
A small program written separately from the main program
to perform a particular task.
The task may be repeatedly required in the main program.
Used to avoid the repetition of smaller programs.
Subroutines are written separately and are stored in a
memory location that is different from the main program.
You can call a subroutine multiple times from the main
program using a simple CALL instruction.
Similar to function call of high level language.
CALL address // used to call a subroutine. It is done by
pushing the return address (content of PC) onto stack
RET // used to return from subroutine by POPing the
Stack Pointer into PC
It is advisable to initialise SP before using CALL
RET Instruction:
Implementing Call by Value and Call
by reference
Write a program to display FF and 11 repeatedly on seven segment
display. Write a delay subroutine and call it.

LXI SP FFFFH
Start: MVI A FFH
OUT 00H
CALL Delay
MVI A, 11
OUT 00H
CALL Delay
JUMP Start

Delay: MVI B FFH // subroutine starts here, B is outer loop counter


Outer: MVI C FF// set inner loop counter
Inner: DCR C
JNZ Inner
DCR B
JNZ outer // total count of 256*256 is done?
RET // return to calling function (main program)
Interrupt of 8085

https://www.slideshare.net/grambabu77/8085
-interrupts-50457972
E E’
Basic IO interfacing

For peripheral:
IO/M’=1

For memory:
IO/M’=0

Including
IO/M’and
WR’and RD’
total 4 control
signals can be
generated.
Interrupts in 8085

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