Index

Exp. No Date Title Page No

1 25-02-23
29-01-2024 IMPLEMENTATION OF HALF ADDER 4 -6
2 25-02-23
29-01-2024 IMPLEMENTATION OF FULL ADDER 7-10
3 04-03-23
05-02-2024 IMPLEMENTATION OF ENCODER 11-15
4 04-03-23
05-02-2024 IMPLEMENTATION OF DECODER 16-19
5 11-03-23
12-02-2024 IMPLEMENTATION OF MULTIPLEXER 20-24
6 11-03-23
12-02-2024 IMPLEMENTATION OF DEMULTIPLEXER 25-28
7 18-03-23
19-02-2024 IMPLEMENTATION OF D FLIPFLOP 29-31
8 25-03-23
26-02-2024 IMPLEMENTATION OF SISO SHIFT REGISTER 32-35
9 01-04-23
04-03-2024 IMPLEMENTATION OF BINARY UP/DOWN COUNTER 36-39
10 08-04-23
09-03-2024 IMPLEMENTATION OF RIPPLE CARRY ADDER 40-42
11 15-04-23
11-03-2024 IMPLEMENTATION OF BRUN MULTIPLIER 43-46
12 22-04-23
11-03-2024 IMPLEMENTATION OF WALLACE TREE MULTIPLIER 47-51
13 29-04-23
18-03-2024 IMPLEMENTATION OF RANDOM-ACCESS MEMORY 52-54
14 06-05-23
18-03-2024 IMPLEMENTATION OF ARITHMETIC LOGIC UNIT (ALU) 55-57
15 13-05-23
25-03-2024 IMPLEMENTATION OF CMOS CODE 58-60
16 20-05-23
02-04-2024 IMPLEMENTATION OF CMOS INVERTER 61-63
17 20-05-23
02-04-2024 IMPLEMENTATION OF CMOS NAND 64-66
18 27-05-23
10-04-2024 IMPLEMENTATION OF PSEUDO CMOS NAND 67-69
19 27-05-23
10-04-2024 IMPLEMENTATION OF DYNAMIC CMOS NAND 70-72
27-05-23 IMPLEMENTATION OF CMOS NAND/AND IN CASCODE
20 18-04-2024 73-75
VOLTAGE SWITCH LOGIC
Ex no: 01
IMPLEMENTATION OF HALF ADDER
Date: 29-01-2024
25-02-23

Aim:

To implement the Half adder using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

a) Structural Description

module Half_adder_1(A, B, SUM, CARRY);

input A, B;
output SUM, CARRY;
xor (SUM, A, B);
and (CARRY, A, B);
endmodule

b) Data Flow Description

module Half_adder_2( A, B, SUM, CARRY);

input A, B ;
output SUM, CARRY;
assign SUM = A ^ B;
assign CARRY = A & B;
endmodule

c) Behavioural Description

module Half_adder_3( A, B, SUM, CARRY);

input A, B ;
output SUM, CARRY;
always @(A or B);
assign {CARRY,SUM}= A+B;
endmodule

4
Ex no: 02
IMPLEMENTATION OF FULL ADDER
Date: 29-01-2024
25-02-23

Aim:

To implement the Full adder using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

A) Structural Description

module Full_adder_1( A, B, Cin, SUM, CARRY);

wire w1,w2,w3;
input A, B, Cin ;
output SUM, CARRY;
xor (w1, A, B);
xor (SUM, Cin, w1);
and (w3, A, B);
and (w2,Cin,w1);
or (CARRY, w3,w2);
endmodule

B) Data Flow Description

module Full_adder_1( A, B, Cin, SUM, CARRY);

wire w1,w2,w3;
input A, B, Cin ;
output SUM, CARRY;

C) Behavioural Description

module FullAdder(X1,X2,Cin,Sum,Carry);
input X1,X2,Cin;
output Sum,Carry;
reg [1:0] temp;
always @(*)
begin

7
Ex no: 03
IMPLEMENTATION OF ENCODER
Date: 05-02-2024
04-03-23

Aim:

To implement the Encoder using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

a) Structural Description

module Encoder(en,i,y);
// declare port list via input and output
input en;
input [7:0]i;
output [2:0]y;
wire temp1,temp2,temp3;
or o1(temp1,i[4],i[5],i[6],i[7]);
or o2(temp2,i[2],i[3],i[6],i[7]);
or o3(temp3,i[1],i[3],i[5],i[7]);
and a1(y[2],temp1,en);
and a2(y[1],temp2,en);
and a3(y[0],temp3,en);
endmodule

b) Data Flow Description

module Encoder(en,i,y);
// declare port list via input and output
input en;
input [7:0]i;
output [2:0]y;
// check the logic diagram and assign the outputs
assign y[2]=i[4] | i[5] | i[6] | i[7] &en;
assign y[1]=i[2] | i[3] | i[6] | i[7] &en;
assign y[0]=i[1] | i[3] | i[5] | i[7] &en;

11
Ex no: 04
IMPLEMENTATION OF DECODER
Date: 05-02-2024
04-03-23

Aim:

To implement the Decoder using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

a) Data Flow Description

module Decoder(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(~a&~b&~c),
d1=(~a&~b&c),
d2=(~a&b&~c),
d3=(~a&b&c),
d4=(a&~b&~c),
d5=(a&~b&c),
d6=(a&b&~c),
d7=(a&b&c);
endmodule

b) Behavioral Description

module Decoder( in,out, en);

input [2:0] in;
input en;
output [7:0] out;
reg [7:0] out;
always @( in or en)
begin
if (en)
begin

16
Ex no: 05
IMPLEMENTATION OF MULTIPLEXER
Date: 12-02-2024
11-03-23

Aim:

To implement the Multiplexer using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

A) Behavioral Description

module multiplexbehaviourl(I,sel,Y);
input [7:0]I;
input [2:0]sel;
output reg Y;
always@(*)
begin
case(sel)
3'b000: Y=I[0];
3'b001: Y=I[1];
3'b010: Y=I[2];
3'b011: Y=I[3];
3'b100: Y=I[4];
3'b101: Y=I[5];
3'b110: Y=I[6];
3'b111: Y=I[7];
default: Y=1'b0;
endcase
end
endmodule

B) Data flow

module muxdataflow(output out, input D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2);
assign S1bar=~S1;

20
Ex no: 06
IMPLEMENTATION OF DEMULTIPLEXER
Date: 12-02-2024
11-03-23

Aim:

To implement the Multiplexer using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

A) Behavioral Description

module DUMULTIPLIXER(y,s,a);
output reg [7:0]y;
input [2:0]s;
input a;
always @(*)
begin
y=0;
case(s)
3'd0: y[0]=a;
3'd1: y[1]=a;
3'd2: y[2]=a;
3'd3: y[3]=a;
3'd4: y[4]=a;
3'd5: y[5]=a;
3'd6: y[6]=a;
3'd7: y[7]=a;
endcase
end
Endmodule

B) Data flow

module Demultiplexer(in,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
input in,s0,s1,s2;

25
Ex no: 07

IMPLEMENTATION OF D FLIPFLOP
Date : 19-02-2024
18-03-23

Aim:

To implement the D Flip Flop using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

module DFF( input clk,

input d,
input rst,
output q);
reg q;
always@(posedge clk)
begin
if (rst==1)
q<=0;
else
q<=d;
end
endmodule

Diagram & Truth Table:

29
Ex no: 08

IMPLEMENTATION OF SISO SHIFT REGISTER

Date : 26-02-2024
25-03-23

Aim:

To implement the SISO Shift Register using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

module siso ( din ,clk ,reset ,dout );

output dout ;
input din ;
input clk ;
input reset ;
wire [2:0]s;
d_flip_flop u0 (.din(din),.clk(clk),.reset(reset),.dout(s[0]));
d_flip_flop u1 (.din(s[0]),.clk(clk),.reset(reset),.dout(s[1]));
d_flip_flop u2 (.din(s[1]),.clk(clk),.reset(reset),.dout(s[2]));
d_flip_flop u3 (.din(s[2]),.clk(clk),.reset(reset),.dout(dout));
Endmodule

Diagram & Truth table:

32
Ex no: 09
IMPLEMENTATION OF BINARY UP/DOWN COUNTER
Date : 04-03-2024
01-04-23

Aim:

To implement the Binary Up/down counter using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

module updown(clk,rst,UpOrDown,Count);
input clk,rst,UpOrDown;
output [3 : 0] Count;
reg [3 : 0] Count;
always @(clk)
begin
if(rst==1)
Count<=0;
else if(UpOrDown==1)
if(Count==15)
Count<=0;
else
Count<=Count+1;
else if(Count==0)
Count<=15;
else
Count<=Count-1;
end
Endmodule

36
Ex no: 10
IMPLEMENTATION OF RIPPLE CARRY ADDER
Date : 09-03-2024
08-04-23

Aim:

To implement the Ripple carry Adder using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

module FullAdder(X,Y,Z,S,C);
input X,Y,Z;
output S,C;
assign S=X^Y^Z;
assign C=(X&Y)|(Z&(X^Y));
endmodule

module Ripple_Carry_Adder1(A,B,S,C);
input [3:0]A;
input [3:0]B;
output [3:0]S;
output C;
wire W1,W2,W3;
FullAdder L1(A[0],B[0],1'b0,S[0],W1);
FullAdder L2(A[1],B[1],W1,S[1],W2);
FullAdder L3(A[2],B[2],W2,S[2],W3);
FullAdder L4(A[3],B[3],W3,S[3],C);
Endmodule

40
Output:

Device utilization summary:

Selected Device : 3s100evq100-5

Number of Slices: 4 out of 960 0%
Number of 4 input LUTs: 7 out of 1920 0%
Number of IOs: 13
Number of bonded IOBs: 13 out of 66 19%
Partition Resource Summary: No Partitions were found in this design.
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
41
 FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
No clock signals found in this design
Asynchronous Control Signals Information:No asynchronous control signals found in this design
Timing Summary:
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.898ns
Timing Detail:
All values displayed in nanoseconds (ns)
Timing constraint: Default path analysis
Total number of paths / destination ports: 28 / 5
-------------------------------------------------------------------------
Delay: 7.898ns (Levels of Logic = 5)
Source: A<1> (PAD)
Destination: C (PAD)
Data Path: A<1> to C Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.106 0.532 A_1_IBUF (A_1_IBUF)
LUT4:I0->O 2 0.612 0.449 L2/C1 (W2)
LUT3:I1->O 2 0.612 0.449 L3/C1 (W3)
LUT3:I1->O 1 0.612 0.357 L4/C1 (C_OBUF)
OBUF:I->O 3.169 C_OBUF (C)
Total 7.898ns (6.111ns logic, 1.787ns route)
(77.4% logic, 22.6% route)
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 1.20 secs

Result:

Thus the Ripple carry Adder using Verilog Module in Xilinx ISE implemented and
verified.

42
Ex no: 11
IMPLEMENTATION OF BRUN MULTIPLIER
Date : 11-03-2024
15-04-23

Aim:

To implement the Brun Multiplier using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

module Half(Sum,Carry,A,B);
input A,B;
output Sum,Carry;
assign Sum=A^B;
assign Carry=A&B;
endmodule

module Fulladder(S,C,X,Y,Z);
input X,Y,Z;
output S,C;
assign S=X^Y^Z;
assign C=(X&Y)|(Z&(X^Y));
endmodule
module Braunmultiplier(output [7:0] y,input [3:0] a,b);
wire [2:0] sl0, cl0, sl1, cl1, sl2, cl2, cl3;
and a0_b0(y[0],a[0],b[0]);
and a0_b1(a0b1,a[0],b[1]);
and a0_b2(a0b2,a[0],b[2]);
and a0_b3(a0b3,a[0],b[3]);
and a1_b0(a1b0,a[1],b[0]);
and a1_b1(a1b1,a[1],b[1]);
and a1_b2(a1b2,a[1],b[2]);
and a1_b3(a1b3,a[1],b[3]);
and a2_b0(a2b0,a[2],b[0]);
43
and a2_b1(a2b1,a[2],b[1]);
and a2_b2(a2b2,a[2],b[2]);
and a2_b3(a2b3,a[2],b[3]);
and a3_b0(a3b0,a[3],b[0]);
and a3_b1(a3b1,a[3],b[1]);
and a3_b2(a3b2,a[3],b[2]);
and a3_b3(a3b3,a[3],b[3]);
//layer1
Half h1(y[1],cl0[0],a0b1,a1b0);
Half h2(sl
0[1],cl0[1],a1b1,a2b0);
Half h3(sl0[2],cl0[2],a2b1,a3b0);
//layer2
Fulladder fa1(y[2], cl1[0], a0b2, cl0[0], sl0[1]);
Fulladder fa2(sl1[1], cl1[1], a1b2, cl0[1], sl0[2]);
Fulladder fa3(sl1[2], cl1[2], a2b2, cl0[2], a3b1);
//layer3
Fulladder fa4(y[3], cl2[0], a0b3, cl1[0], sl1[1]);
Fulladder fa5(sl2[1], cl2[1], a1b3, cl1[1], sl1[2]);
Fulladder fa6(sl2[2], cl2[2], a2b3, cl1[2], a3b2);
//layer4
Half h4(y[4], cl3[0], cl2[0], sl2[1]);
Fulladder fa7(y[5], cl3[1], cl3[0], cl2[1], sl2[2]);
Fulladder fa8(y[6], y[7], cl3[1], cl2[2], a3b3);
Endmodule

44
Output:

45
Report:
Device utilization summary:
Selected Device : 7a30tcsg324-1
Slice Logic Utilization:
Number of Slice LUTs: 17 out of 21000 0%
Number used as Logic: 17 out of 21000 0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 17
Number with an unused Flip Flop: 17 out of 17 100%
Number with an unused LUT: 0 out of 17 0%
Number of fully used LUT-FF pairs: 0 out of 17 0%
Number of unique control sets: 0

IO Utilization:
Number of IOs: 16
Number of bonded IOBs: 16 out of 210 7%

Timing Report

Timing Summary:
---------------
Speed Grade: -1

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 5.370ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

Timing constraint: Default path analysis

Total number of paths / destination ports: 209 / 8
-------------------------------------------------------------------------
Delay: 5.370ns (Levels of Logic = 7)
Source: a<1> (PAD)
Destination: y<6> (PAD)

Data Path: a<1> to y<6>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 8 0.001 0.985 a_1_IBUF (a_1_IBUF)
LUT6:I0->O 3 0.124 0.550 fa2/C1 (cl1<1>)
LUT4:I2->O 2 0.124 0.925 fa5/Mxor_S_xo<0>1 (sl2<1>)
LUT5:I0->O 2 0.124 0.945 h4/Carry1 (cl3<0>)
LUT6:I0->O 2 0.124 0.945 fa7/C1 (cl3<1>)
LUT6:I0->O 1 0.124 0.399 fa8/Mxor_S_xo<0>1 (y_6_OBUF)
OBUF:I->O 0.000 y_6_OBUF (y<6>)
----------------------------------------
Total 5.370ns (0.621ns logic, 4.749ns route)
(11.6% logic, 88.4% route)
Result:

Thus the Brun Multiplier using Verilog Module in Xilinx ISE implemented and verified

46
Ex no: 12
IMPLEMENTATION OF WALLACE TREE MULTIPLIER
Date : 11-03-2024
22-04-23

Aim:

To implement the Wallace Tree Multiplier using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

module halfadd(Sum_half,Carry_half,A,B);
input A,B;
output Sum_half,Carry_half;
assign Sum_half=A^B;
assign Carry_half=A&B;
endmodule
module fulladd(S,C,X,Y,Z);
input X,Y,Z;
output S,C;
assign S=X^Y^Z;
assign C=(X&Y)|(Z&(X^Y));
endmodule
module wallacetree(input [3:0] a,b,output [7:0] p);
wire x0, x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,s1 ,s2, s3 ,s4,s5;
wire s6,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11;
assign x0 = a[3]&b[3];
assign x1 = a[3]&b[2];
assign x2 = a[2]&b[3];
assign x3 = a[2]&b[2];
assign x4 = a[1]&b[3];
assign x5 = a[3]&b[1];
assign x6 = a[1]&b[2];
assign x7 = a[0]&b[3];
assign x8 = a[3]&b[0];
47
assign x9 = a[2]&b[1];
assign x10 = a[1]&b[1];
assign x11 = a[0]&b[2];
assign x12 = a[2]&b[0];
assign x13 = a[1]&b[0];
assign x14 = a[0]&b[1];
assign x15 = a[0]&b[0];
halfadd ha2(s1,c1,x6,x7);
halfadd ha1(s2,c2,x3,x4);
fulladd fa3(s6,c6,x1,x2,c2);
fulladd fa2(s5,c5,s2,x5,c1);
fulladd(s4,c4,s1,x8,x9);
halfadd ha3(s3,c3,x10,x11);
halfadd ha4(p[1],c7,x13,x14);
fulladd fa4(p[2],c8,s3,x12,c7);
fulladd fa5(p[3],c9,s4,c3,c8);
fulladd fa6(p[4],c10,s5,c4,c9);
fulladd fa7(p[5],c11,s6,c5,c10);
fulladd fa8(p[6],p[7],x0,c6,c11);
assign p[0] = x15;
endmodule

48
Output:

Report:

Device utilization summary:

Selected Device : 7a30tcsg324-1

Slice Logic Utilization:
Number of Slice LUTs: 19 out of 21000 0%
Number used as Logic: 19 out of 21000 0%
49
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 19
Number with an unused Flip Flop: 19 out of 19 100%
Number with an unused LUT: 0 out of 19 0%
Number of fully used LUT-FF pairs: 0 out of 19 0%
Number of unique control sets: 0

IO Utilization:
Number of IOs: 16
Number of bonded IOBs: 16 out of 210 7%

Specific Feature Utilization:

Partition Resource Summary:

No Partitions were found in this design.

=======================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:

----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -1

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 4.744ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 208 / 8
-------------------------------------------------------------------------
Delay: 4.744ns (Levels of Logic = 7)
Source: a<2> (PAD)
Destination: p<6> (PAD)

Data Path: a<2> to p<6>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
50
 ---------------------------------------- ------------
IBUF:I->O 8 0.001 0.582 a_2_IBUF (a_2_IBUF)
LUT2:I0->O 2 0.124 0.542 x91 (x9)
LUT6:I4->O 2 0.124 0.925 _i000001/Mxor_S_xo<0>1 (s4)
LUT6:I1->O 3 0.124 0.730 fa5/C1 (c9)
LUT5:I2->O 2 0.124 0.945 fa7/C1 (c11)
LUT6:I0->O 1 0.124 0.399 fa8/Mxor_S_xo<0>1 (p_6_OBUF)
OBUF:I->O 0.000 p_6_OBUF (p<6>)
----------------------------------------
Total 4.744ns (0.621ns logic, 4.123ns route)
(13.1% logic, 86.9% route)

========================================================================
Cross Clock Domains Report:
========================================================================

Total REAL time to Xst completion: 3.00 secs

Total CPU time to Xst completion: 3.15 secs

Result:

Thus the Wallace Tree Multiplier using Verilog Module in Xilinx ISE implemented and
verified

51
Ex no: 13
IMPLEMENTATION OF RANDOM-ACCESS MEMORY
Date : 18-03-2024
29-04-23

Aim:

To implement the RAM 1024 using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

module Ram(datain,addr,dataout,RW,clk);
input RW,clk;
input [9:0]addr;
input [7:0]datain;
output [7:0]dataout;
reg [7:0]mem[0:1023];
reg [7:0]dataout;
always@(posedge clk)
begin
if (RW==1)
dataout<=mem[addr];
else
mem[addr]<=datain;
end
endmodule

Output:

52
Report:

Device utilization summary:

---------------------------

Selected Device : 7a30tcsg324-1

Slice Logic Utilization:

Number of Slice LUTs: 1 out of 21000 0%
Number used as Logic: 1 out of 21000 0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 1
Number with an unused Flip Flop: 1 out of 1 100%
Number with an unused LUT: 0 out of 1 0%
Number of fully used LUT-FF pairs: 0 out of 1 0%
Number of unique control sets: 0

IO Utilization:
Number of IOs: 28
Number of bonded IOBs: 28 out of 210 13%

Specific Feature Utilization:

Number of Block RAM/FIFO: 1 out of 52 1%
Number using Block RAM only: 1
Number of BUFG/BUFGCTRLs: 1 out of 32 3%

Timing Summary:
---------------
Speed Grade: -1

Minimum period: No path found

Minimum input arrival time before clock: 1.193ns
Maximum output required time after clock: 3.152ns
Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)
53
=======================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 20 / 20
-------------------------------------------------------------------------
Offset: 1.193ns (Levels of Logic = 1)
Source: datain<7> (PAD)
Destination: Mram_mem (RAM)
Destination Clock: clk rising
Data Path: datain<7> to Mram_mem
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.001 0.399 datain_7_IBUF (datain_7_IBUF)
RAMB18E1:DIADI7 0.793 Mram_mem
----------------------------------------
Total 1.193ns (0.794ns logic, 0.399ns route)
(66.6% logic, 33.4% route)
=======================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset: 3.152ns (Levels of Logic = 1)
Source: Mram_mem (RAM)
Destination: dataout<7> (PAD)
Source Clock: clk rising
Data Path: Mram_mem to dataout<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
RAMB18E1:CLKARDCLK->DOADO7 1 2.753 0.399 Mram_mem (dataout_7_OBUF)
OBUF:I->O 0.000 dataout_7_OBUF (dataout<7>)
----------------------------------------
Total 3.152ns (2.753ns logic, 0.399ns route)
(87.3% logic, 12.7% route)

Cross Clock Domains Report:

--------------------------
Cross Clock Domains Report:
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.14 secs

Total memory usage is 4548212 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)
Number of infos : 1 ( 0 filtered)

Result:

Thus the RAM 1024 using Verilog Module in Xilinx ISE implemented and verified

54
Ex no: 14
IMPLEMENTATION OF ARITHMETIC LOGIC UNIT (ALU)
Date : 18-03-2024
06-05-23

Aim:

To implement the Arithmetic logic unit (ALU) using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:

module ArithmeticUnit(S,A,B,Y);
input [2:0]S;
input A,B;
output Y;
reg Y;
always@(S,A,B)
begin
case(S)
3'b000: Y<=A|B;//Logical OR
3'b001: Y<=A&B;//Logical AND
3'b010: Y<=A^B;//Logical XOR
3'b011: Y<=~(A|B);//Logical NOR
3'b100: Y<=~(A&B);//Logical NAND
3'b101: Y<=A~^B;//Logical XNOR
3'b110: Y<=A-B;//Logical Subtraction
3'b111: Y<=A*B;//Logical Multiplication
endcase
end
endmodule

55
Output:

Report:

Device utilization summary

Slice Logic Utilization:
Number of Slice LUTs: 1 out of 21000 0%
Number used as Logic: 1 out of 21000 0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 1
Number with an unused Flip Flop: 1 out of 1 100%
Number with an unused LUT: 0 out of 1 0%
Number of fully used LUT-FF pairs: 0 out of 1 0%
Number of unique control sets: 0

56
IO Utilization:
Number of IOs: 6
Number of bonded IOBs: 6 out of 210 2%

Timing Report

Clock Information:
No clock signals found in this design
Asynchronous Control Signals Information:
No asynchronous control signals found in this design

Timing Summary:
Speed Grade: -1
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 1.443ns

Timing Details:
All values displayed in nanoseconds (ns)

=======================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 5 / 1
-------------------------------------------------------------------------
Delay: 1.443ns (Levels of Logic = 3)
Source: A (PAD)
Destination: Y (PAD)

Data Path: A to Y
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.001 0.919 A_IBUF (A_IBUF)
LUT5:I0->O 1 0.124 0.399 Mmux_Y_2_f7 (Y_OBUF)
OBUF:I->O 0.000 Y_OBUF (Y)
----------------------------------------
Total 1.443ns (0.125ns logic, 1.318ns route)
(8.7% logic, 91.3% route)

Cross Clock Domains Report:

=======================================================================
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.08 secs
Total memory usage is 4549300 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Result:

Thus the ALU using Verilog Module in Xilinx ISE implemented and verified

57
Ex no: 15
IMPLEMENTATION OF CMOS CODE
Date : 25-03-2024
13-05-23

Aim:

To implement the CMOS code using Verilog Module in Xilinx ISE.

Software Required:

● Xilinx ISE Design Suite.

Program:
module pmos1(y,vdd,a);
input a,vdd;
output y;
reg y;
always@(a)
begin
if (a==1)
y=0;
else
y=1;
end
endmodule
module nmos1(y,gnd,a);
input a,gnd;
output y;
reg y;
always@(a)
begin
if (a==1)
y=0;
else
y=0;
end
endmodule

58
 Main Program:
module cmosinv(a,y);
input a;
output y;
wire y1,y2;
supply0 gnd;
supply1 vdd;
pmos1 p1(y1,vdd,a);
nmos1 n1(y2,gnd,a);
assign {y}= y1 + y2;
endmodule

Output:

Device utilization summary:

---------------------------
Selected Device : 7a30tcsg324-1
Slice Logic Utilization:
Number of Slice LUTs: 1 out of 21000 0%
Number used as Logic: 1 out of 21000 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1
Number with an unused Flip Flop: 1 out of 1 100%
Number with an unused LUT: 0 out of 1 0%

59
 Number of fully used LUT-FF pairs: 0 out of 1 0%
Number of unique control sets: 0
IO Utilization:
Number of IOs: 2
Number of bonded IOBs: 2 out of 210 0%

Timing Details:
---------------
All values displayed in nanoseconds (ns)

========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 0.945ns (Levels of Logic = 3)
Source: a (PAD)
Destination: y (PAD)

Data Path: a to y
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.001 0.399 a_IBUF (a_IBUF)
INV:I->O 1 0.146 0.399 p1/y1_INV_0 (y1)
OBUF:I->O 0.000 y_OBUF (y)
----------------------------------------
Total 0.945ns (0.147ns logic, 0.798ns route)
(15.6% logic, 84.4% route)

Result:

Thus the CMOS Inverter using Verilog Module in Xilinx ISE implemented and verified

60
Ex no: 16
IMPLEMENTATION OF CMOS INVERTER
Date :20-05-23
02-04-2024

Aim:

To implement the CMOS inverter using EDA tool & analyse the characteristics.

Software Required:

● EDA (Micro Wind Simulator).

Circuit:

61
Layout:

Output:

62
Program:
// DSCH 2.7f
// 27-05-2023 14:54:09
// F:\Vivek\CMos Inverter.sch
module CMos Inverter( in1,out1);
input in1;
output out1;
nmos #(1) nmos(out1,vss,in1); // 1.0u 0.12u
pmos #(1) pmos(out1,vdd,in1); // 2.0u 0.12u
endmodule
// Simulation parameters in Verilog Format
always
#10 in1=~in1;
// Simulation parameters
// in1 CLK 10 10

Result:

Thus the CMOS inverter was implemented using EDA tool & analysed its characteristics

63
Ex no: 17
IMPLEMENTATION OF CMOS NAND
Date : 02-04-2024
20-05-23

Aim:

To implement the CMOS NAND using EDA tool & analyse the characteristics.

Software Required:

● EDA (Micro Wind Simulator).

Circuit:

64
Layout:

Output:

65
Program:
// DSCH 2.7f
// 27-05-2023 15:44:43
// F:\Vivek\CMos Nand 4 input.sch
module CMos Nand 4 input( in4,in2,in3,in1,out1);
input in4,in2,in3,in1;
output out1;
pmos #(1) pmos(out1,vdd,in1); // 2.0u 0.12u
pmos #(1) pmos(out1,vdd,in2); // 2.0u 0.12u
pmos #(1) pmos(out1,vdd,in3); // 2.0u 0.12u
pmos #(1) pmos(out1,vdd,in4); // 2.0u 0.12u
nmos #(1) nmos(out1,w6,in1); // 1.0u 0.12u
nmos #(1) nmos(w6,w7,in2); // 1.0u 0.12u
nmos #(1) nmos(w7,w8,in3); // 1.0u 0.12u
nmos #(1) nmos(w8,vss,in4); // 1.0u 0.12u
endmodule
// Simulation parameters in Verilog Format
always
#10 in4=~in4;
#20 in2=~in2;
#40 in3=~in3;
#80 in1=~in1;
// Simulation parameters
// in4 CLK 10 10
// in2 CLK 20 20
// in3 CLK 40 40
// in1 CLK 80 80

Result:

Thus the CMOS NAND was implemented using EDA tool & analysed its characteristics

66
Ex no: 18
IMPLEMENTATION OF PSEUDO CMOS NAND
Date : 10-04-2024
27-05-23

Aim:

To implement the PSEUDO CMOS NAND using EDA tool & analyse the characteristics.

Software Required:

● EDA (Micro Wind Simulator).

Circuit:

67
Layout:

Output:

68
Program:
// DSCH 2.7f
// 27-05-2023 16:19:04
// F:\Vivek\CMos PSEUDO.sch

module CMos PSEUDO( in1,in2,in3,in4,out1);

input in1,in2,in3,in4;
output out1;
pmos #(1) pmos(out1,vdd,vss); // 2.0u 0.12u
nmos #(1) nmos(out1,w2,in1); // 1.0u 0.12u
nmos #(1) nmos(w2,w4,in2); // 1.0u 0.12u
nmos #(1) nmos(w4,w6,in3); // 1.0u 0.12u
nmos #(1) nmos(w6,vss,in4); // 1.0u 0.12u
endmodule

// Simulation parameters in Verilog Format

always
#10 in1=~in1;
#20 in2=~in2;
#40 in3=~in3;
#80 in4=~in4;

// Simulation parameters
// in1 CLK 10 10
// in2 CLK 20 20
// in3 CLK 40 40
// in4 CLK 80 80

Result:

Thus the PSEUDO CMOS NAND was implemented using EDA tool & analysed its
characteristics.

69
Ex no: 19
IMPLEMENTATION OF DYNAMIC CMOS NAND
Date : 10-04-2024
27-05-23

Aim:

To implement the Dynamic CMOS NAND using EDA tool & analyse the characteristics.

Software Required:

● EDA (Micro Wind Simulator).

Circuit:

70
Layout:

Output:

71
Program:

Result:

Thus the Dynamic CMOS NAND was implemented using EDA tool & analysed its
characteristics.

72
Ex no: 20
IMPLEMENTATION OF CMOS NAND/AND IN CASCODE
VOLTAGE SWITCH LOGIC
Date : 18-04-2024
27-05-23

Aim:

To implement the CMOS NAND/AND in cascode voltage switch logic using EDA tool &
analyse the characteristics.

Software Required:

● EDA (Micro Wind Simulator).

Circuit:

Layout:

73
Output:

74
Program:
// DSCH 2.7f
// 01-06-2023 23:44:24
module CMOS NAND-AND( in1,in2,out1,out2);
input in1,in2;
output out1,out2;
pmos #(1) pmos(out1,vdd,out2); // 2.0u 0.12u
pmos #(1) pmos(out2,vdd,out1); // 2.0u 0.12u
nmos #(1) nmos(out1,vss,w3); // 1.0u 0.12u
nmos #(1) nmos(out1,vss,w4); // 1.0u 0.12u
nmos #(1) nmos(w3,vss,in1); // 1.0u 0.12u
pmos #(1) pmos(w3,vdd,in1); // 2.0u 0.12u
pmos #(1) pmos(w4,vdd,in2); // 2.0u 0.12u
nmos #(1) nmos(w4,vss,in2); // 1.0u 0.12u
nmos #(1) nmos(out2,w7,in1); // 1.0u 0.12u
nmos #(1) nmos(w7,vss,in2); // 1.0u 0.12u
endmodule

// Simulation parameters in Verilog Format

always
#10 in1=~in1;
#20 in2=~in2;

// Simulation parameters
// in1 CLK 10 10
// in2 CLK 20 20

Result:

Thus the CMOS NAND/AND in cascode voltage switch logic was implemented using
EDA tool & analysed its characteristics.

75