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8051 Memory Organization - Introduction

• Memory organization- Memory Unit inside and outside the CPU of

8051

• The 8051 has

– Inbuilt memory and also

– External memory unit can be interfaced to it.

– Inbuilt memory Read/Write memory of 256 Byes (Upgraded) and

Read-only-memory of 4 KB.

– External Memory of 64 KB of Read/Write Memory and 64 KB of

Read-only-Memory

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 Memory Unit (internal and External)

Memory (8051)

Internal Memory External Memory

Read/Write Memory Read Only Memory

Read/Write Memory Read Only Memory
(R/W) (ROM)
(R/W) (ROM)
64 KB – 4 KB** 65536 Byte
256 Bytes 4 KB
(60 KB) (64 KB)

** 4 KB is internal ROM. This shall be explained while External RAM is explained

Read/Write memory is Generally called as RAM
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 8051-Memory Unit Interfacing

8051 CPU PSEN

Internal RAM 8 bit internal Address/ Data bus OE

R/W memory External ROM

256 Bytes 64 KB
Addresses Addresses
00 - FF 0000-FFFF

Port 2 & Port 0 16 bit External Address bus

Port 0 8 bit External Data bus

Internal ROM External RAM

4096 Bytes R/W memory
Port 3 WR WR
Addresses 60 KB
RD OE
0000-0FFF Addresses
16 bit internal Address/ Data bus
1000 - FFFF

OE-OUTPUT ENABLE, PSEN- PROGRAM STORE ENABLE, RD-READ, WR,WRITE

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256 Bytes of 64 KB of 64 KB of
Internal RAM External ROM External RAM

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8051- Registers and Internal Memory

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Dayanandhan K, Sathyabama Institute of Science and Technology
 8051- Internal Memory

Internal Memory

Read/Write Memory Read Only Memory

(R/W) (ROM)
256 Bytes 4 KB

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 8051- Internal RAM Memory

Internal
Memory

Read/Write Memory
(R/W)
256 Bytes

In earlier version of 8051, internal READ/WRITE memory is 128 Bytes

But in Upgraded version it is 256 Bytes 8
 8051- Internal RAM Memory

Internal Memory

Read/Write Memory
(R/W)
128 Bytes 128 Bytes
256 Bytes
Address Address
00 H to 7F H 80 H to FF H

128 Bytes of Read-Write Memory (RAM)

128 Bytes of Read-Write Memory (RAM)

Special Function Registers (SFR)
In earlier version of 8051, internal READ/WRITE memory is 128 Bytes
But in Upgraded version it is 256 Bytes
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 8051- Internal RAM Memory
80 Bytes
7F H Address
Internal Memory The 128 Bytes internal
30 H to 7F H
General RAM is divided into

Read/Write Memory
Purpose three portions.
(R/W) Registers 1. 32 Bytes of Bank
256 Bytes
16 Bytes registers
128 Bytes Address 2. 16 Bytes of Bit-
20 H to 1F H Addressable
Bit
Address Registers
Addressable
00 H to 7F H Registers
3. 80 Bytes of General
Purpose Registers

32 Bytes
Address
00 H to 1F H
00 H Bank registers
128 Bytes of Read-Write Memory (RAM)

In earlier version of 8051, internal READ/WRITE memory is 128 Bytes

But in Upgraded version it is 256 Bytes
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 8051- Internal RAM- Bank Registers

Internal Memory 32 Bytes Bank registers are divided into 4 banks.

Bank 0, 1, 2 and 3 each containing 8 registers from R0 to R7
Each are of 8 bit storage (1 Byte storage)
Read/Write Memory
(R/W)
256 Bytes

Addresses
Bank 0 Addresses
Bank 1 Addresses
Bank 2 Addresses
Bank 3
07 H R7 0F H R7 17 H R7 1F H R7
06 H R6 0E H R6 16 H R6 1E H R6
05 H R5 0D H R5 15 H R5 1D H R5
04 H R4 0C H R4 14 H R4 1C H R4
03 H R3 0B H R3 13 H R3 1B H R3
02 H R2 0A H R2 12 H R2 1A H R2
01 H R1 09 H R1 11 H R1 19 H R1
00 H R0 08 H R0 10 H R0 18 H R0
8 Bytes of 8 Bytes of 8 Bytes of 8 Bytes of
Bank 0 registers Bank 1 registers Bank 2 registers Bank 3 registers

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 For selecting a particular Bank, PSW register to be used.
The PSW Register
• Program Status Word is a “bit addressable” 8-bit register that has all the flags.
MSB LSB
PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0
CY AC F0 RS1 RS0 OV - P

Symbol Position Function

CY PSW.7 Carry Flag
AC PSW.6 Auxiliary Carry Flag. For BCD Operations
F0 PSW.5 Flag 0. Available to the user for general purposes.
RS1 PSW.4 Register bank select bits. Set by software to
determine which register bank is being used.
RS0 PSW.3
OV PSW.2 Overflow Flag
- PSW.1 Not used
P PSW.0 Parity Flag. Even Parity.

• Bit 3 & 4 (PSW.3 & PSW.4), RS0 & RS1, decides the Bank selection.
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• Program Status Word is a “bit addressable” 8-bit register that has all the flags.
MSB LSB
PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0
CY AC F0 RS1 RS0 OV - P

RS1 RS0 Bank Selected

0 0 Bank 0 – 1st Bank
0 1 Bank 1 – 2nd Bank
1 0 Bank 2 – 3rd Bank
1 1 Bank 3 – 14th Bank

• Default Bank is 1st Bank – Bank 0

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 8051- Internal RAM- Bank Registers
MSB LSB
Internal Memory
PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0
CY AC F0 RS1 RS0 OV - P
Read/Write Memory X X X 0 0
1 X X X
(R/W)
256 Bytes
RS1 RS0 Bank Selected SETB PSW.3 SETB The bit PSW.3 is SET-RS0=1
0 0
1 0–2
Bank 1 1nd
st Bank
Bank CLR PSW.4 CLR The bit PSW.4 is RESET-RS1=0
Instructions for Changing Bank registers
Selected bank

Bank 0 Addresses
Bank 1 Addresses
Bank 2 Addresses
Bank 3
Addresses
07 H R7 0F H R7 17 H R7 1F H R7
06 H R6 0E H R6 16 H R6 1E H R6
05 H R5 0D H R5 15 H R5 1D H R5
04 H R4 0C H R4 14 H R4 1C H R4
03 H R3 0B H R3 13 H R3 1B H R3
02 H R2 0A H R2 12 H R2 1A H R2
01 H R1 09 H R1 11 H R1 19 H R1
00 H R0 08 H R0 10 H R0 18 H R0
8 Bytes of 8 Bytes of 8 Bytes of 8 Bytes of 14
Bank 0 registers Bank 1 registers Bank 2 registers Bank 3 registers
 BYTE 8051- Internal RAM- Bit Addressable Registers
ADDRESS
BIT ADDRESSES 16 BYTES OF BIT-ADDRESSABLE
2F 7F 7E 7D 7C 7B 7A 79 78
BYTE ADDRESSING
2E 77 76 75 74 73 72 71 70 To write data 94H, in byte address 20,
MOV 20, #94H
2D 6F 6E 6D 6C 6B 6A 69 68 Where 20 is the address and 94H is the data, as
shown in the figure below.
2C 67 66 65 64 63 62 61 60
This is termed as Byte Addressing, since 1
2B 5F 5E 5D 5C 5B 5A 59 58 byte of data is addressed.

2A 57 56 55 54 53 52 51 50 07 06 05 04 03 02 01 00

29 4F 4E 4D 4C 4B 4A 49 48 20 1 0 0 1 0 1 0 0

28 47 46 45 44 43 42 41 40
BIT ADDRESSING
27 3F 3E 3D 3C 3B 3A 39 38 To write bit 1, in bit address 03,
SETB 03H
26 37 36 35 34 33 32 31 30
Where the bit address 03H, is SET with bit 1
25 2F 2E 2D 2C 2B 2A 29 28 and
This is termed as Bit Addressing, since 1 bit of
24 27 26 25 24 23 22 21 20 address is addressed.
23 1F 1E 1D 1C 1B 1A 19 18
07 06 05 04 03 02 01 00
22 17 16 15 14 13 12 11 10

21 0F 0E 0D 0C 0B 0A 09 08 20 1 0 0 1 1 1 0 0

20 07 06 05 04 03 02 01 00
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16 BYTES OF BIT-ADDRESSABLE REGISTERS
 8051- Internal RAM- General Purpose Registers

Internal Memory
The General Purpose Registers are BYTE
ADDRESSABLE only
Addresses
7F H To write data 3AH, in byte address 50,
Read/Write Memory
(R/W)
256 Bytes MOV 50, #3AH

Where 50 is the address and 3AH is the data, as

shown in the figure beside.

80 bytes

30 H

80 Bytes of
General Purpose registers

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 8051- Internal RAM- Special Function Registers
(SFR)
Internal Memory

Read/Write Memory
(R/W)
256 Bytes

• ACC and B registers – 8 bit each

• DPTR : [DPH:DPL] – 16 bit
combined
• PC (Program Counter) – 16 bits
• SP (Stack Pointer) – 8 bit
• PSW (Program Status Word)
• Port Latches
• Serial Data Buffer
• Timer Registers
• Control Registers

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8051- Internal RAM- Special Function Registers (SFR)

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Dayanandhan K, Sathyabama Institute of Science and Technology
 The ACC – Accumulator
• Commonly used for move and arithmetic instructions.
• Can be referred to in several ways:
– Implicitly in op-codes.
– Referred to as ACC (or A) for instructions that allow specifying a
register.
– By its SFR address 0E0H.

• Operates in a similar manner to the 8085 accumulator.

• Bit addressable.
– ACC.2 means bit 2 of the ACC register.

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 The B Register
• Commonly used as a temporary register, much like a 9th
R register.
• Used by two op-codes
– MUL AB, DIV AB
• B register holds the second operand and will hold part of
the result
– Upper 8 bits of the multiplication result
– Remainder in case of division.

• Can also be accessed through its SFR address of 0F0H.

• Bit addressable.

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 The DPL and DPH Registers
• 2 8-bit registers that can be combined into a 16-bit DPTR – Data
Pointer.
• Used by commands that access external memory
• Also used for storing 16bit values
mov DPTR, #data16
; setup DPTR with 16bit ext address
movx A, @DPTR
; copy mem[DPTR] to A

• Can be accessed as 2 separate 8-bit registers if needed.

• DPTR is useful for string operations and Look-Up-Table (LUT)
operations.
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 The SP Register
• SP is the stack pointer.
• SP points to the last used location of the stack.
– Push operation will first increment SP and then copy data.
– Pop operation will first copy data and then decrement SP.
• In 8051, stack grows upwards (from low memory to high memory)
and can be in the internal RAM only.
• On power-up, SP points to 07H.
– Register banks 2,3,4 (08H to 1FH) form the default stack area.

• Stack can be relocated by setting SP to the upper memory area in

30H to 7FH.
– mov SP, #32H

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 The PSW Register
• Program Status Word is a “bit addressable” 8-bit register
that has all the flags.
MSB LSB
CY AC F0 RS1 RS2 OV - P

Symbol Position Function

CY PSW.7 Carry Flag
AC PSW.6 Auxiliary Carry Flag. For BCD
Operations
F0 PSW.5 Flag 0. Available to the user for general
purposes.
RS1 PSW.4 Register bank select bits. Set by
RS2 PSW.3 software to determine which register
bank is being used.
OV PSW.2 Overflow Flag
- PSW.1 Not used
P PSW.0 Parity Flag. Even Parity. 23
 The P0, P1, P2, and P3 Registers
• Port Latches.
• Specify the value to be output on the specific output port
or the value read from the specific input port.

• Bit addressable.
– First bit has the same address as the register.
– Example: P1 has address 90H in the SFR, so
• P1.7 or address 97H refer to the same bit.

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 The SBUF Register
• Serial Port Data Buffer.
• 2 registers at the same location
– One is read-only used for reading serial input
data.
• Serial Data Receive Buffer.
– The other is write-only used for storing serial
output data.
• Serial Data Transmit Buffer.

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 Timer Registers – T0 and T1
• The high and low bytes of the 16-bit down counting
register for timer/counter T0.
• Timer T0, consists of two 8 bit timer registers TL0 and
TH0.
• There is also a TH1 / TL1 pair for the T1 timer.
• There are several modes to operate both the timers.

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 Control Registers
• IP – Interrupt Priority.
• IE – Interrupt Enable.
• TMOD – Timer Mode.
• TCON – Timer Control.
• T2CON – Timer 2 Control (8052)
• SCON – Serial Port Control.
• PCON – Power Control (80C51).

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 8051- Internal Memory- ROM

Internal Memory

Read Only Memory

(ROM)
4 KB
Addresses
0000 -0FFF 28
 8051- Internal Memory- ROM
0FFF H
Internal Memory

Read Only Memory

(ROM) Internal ROM
4 KB
Addresses
4 K Bytes
0000 -0FFF

Address
 4 Kilo Bytes of Internal Read-Only Memory (ROM), accessed by 0000 H to 0FFF H
internal 16 bit address bus and 8-bit data bus.
 Only reading is possible from this ROM. Interrupt vector
addresses, are allotted in this ROM only.
 The address ranges from 0000H to 0FFFH as shown in the
0000 H
figure beside.
4 KB of Read Only Memory (ROM)
 This ROM shares address with external RAM.
 External RAM has address from 1000H to FFFFH (60 KB)
 Pin EA shall be 1 for access of internal ROM

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 8051- Internal RAM- STACK

Internal Memory • Bank 0 doesn’t involve in STACK operation. Only other Banks
are involved in stack operation.

Read/Write Memory
• Stack Pointer SP (8 Bit-Register) by default stores value 07H
(R/W)
256 Bytes
in it. The stack starts from 08H to FFH
• As stack is loaded by Push instructions, SP increases from
07 to FF and POP instruction decreases SP by one.

Addresses
Bank 1 Addresses
Bank 2 Addresses
Bank 3
0F H R7 17 H R7 1F H R7
0E H R6 16 H R6 1E H R6
0D H R5 15 H R5 1D H R5
0C H R4 14 H R4 1C H R4
0B H R3 13 H R3 1B H R3
0A H R2 12 H R2 1A H R2
09 H R1 11 H R1 19 H R1
08 H R0 10 H R0 18 H R0
SP=07 8 Bytes of 8 Bytes of 8 Bytes of 30
Bank 1 registers Bank 2 registers Bank 3 registers
 8051- External Memory

External Memory

Read/Write Memory Read Only Memory

(R/W) (ROM)
64 KB – 4 KB** 65536 Byte
(60 KB) (64 KB)
Address Address
1000H – FFFFH 0000H - FFFFH
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 8051- External Memory-Read only Memory

External Memory

 External ROM of 64 Kilo Bytes of Read-Only Memory (ROM),

Read Only Memory accessed by external 16 bit address bus and 8-bit data bus.
(ROM)


65536 Byte
(64 KB) Only reading is possible from this ROM. User can once write a
Address
0000H - FFFFH Program using this ROM. This is called Program or Code
memory unit.
 The address ranges from 0000H to FFFFH as shown in the
figure beside.
 The instruction used to access this ROM is
 MOVC A, @DPTR
 Here DPTR (Data-Pointer) is used to access the address
stored in Data-Pointer. MOVC is a special MNEMONIC
used for External ROM.
 Only Read can be done since it is a ROM and the
instruction cannot be MOVC @DPTR, A.
 Pin EA shall be 0 for access of external ROM

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 8051- Possible Questions

 Describe briefly about the memory organization in 8051.

 Elaborately brief the internal memory units of 8051.
 Elaborately brief the 128 bytes of internal RAM of 8051
 Elaborately brief the SFRs of internal RAM of 8051

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