An internship report

on
VLSI
Submitted in partial fulfillment of the requirement for
The award of the degree

BACHELOR OFTECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING

By

SRAVANI KATTEKOTA

20NN1A0435

DEPARTMENT OF ELECTRONIC AND COMMUNICATION

ENGINEERING
VIGNAN’S NIRULA INSTITUTE OF TECHNOLOGY AND SCIENCE FOR
WOMEN
(Approved by AICTE, NEWDELHI and Affiliated to JNTUK KAKINADA)
PEDAPALAKALURU, GUNTUR-522005
 Official Certificate

Signature of Head of the Department External Examiner

Dr. G. Sandhya
Associate Professor
 DECLARATION
I, hereby declare that the work described in this Internship, entitled “VLSI
DESIGN” which is submitted by us in partial fulfillment of the academic requirement in
Bachelor of Technology in the department of ELECTRONICS AND COMMUNICATION
ENGINEERING of VIGNAN’S NIRULA INSTITUTE OF TECHNOLOGY AND
SCIENCE FOR WOMEN, affiliated to JNTU, Kakinada, Andhra Pradesh is the result of
work done by SRAVANI KATTEKOTA [20NN1A0435].
This is certified that the above statement made by the candidate is correct to the
best of my knowledge.

K. SRAVANI
20NN1A0435
 ACKNOWLEDGEMENT

The completion of any internship depends upon the cooperation, coordination and
combined efforts of several sources of knowledge. This report acknowledgements a
number guidance, supervision, stimulation and a lot of inspiration from numerous people.
First of all, we thank the almighty for the blessings that have been showered upon
us to complete this internship successfully. Our grateful regards to our beloved principle,
Dr. P. Radhika for her constant support and motivation.
We take this opportunity to express our gratitude to Dr. G. Sandhya, Head of the
Department of Electronics and Communication Engineering for her great help and
encouragement to do this project work.
We are grateful to all the lecturers who have directly or indirectly helped in our
internship. We pay our respects and love to our parents and friends for their encouragement
throughout our work.
At last, we end up by thanking all who helped us in finalizing the internship within
the limited time frame.
 Contents
Chapter 1......................................................................................................................... 1

Introduction ................................................................................................................. 1

Chapter 2......................................................................................................................... 5

VLSI design verification using Verilog HDL ............................................................. 5

Chapter 3......................................................................................................................... 7

Combinational and Sequential Logic design .............................................................. 7

Chapter 4....................................................................................................................... 10

Flipflops and Latches ................................................................................................ 10

Chapter 5....................................................................................................................... 16

UART ....................................................................................................................... 16

Chapter 6....................................................................................................................... 19

ALU .......................................................................................................................... 19

Chapter 7....................................................................................................................... 25

Verification and System Verilog (SV) ....................................................................... 25

 LIST OF FIGURES
Figure 1 Common in Vlsi................................................................................................ 1

Figure 2 Vlsi Design cycle .............................................................................................. 2

Figure 3 A combinational circuit containing two inputs and four outputs ...................... 7

Figure 4 JK Flipflop ...................................................................................................... 12

Figure 5 D Flipflop ....................................................................................................... 13

Figure 6 T Flipflop ........................................................................................................ 13

Figure 7 SR Flipflop ..................................................................................................... 15

Figure 8 SR latch........................................................................................................... 15

Figure 9 UART ............................................................................................................. 16

Figure 10 Frame Format ............................................................................................... 17

Figure 11 Parity bit........................................................................................................ 18

Figure 12 ALU ............................................................................................................. 19

Figure 13 ALU Signals ................................................................................................. 21

Figure 14 Output waveform .......................................................................................... 24

 Chapter 1

Introduction

1.1 Introduction of VLSI system design :

What is VLSI Design:-
VLSI Design - Also known as Very Large Scale Integration(VLSI) or
Semiconductor Engineering Process of creating an Integrated Circuit(IC) by
combining billions of transistors into a single chip IC design started off with 2
transistors in 1960s to billions of transistors in today's devices.
What do all these have in common ?

Figure 1:common in vlsi

In our modern world, just about everything is woven together by electronics.
From microwaves to satellites, electronics-powered devices are infused into our every
waking moment. Today, even our sleep includes digital acoustics, haptics, and
analytics. But while the systems that light, connect, and move our lives can vary
greatly, nearly every electronic device has one or more of the same fundamental
building block the very small and very complex integrated circuit. An integrated

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circuit (IC) commonly called a chip is made out of a semiconductor material called
silicon, in which small electronic components called transistors are formed within the
silicon and then wired together with interconnects layered on top of the silicon surface.
VLSI Design Cycle :

Figure 2:Vlsi Design cycle

1.2 VLSI Technology :

VLSI began in the 1970s when MOS integrated circuit (Metal Oxide
Semiconductor) chips were developed and then widely adopted, enabling complex
semiconductor and telecommunication technologies.
Very large-scale integration is a process of embedding or integrating hundreds
of thousands of transistors onto a singular silicon semiconductor microchip. VLSI
technology's conception dates back to the late 1970s when advanced level processor
(computer) microchips were also in their development stages. Two of the most common
VLSI devices are the microprocessor and the microcontroller.
VLSI refers to an integrated circuit technology with numerous devices on a
single chip. The term originates, of course, in the 1970s, along with various other scale
integration classifications based on the number of gates or transistors per IC.
The remarkable growth of the electronics industry is primarily due to the
advances in large-scale integration technologies. With the arrival of VLSI designs, the
number of possibilities for ICs in control applications, telecommunications, high-
performance computing, and consumer electronics as a whole continues to rise.

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 Presently, technologies like smartphones and cellular communications afford
unprecedented portability, processing capabilities, and application access due to VLSI
technology. The forecast for this trend indicates a rapid increase as demands continue
to increase.

1.3 The Design Process of a VLSI IC :

Overall, VLSI IC design incorporates two primary stages or parts:

1. Front-End Design: This includes digital design using a hardware description

language, for example, Verilog, System Verilog, and VHDL. Furthermore, this
stage encompasses design verification via simulation and other verification
techniques. The entire process also incorporates designing, which starts with the
gates and continues through to design for testability.

2. Back-End Design: This consists of characterization and CMOS library design.

Additionally, it involves fault simulation and physical design.

The entire design process follows a step-by-step approach, and the following are the
front-end design steps:

• Problem Specification: This is a high-level interpretation of a system. We

address the key parameters, such as design techniques, functionality,
performance, fabrication technology, and physical dimensions. The final
specifications include the power, functionality, speed, and size of the VLSI
system.
• Architecture Definition: This includes fundamental specifications such as
floating-point units and which system to use, such as RISC or CISC and ALU's
cache size.
• Functional Design: This recognizes the vital functional units of a system and,
thus, enables identification of each unit's physical and electrical specifications
and interconnect requirements.
• Logic Design: This step involves control flow, Boolean expressions, word
width, and register allocation.

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 • Circuit Design: This step performs the realization of the circuit in the form of a
netlist. Since this is a software step, it utilizes simulation to check the outcome.
• Physical Design: In this step, we create the layout by converting the netlist into
a geometrical depiction. This step also follows some preconceived static rules,
such as the lambda rules, which afford precise details of the ratio, spacing
between components, and size.

The following are the back-end design steps for hardware development:

• Wafer Processing: This step utilizes pure silicon melted in a pot at 1400º C.
Then, a small seed comprising the required crystal orientation is injected into
liquefied silicon and gradually pulled out, 1mm per minute. We manufacture the
silicon crystal as a cylindrical ingot and cut it into discs or wafers before
polishing and crystal orientation.
• Lithography: This process (photolithography) includes masking with photo
etching and a photographic mask. Next, we apply a photoresist film on the wafer.
A photo aligner then aligns the wafer to a mask. Finally, we expose the wafer to
ultraviolet light, thus highlighting the tracks through the mask.
• Etching: Here, we selectively remove material from the surface of the wafer to
produce patterns. With an etching mask to protect the essential parts of the
material, we use additional plasma or chemicals to remove the remaining
photoresist.
• Ion Implantation: Here, we utilize a method to achieve a desired electrical
characteristic in the semiconductor, i.e., a process of adding dopants. The
process uses a beam of high-energy dopant ions to target precise areas of the
wafer. The beam's energy level determines the depth of wafer penetration.
• Metallization: In this step, we apply a thin layer of aluminum over the entire
wafer.
• Assembly and Packaging: Every one of the wafers contains hundreds of chips.
Therefore, we use a diamond saw to cut the wafers into single chips. Afterward,
they receive electrical testing, and we discard the failures. In contrast, those that
pass receive a thorough visual inspection utilizing a microscope. Finally, we
package the chips that pass the visual inspection as well as recheck them.

4
 Chapter 2

VLSI design verification using Verilog HDL

VLSI (Very Large Scale Integration) design verification is a crucial step in the
development of integrated circuits. It involves checking that the design correctly
implements the desired functionality and meets all specified constraints. One of the
most commonly used languages for VLSI design and verification is Verilog HDL
(Hardware Description Language).

Here are some key points about VLSI design verification using Verilog HDL:

1. Verilog HDL: Verilog is a hardware description language used for modeling

digital circuits. It allows designers to describe the structure and behavior of a
digital system1.
2. Levels of Abstraction: Verilog supports design at various levels of abstraction,
including the behavioural level, register-transfer level, and gate level1. This
flexibility allows designers to choose the level of detail that best suits their
needs.
3. Simulation and Testbenches: Verification often involves simulating the design
with a testbench, which is a model of the environment in which the design
operates. The testbench generates input signals for the design and checks the
design’s outputs against expected results2.
4. Design Examples: Real-world examples of VLSI design using Verilog might
include designing a microprocessor, a memory unit, or a network switch1.
Each of these designs would require a thorough verification process to ensure
correct functionality.
5. Tools and Resources: There are many tools available for VLSI design and
verification with Verilog, such as the High-Frequency Structure Simulator
(HFSS). These tools can help designers create more efficient and reliable
designs3.

5
Here are some additional points:
• Behavioural Level Verification: At this level, Verilog is used to verify the
design’s functionality without considering its structure. It involves writing
testbenches that simulate the behaviour of the digital system.
• Register-Transfer Level (RTL) Verification: RTL verification checks the logic
of the design at a level where operations and data transfers between registers
are described. This is often where most of the functional verification is
performed.
• Gate Level Verification: After RTL verification, the design is synthesized to a
gate-level netlist, which is then verified to ensure that the synthesis process
has not introduced any errors.
• Testbenches: A critical component of Verilog verification, testbenches are used
to apply stimuli to the design under test and check its response against
expected outcomes.
• Simulation Tools: Tools like ModelSim or VCS are used to simulate Verilog
testbenches and provide a dynamic environment for verification.

6
 Chapter 3

Combinational and Sequential Logic design

What Is a Combinational Circuit?

Combinational circuits are a kind of digital logic circuit whose instantaneous output
depends only on the combination of its inputs. For example, a combinational circuit
could be used to add any number of inputs, or to subtract them, or to perform other
mathematical operations. In fact, one of the main applications of combinational
circuits is to perform something called ''Boolean Algebra,'' which refers to the
performance of basic mathematical operations with binary numbers.

Figure 3:A combinational circuit containing two inputs and four outputs.

A combinational circuit typically has several inputs along with one or more
outputs. Because it is a digital circuit, the values of the inputs must either be 0 or 1. The
value of the outputs must also be a 0 or 1. An Adder circuit would take the instantaneous
values of all the inputs, add them together, and output the sum of the inputs. If the inputs
are changed, the output will also change nearly instantaneously. Unlike sequential logic

7
circuits, combinational circuits do not have memory; their outputs depend solely on the
current state of the inputs.

The invention of the combinational circuit, along with their ability to perform Boolean
Algebra, has been an essential part of the digital revolution.

Sequential logic design

A Sequential logic circuit is a form of the binary circuit; its design employs one
or more inputs and one or more outputs, whose states are related to some definite rules
that depend on previous states. Both the inputs and outputs can reach either of the two
states: logic 0 (low) or logic 1 (high). In these circuits, their output depends not only
on the combination of the logic states at its inputs but moreover on the logic states
that existed previously. In other words, their output depends on a SEQUENCE of the
events occurring at the circuit inputs. Examples of such circuits include clocks, flip-
flops, bi-stables, counters, memories, and registers. The actions of the sequential
circuits depend on the range of basic sub-circuits.

What is a Sequential Logic Circuit?

A sequential circuit is a logical circuit, where the output depends on the present
value of the input signal as well as the sequence of past inputs. While a combinational
circuit is a function of present input only. A sequential circuit is a combination of a
combinational circuit and a storage element. the sequential circuits use current input
variables and previous input variables which are stored and provide the data to the
circuit on the next clock cycle.
Design Procedure of Sequential Logic Circuits
1. This procedure involves the following steps
2. First, derive the state diagram
3. Take as the state table or an equivalence representation, such as a state
diagram.
4. The number of states may be reduced by the state reduction technique
5. Verify the number of flip-flops needed
6. Choose the type of flip-flops to be used

8
 7. Derive excitation equations
8. Using the map or some other simplification method, derive the output
function and the flip-flop input functions.
9. Draw a logic diagram or a list of Boolean functions from which a logic
diagram can be obtained.
Categories of Sequential Logic Circuits
Sequential logic circuits are divided into three categories like following.

• Event-Driven
• Clock Driven
• Pulse Driven

Event-Driven: Asynchronous circuits that can change the state immediately when
enabled. Asynchronous (fundamental mode) sequential circuit: The behavior is
dependent on the arrangement of the input signal that changes continuously over time,
and the output can be changed at any time (clockless).

Clock Driven: Synchronous circuits that are synchronized to a specific clock signal.
Synchronous (latch mode) sequential circuit: The behavior can be defined from the
knowledge of circuits that achieve synchronization by using a timing signal called the
clock.

Pulse Driven: This is a mixture of the two that responds to the triggering pulses.

9
 Chapter 4

Flipflops and Latches

4.1 What is Flipflop?

A flip flop in digital electronics is a circuit with two stable states that can be used to
store binary data. The stored data can be changed by applying varying inputs. Flip-flops
and latches are fundamental building blocks of digital electronics systems used in
computers, communications, and many other types of systems. Both are used as data
storage elements.
A flip-flop is a type of circuit that can store and recall a single bit of information. Its
name comes from its ability to “flip” or “flop” between two stable states. By latching a
value and changing it when triggered by a clock signal, flip-flops can store data over time.
They are called flip-flops because they have two stable states and switch between them
based on a triggering event.

4.2 What device is a flipflop?

A flip-flop is not a specific device but rather a term used to describe a group of
sequential logic circuits. These circuits made up of digital logic gates and other
components, can be created using different electronic elements like transistors, integrated
circuits (ICs), or programmable logic devices (PLDs).
Flip-flops play a critical role in computer electronics by serving as memory elements,
storing state information, ensuring clock synchronization, enabling digital counting, and
facilitating control logic. They are essential for data storage, sequencing, coordination,
and control within a computer system.

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4.3 Flipflop Types

There are basically 4 types of flip-flops in digital electronics:

1. SR Flip-Flop

2. JK Flip-Flop

3. D Flip-Flop

4. T Flip-Flop

SR Flipflop:

This is the most common flip-flop among all. This simple flip-flop circuit has a set input (S)
and a reset input (R). In this system, when you Set “S” as active, the output “Q” would be
high, and “Q” would be low. Once the outputs are established, the wiring of the circuit is
maintained until “S” or “R” go high, or power is turned off.

Truth table:
S R Q Q’
0 0 0 1
0 1 0 1
1 0 1 0
1 1 ∞ ∞

JK Flipflop:
Due to the undefined state in the SR flip-flops, another flip-flop is required in electronics. The
JK flip-flop is an improvement on the SR flip-flop where S=R=1 is not a problem.

11
 Figure 4:JK Flipflop

The input condition of J=K=1 gives an output inverting the output state. However, the outputs
are the same when one tests the circuit practically.
If J and K data input are different (i.e. high and low), then the output Q takes the value
of J at the next clock edge. If J and K are both low, then no change occurs. If J and K
are both high at the clock edge, then the output will toggle from one state to the other.
JK Flip-Flops can function as Set or Reset Flip-flops.
Truth Table:
J K Q Q’
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 1
0 0 1 1
0 1 1 0
1 0 1 1
1 1 1 0

D Flipflop:
D flip-flop is a better alternative that is very popular with digital electronics. They are
commonly used for counters and shift registers and input synchronization.

12
 Figure 5:D Flipflop

In the D flip-flops, the output can only be changed at the clock edge, and if the input changes
at other times, the output will be unaffected.
Truth Table:
D Q Q’

0 0 1
0 0 1

1 0 1

1 1 0

T Flipflop:
A T flip-flop is like a JK flip-flop. These are basically single-input versions of JK flip-flops.
This modified form of the JK is obtained by connecting inputs J and K together. It has only
one input along with the clock input.

Figure 6:T Flipflop

13
These flip-flops are called T flip-flops because of their ability to complement their state i.e.
Toggle, hence they are named Toggle flip-flops.
Truth Table:
T Q Q (t+1)

0 0 0

1 0 1

0 1 1

1 1 0

4.4 Latches:
Latches are digital circuits that store a single bit of information and hold its value
until it is updated by new input signals. They are used in digital systems as temporary
storage elements to store binary information. Latches can be implemented using various
digital logic gates, such as AND, OR, NOT, NAND, and NOR gates.
There are two types of latches:
1. S-R (Set-Reset) Latches: S-R latches are the simplest form of latches and are
implemented using two inputs: S (Set) and R (Reset). The S input sets the output
to 1, while the R input resets the output to 0. When both S and R are at 1, the

latch is said to be in an “undefined” state.

2. D (Data) Latches: D latches are also known as transparent latches and are
implemented using two inputs: D (Data) and a clock signal. The output of the
latch follows the input at the D terminal as long as the clock signal is high.
When the clock signal goes low, the output of the latch is stored and held until

the next rising edge of the clock.

3. Latches are widely used in digital systems for various applications, including
data storage, control circuits, and flip-flop circuits. They are often used in
combination with other digital circuits to implement sequential circuits, such as
state machines and memory elements.
4. In summary, latches are digital circuits that store a single bit of information and
hold its value until it is updated by new input signals. There are two types

14
 of latches: S-R (Set-Reset) Latches and D (Data) Latches, and they are widely
used in digital systems for various applications.
4.5 Flipflops vs Latches:
The primary difference between a latch and a flip-flop is a gating or clocking mechanism.
Flip Flops are edge-triggered and a latch is level-triggered.
For example, let us talk about SR latch and SR flip-flops. In this circuit when you Set S as
active, the output Q will be high and Q’ will be Low. This is irrespective of anything else.
(This is an active-low circuit; so active here means low, but for an active high circuit, active
would mean high).

Figure 7:SR Flipflop

A flip-flop, on the other hand, is a synchronous circuit and is also known as a gated
or clocked SR latch.

Figure 8:SR latch

In this circuit diagram, the output is changed (i.e. the stored data is changed) only when you
give an active clock signal. Otherwise, even if the S or R is active, the data will not change.

15
 Chapter 5

UART

5.1 What is UART?

UART stands for universal asynchronous receiver / transmitter and defines a
protocol, or set of rules, for exchanging serial data between two devices. UART is very
simple and only uses two wires between transmitter and receiver to transmit and receive in
both directions. Both ends also have a ground connection. Communication in UART can
be simplex (data is sent in one direction only), half-duplex (each side speaks but only one
at a time), or full-duplex (both sides can transmit simultaneously). Data in UART is
transmitted in the form of frames.

Figure 9:UART

5.2 Where is UART used?

UART was one of the earliest serial protocols. The once ubiquitous serial ports are
almost always UART-based, and devices using RS-232 interfaces, external modems, etc.
In recent years, the popularity of UART has decreased: protocols like SPI and I2C have
been replacing UART between chips and components. Instead of communicating over a
serial port, most modern computers and peripherals now use technologies like Ethernet and
USB. However, UART is still used for lower-speed and lower-throughput applications,
because it is very simple, low-cost and easy to implement.

16
One of the big advantages of UART is that it is asynchronous – the transmitter and receiver
do not share a common clock signal. Although this greatly simplifies the protocol, it does
place certain requirements on the transmitter and receiver. Since they do not share a clock,
both ends must transmit at the same, pre-arranged speed in order to have the same bit
timing. The most common UART baud rates in use today are 4800, 9600, 19.2K, 57.6K,
and 115.2K. In addition to having the same baud rate, both sides of a UART connection
also must use the same frame structure and parameters. The best way to understand this is
to look at a UART frame.

5.3 UART Frame Format:

Figure 10:Frame Format

As with most digital systems, a “high” voltage level is used to indicate a logical “1” and a
“low” voltage level is used to indicate a logical “0”. Since the UART protocol doesn’t define
specific voltages or voltage ranges for these levels, sometimes high is also called “mark”
while low is called “space”. Note that in the idle state (where no data is being transmitted),
the line is held high. This allows an easy detection of a damaged line or transmitter.

5.4 Start and Stop bits:

Because UART is asynchronous, the transmitter needs to signal that data bits are coming.
This is accomplished by using the start bit. After the data bits are finished, the stop bit
indicates the end of user data. The stop bit is either a transition back to the high or idle state
or remaining at the high state for an additional bit time. A second (optional) stop bit can be
configured, usually to give the receiver time to get ready for the next frame, but this is
uncommon in practice.

17
5.5 Parity bit:
A UART frame can also contain an optional parity bit that can be used for error detection.
This bit is inserted between the end of the data bits and the stop bit. The value of the parity
bit depends on the type of parity being used (even or odd):
• In even parity, this bit is set such that the total number of 1s in the frame will be
even.
• In odd parity, this bit is set such that the total number of 1s in the frame will be odd.
Example:
Capital “S” (1 0 1 0 0 1 1) contains a total of three zeros and 4 ones. If using even parity, the
parity bit is zero because there already is an even number of ones. If using odd parity, then
the parity bit has to be one in order to make the frame have odd numbers of 1s.
The parity bit can only detect a single flipped bit. If more than one bit is flipped, there’s no
way to reliably detect these using a single parity bit.

Figure 11:Parity bit

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 Chapter 6

ALU
6.1 What is an ALU?
An arithmetic-logic unit is the part of a central processing unit that carries
out arithmetic and logic operations on the operands in computer instruction words.
In some processors, the ALU is divided into two units: an arithmetic unit (AU) and a
logic unit (LU). Some processors contain more than one AU -- for example, one for
fixed-point operations and another for floating-point operations.
In computer systems, floating-point computations are sometimes done by a floating-
point unit (FPU) on a separate chip called a numeric coprocessor.
ALU conducts arithmetic and logic operations. It is a major component of the CPU in
a computer system. An integer unit (IU) is just an integrated circuit within a GPU or
GPU that performs the last calculations in the processor.
It can execute all arithmetic and logic operations, including Boolean comparisons,
such as subtraction, addition, and shifting (XOR, OR, AND, and NOT operations).
Binary numbers can also perform bitwise and mathematical operations. AU
(arithmetic unit) and LU (logic unit) are two types of arithmetic logic units. The
ALU’s operands and code instruct it on which operations to perform based on the
incoming data. When the ALU has finished processing the data, it sends the result to
the computer memory.

Figure 12:ALU

19
6.2 Uses of ALU:
ALUs, in addition to doing addition and subtraction calculations, also handle the
process of multiplication of two integers because they are designed to perform integer
calculations; thus, the result is likewise an integer. Division operations, on the other
hand, are frequently not done by ALU since division operations can result in a
floating-point value. Instead, division operations are normally handled by the floating-
point unit (FPU), which may also execute other non-integer calculations.
Engineers can also design the ALU to do any operation they choose. However, as the
operations become more sophisticated, ALU becomes more expensive since it
generates more heat as well as takes up more space on the CPU. Therefore, engineers
create powerful ALUs, ensuring that the CPU is both quick and powerful.
The ALU performs the computations required by the CPU; most of the operations are
logical in nature. If the CPU is built more powerful, it will be designed on the basis
of the ALU. Then it generates more heat and consumes more energy or power. As a
result, there must be a balance between how intricate and strong ALU is and how
much it costs. The primary reason why faster CPUs are more expensive is that they
consume more power and generate more heat due to their ALUs. The ALU’s major
functions are arithmetic and logic operations, as well as bit-shifting operations.

6.3 Operations Performed by ALU:

Although the ALU is a critical component of the CPU, the design and function
of the ALU may vary amongst processors. Some ALUs, for example, are designed
solely to conduct integer calculations, whereas others are built to perform floating-
point computations. Some processors have a single arithmetic logic unit that performs
operations, whereas others have many ALUs that conduct calculations. ALU’s
operations are as follows:

1. Arithmetic Operators:
It refers to bit subtraction and addition, despite the fact that it does multiplication
and division. Multiplication and division processes, on the other hand, are more
expensive to do. Addition can be used in place of multiplication, while subtraction
can be used in place of division.

20
 2. Bit-Shifting Operators:
It is responsible for a multiplication operation, which involves shifting the
locations of a bit to the right or left by a particular number of places.

3. Logical Operations:
These consist of NOR, AND, NOT, NAND, XOR, OR, and more.

6.4 ALU Signals:

The ALU contains a variety of electrical input and output connections, which
result in the digital signals being cast between the ALU and the external electronics.
External circuits send signals to the ALU input, and the ALU sends signals to the
external electronics.
Opcode: The operation selection code specifies whether the ALU will conduct
arithmetic or a logic operation when it performs the operation.
Data: The ALU contains three parallel buses, each with two input and output
operands. These three buses are in charge of the same amount of signals.
Input: Once ALU has completed the operation, then the status inputs allow the ALU
to obtain more information needed to complete the process successfully. A single
“carry-in” is used, which is a stored carry-out from the prior ALU operation.
Output: The status outputs, which are numerous signals, offer the results of an ALU
operation in the form of extra data. Overflow, carry out, zero, negative, and other
status signals are usually handled by general ALUs. The status output signals were
stored in the external registers after the ALU completed each operation. These signals
are saved in external registers, which allows them to be used in future ALU operations.

Figure 13:ALU Signals

21
6.5 ALU Configurations:
The following is a description of how the ALU interacts with the processor. These
configurations are included in every arithmetic logic unit:
Accumulator
Instruction Set Architecture
Stack
Register Stack
Register to Register
Register Memory
Pros of ALU
The following are some of the benefits of ALU:
It supports high-performance parallel architecture and applications. It can provide the
desired output at the same time and combine integers and floating-point variables.
It has the ability to carry out instructions on a large number of items and has a high
level of precision.
The ALU can combine two arithmetic operations in the same code, such as
multiplication and addition or subtraction and addition, or any two operands. A+B*C
is an example.
They remain consistent throughout the presentation, and they’re spaced in such a way
that they do not interrupt any of the segments.
It is, in general, highly rapid, and as a result, it produces results swiftly. With ALU,
there are no sensitivity difficulties or memory wastage. They are less costly and reduce
the number of logic gates required.
Cons of ALU:
The following are some of ALU’s drawbacks:
• Floating variables have higher delays with the ALU, and the intended
controller is difficult to grasp.
• If memory space were fixed, bugs would appear in the results.
• Amateurs are tough to understand since their circuits are complex, and the
principle of pipelining is also difficult to grasp.
• The inconsistencies in latencies are a known drawback of ALU. Another flaw
is rounding off, which reduces precision.

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We'll describe a simple ALU in Verilog HDL with only combinational circuits for 8-
bit processor. For simplicity, only eight operations are chosen but you can design an
ALU. Below is the code for a 8-bit ALU which can perform addition, subtraction,
division, multiplication, logical AND, OR, NOT and EX-OR.
// 8-bit arithmetic and logical unit
➢ module alu(
➢ input [2:0]opcode,
➢ input [7:0]OperandA,OperandB,
➢ output reg [7:0]result
➢ );
➢ always @(*)begin
➢ case(instruction)
➢ 3'b000:
➢ result = OperandA + B;
➢ 3'b001:
➢ result = OperandA - B;
➢ 3'b010:
➢ result = OperandA / B;
➢ 3'b011:
➢ result = OperandA * B;
➢ 3'b100:
➢ result = OperandA & B;
➢ 3'b101:
➢ result = OperandA | B;
➢ 3'b110:
➢ result = ~OperandA;
➢ 3'b111:
➢ result = OperandA ^ OperandA;
➢ default:
➢ result = 0;
➢ endcase
➢ end
➢ endmodule

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The above code has processing elements (PE) and MUX. We have to perform 8
operations so, 8X1 MUX is required to select the desired operation. The length of the
inputs is 8-bit so we require eight 8X1 MUX. The above code is described using
behavioural modelling. The case statement will be synthesised to MUX and each
processing element will be synthesised to a combinational circuit.
If the instruction is 000, it performs the addition operation of the operands A and B
and output is available at the output of the MUX, 001 performs the subtraction
operations and so on.
ALU Testbench:
➢ module alu_tb;
➢ reg [2:0]instruction;
➢ reg [7:0]A,B;
➢ wire [7:0]result;
➢ alu uut (instruction, A, B, result);
➢ integer i;
➢ initial begin
➢ A = 50; B = 10; instruction = 0;
➢ for (i = 1; i < 8; i = i+ 1) begin
#10
➢ instruction = i;
➢ end
#10
➢ $finish();
➢ end
➢ endmodule

Figure 14:Output waveform

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 Chapter 7

Verification and System Verilog (SV)

Verification is a critical step in the VLSI (Very Large Scale Integration) design
process. It ensures that the design meets its specifications and behaves as intended. System
Verilog (SV) is a popular language used for both design and verification in the VLSI
industry.
7.1 System Verilog for Verification:
System Verilog extends the Verilog HDL to include powerful verification features. It
introduces new constructs for creating testbenches and performing high-level verification
tasks. These features include:

• Classes and Objects: System Verilog supports object-oriented programming, which

allows for more modular and reusable testbenches.
• Randomization: System Verilog provides built-in random number generation and
constraint solving, which are essential for creating randomized test cases.
• Assertions: System Verilog assertions (SVA) allow designers to specify expected
behaviour and automatically check that the design meets these expectations.
• Coverage: System Verilog includes constructs for measuring how thoroughly the
design has been tested.
Here’s a simple example of a System Verilog testbench for a 4-bit counter module:
module counter_tb;
// Testbench signals
➢ reg clk;
➢ reg reset;
➢ wire [3:0] q;
// Instantiate the counter module
➢ Counter uut (
➢ .clk(clk),
➢ .reset(reset),
➢ .q(q)
➢ );

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 // Clock generation
➢ always #5 clk = ~clk;
// Test sequence
➢ initial begin
// Initialize signals
➢ clk = 0;
➢ reset = 1;
➢ #10 reset = 0;
// Wait for a few clock cycles
➢ #100;
// Check the counter value
➢ if (q !== 4'b1010) begin
➢ $display("Test failed");
➢ $finish;
➢ end
// If the test passes
➢ $display("Test passed");
➢ $finish;
➢ End
➢ endmodule

In this testbench, a clock signal is generated, a reset is applied, and then the counter’s output
is checked against an expected value after a certain number of clock cycles. If the output is
incorrect, it displays “Test failed”; otherwise, it displays “Test passed”.

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