Published by : International Journal of Engineering Research & Technology (IJERT)

http://www.ijert.org ISSN: 2278-0181

Vol. 12 Issue 04, April-2023

VLSI Implementation of Adaptive FIR Filter

using DA with Low Power and Low Area
Sruthi S Anas A S
Department of Electronics and Communication, Department of Electronics and Communication,
Kollam, Kerala Kollam, Kerala

Abstract- Adaptive Filter are digital filters whose coefficients In signal processing applications such as echo
change with an objective to make the filter converge to optimal cancellation, digital communications an adaptive filter, is
state. The conventional adaptive Fir filter the adder-based shift essential since only a limited amount of a priori knowledge
accumulation is replaced by compressor adder are used to of signal properties is available in. It consist of multiplier,
reduce area and the critical path is large to obtain filter
response so pipelined concept are introduced in the least mean
delay elements and adders. When we observe the
square (LMS)algorithm. With these two concepts the power architecture multiplier will occupy more area and power
consumption of the adaptive filters will be reduced. This will be consumption. The linear combiner form the filter output y,
coded in Verilog HDL language and implemented on Artix 7 remains at the centre of the architecture. The adaptive filter
FPGA hardware. This will be suited for signal processing will change the filter coefficient to bring them closer to their
application design such as adaptive decision feedback equalizer ideal values. The filter coefficient can be updated with a
for removing the signal noises, hearing aids and ECG signal variety of adaptive techniques. FIR and IIR are two types of
analysis. adaptive filters. Because of the natural stability and ease of
computation adaptive FIR filter are more advantageous than
Keywords: Pipelined, LMS adaptive FIR filter, Distributed
Arithmetic, Compressor adder, Artix 7 FPGA
IIR filters.
Least mean square adaptive design, Recursive adaptive
I. INTRODUCTION design, Normalized adaptive filter are the three main
algorithms presents. Because filter coefficients may be
An adaptive filter is a digital filter that has self-adjusting quickly adjusted, the least mean square adaptive method is
characteristics. It is capable of adjusting its filter coefficients better choice. Multiplier, shifter, and adder are commonly
automatically to adapt the input signal via an adaptive used in any filters. Multiplier will take up more space and
algorithm. Adaptive filter play an important role in digital energy. Multiplier architecture are replaced by multiplier-
signal processing (DSP) products in area such as telephone less architecture in adaptive FIR filter to save area and power
echo cancellation, noise cancellation, equalization of consumption. To enhance the speed and reduce power, a
communication channel, biomedical signal enhancement, number of multiplier-less adaptive FIR filter topologies are
active noise control (ANC), and adaptive control systems. available. The distributed arithmetic model is well known
Adaptive filter work generally for the adaptation of signal- multiplier-free design for more efficient adaptive filter
changing environments, spectral overlap between noise and implementation.
signal and unknown or time-varying noise.
II. PREVIOUS WORK
Adaptive filter are widely used in several digital signal
processing applications. The tapped-delay line finite
impulse response (FIR) filter whose weights are updated by In 1996, pipeline FIR filter architecture and increasing
the Least mean square (LMS)algorithm is the mostly performance of decision-feedback equalizer [13] in which
popularly used adaptive filter not only due to its simplicity using Booth-encoding based input decomposition scheme
but also due to its satisfactory convergence performance. for FIR filter implementations. The high-order/high speed
The direct form-configuration on the forward path of the FIR FIR filter architecture usually have unavoidable pipelining
filter results in a long critical path due to the inner-product delays, and they add to the feedback loop delay of the
computation to obtain a filter output. Therefore, when the decision feedback equalizers. The added delay degrades the
input signal has sampling rate, it is necessary to reduce the performance of the equalizer for strong ISI signals. Finally,
critical path of the structure so that the critical path could not we present a new decision feedback equalizer architecture
exceed the sampling period. which function perfectly even though strong near-ISI signals
LMS is the frequently used algorithm in adaptive exist in the channel.
filtering. It is basically a gradient descent algorithm which In 2020, a generalized maximum correntropy criterion based
means that is adjusts the adaptive filter coefficients by robust sparse adaptive room equalization.[4] An adaptive
modifying them by an amount which is proportional to the room equalization scheme is usually employed to
gradient of the error surface. It can be represented in the compensate for the distortion of sound produced by the room
following equation (1). impulse response, thereby offering an improved listening
F(u(n), e(n), µ) = µe(n)u*(n) ………… (1) experience. In a conventional adaptive room equalizer, an
adaptive filter updated using a filtered-x least mean square

IJERTV12IS040305 www.ijert.org 498

(This work is licensed under a Creative Commons Attribution 4.0 International License.)
Published by : International Journal of Engineering Research & Technology (IJERT)
http://www.ijert.org ISSN: 2278-0181
Vol. 12 Issue 04, April-2023

(FxLMS) algorithm is used to achieve room equalization. Hanning window are cosine windows, but the weight
FxLMS algorithm-based room equalizers are not robust to coefficient is different. The weighting of Hamming window
strong disturbances picked by the reference microphone. An will make the side lobe smaller. Its spectrum is also
adaptive room equalizer tries to compensate for the composed of three rectangular windows, and the attenuation
deterioration in audio quality caused by the acoustic path speed is slower than that of Hanning window. Hamming
between loudspeaker and the listener. In its basic form, an window and Hanning window are window functions often in
adaptive room equalization system consists of an adaptive signal processing.
filter which is added between the sound sources and
loudspeaker. III. CURRENT WORK
Adaptive filters have coefficients that are allowed
FIR FILTER USING LMS ALGORITHM to vary over time. They are used when the filter response that
Mostly the adaptive filter is used in noise best accomplishes a particular task is not known a priori, or
cancellation applications. The desired signal is combination when the nature of the operating environment is expected to
of source signal and noise signal which is uncorrelated to the change over time. A typical system goal would be for a filter
signal. Filters takes a noise input and correlates with the to suppress undesired noise to the greatest extent possible
noise in desired signal to obtain the actual signal. Input of a while leaving the target signal intact to the extent possible.
filter is a reference noise which is correlated with the noise
in the desired signal. The error term e(n) obtained from the 𝐿−1
system is then used to cancel the noise in the original signal 𝑦𝑘 = ∑ 𝑥𝑙𝑘 𝑤𝑙𝑘
by using the LMS algorithm. Most widely use algorithm in
𝑙=0
adaptive filter is an LMS algorithm due to its simplicity. It
doesn’t needs an extra mathematical calculation like matrix
inversion nor correlation function. ...………….(1)
Mean square error (MSE) logic is used in LMS
algorithm.[6] It uses an input signal, step-size parameter, the Where the {𝑤𝑙𝑘}represent the variable weights of
subtraction of desired signal and filter output signal for the adaptive filter and the signals {𝑥𝑙𝑘} are the inputs to
calculating the updated filter coefficients. The LMS those weights. While this equation can be applied directly to
algorithm uses a structure of an FIR filter. Filter as two main any system for which the output is obtained by computing
components those are L delay registers and weight updated the linear combination of the outputs of an array of sensors,
blocks. The unit delay register are made of D flipflops. And the most common implementation for the adaptive processor
each weight updated component consist of multiplier, adder, is that of an FIR filter with variable coefficients. The block
and a buffer to store the new updated weights of the filter diagram of adaptive FIR filter as shown in Fig.1.
coefficient. According to error signal is obtained from the
difference of the filter output and desired signal. The error
signal is then multiplied with input signal and step size µ,
which produces next sets of filter coefficients.

FIR FILTER WITH SEVERAL WINDOW

FUNCTIONS
FIR low-pass filter is analysed and designed by
window function method [3] The design of FIR filter with
different window functions such as Hamming window and
Hanning window, simulates on MATLAB platform, and
compares and analyses the influence of different window
functions on the design performance of FIR filter.

Hanning window is also called rising cosine Fig.1 Block diagram of adaptive FIR filter
window. The side lobe is greatly reduced and the main lobe
width is doubled. Thus, high frequency interference and ADAPTIVE FIR FILTER USING DA WITH LOW
energy leakage can be eliminated. Compare with the POWER AND LOW AREA
spectrum of hanning window and rectangular window, the A low-complexity pipelined adaptive FIR filter is designed
main lobe of hanning window is widened and reduced, and using Distributed Arithmetic (DA) architecture for signal
the side lobe is significantly reduced. Hanning window is processing applications. Generally adaptive filter will
better than rectangular window. However, the disadvantage occupy more area and power consumption because of using
of hanning window is that it widens the main lobe, which is memories in the filters for partial product (PP) generation.
equivalent to widening the analysis bandwidth and reducing To get rid of this, the pipeline concept to reduce the registers
the frequency resolution. in the filter and also reduce the area further compressor
adders are used in the adaptive filter architectures instead of
Hamming window is also a kind of cosine window, using normal adders. With these two concepts the area and
also known as improved raised cosine window. It and power consumption of the adaptive filter will be reduced.

IJERTV12IS040305 www.ijert.org 499

(This work is licensed under a Creative Commons Attribution 4.0 International License.)
Published by : International Journal of Engineering Research & Technology (IJERT)
http://www.ijert.org ISSN: 2278-0181
Vol. 12 Issue 04, April-2023

And is well suited for signal processing application designs Fig.2 shows the 4-point inner product block. It
such as adaptive decision feedback equalizers for removing contains a DA table, 16:1 multiplexer, and conditional carry
the signal noises and inter symbol interference, hearing aids save accumulator. The DA table, which is made up of a 15
and ECG signal analysis. registers array, stores the partial inner products y. The
register’s contents are selected using the 16:1 multiplexer
It consist of multipliers, delay elements and adders. (MUX). The weight vector A=h31h21h11h01 is used to
The adaptive filters will change the filter coefficient to bring regulate the MUX, and the MUX output is sent to the
them closer to their ideal values. The filter coefficient can be conditional carry save accumulator (CSA) after every L bit
updated with a variety of adaptive techniques. FIR and IIR cycles. The CSA is used to shift and aggregate all partial
are two types of adaptive filters. Because of their natural inner products acquired from the MUX, as well as produce
stability and ease of computation, adaptive FIR filters are a total and a carry for each with a bit length of (L+2). To
more advantageous than IIR filters. Adaptive filters come in generate filter output, the sum words ROM the carry save
a variety of shapes and sizes. Least mean square adaptive accumulator are shifted and then added with the carry words
design, Recursive adaptive design, Normalized adaptive and an input carry “1” is employed. The error signal e is
filter are the three main algorithms present. Because filter obtained by subtracting the filter’s result from the target
coefficients may be quickly adjusted, the least mean square signal w(n).
adaptive method is a better choice.

Fig.2 Inner product block

Except for the most significant bit, all of the bits of accumulate operations across shifters, lookup tables (LUTs),
the error signal are evaluated, and the error signal is and adders in such a way that conventional multiplier are not
multiplied by a right shift. The no. of sites to be moved will required. It is extensively used in computing the sum of
be determined by the magnitude of the error, which is products.
dependent on the number of leading zeros present. Execute
the control word ‘t’ present in the barrel shifter by leveraging Fig.3 illustrate the partial product DA table for
that error. In error calculations, the convergence factor is N=4. It has seven parallel adders, each of which calculates
commonly given as O(1/N). In the current DA design, we seven new clock values in advance. It will assist in reducing
have assumed it is =1/N. In contrast,2-i/N is used when ‘i’ is the no. of clock cycles needed to compute the sums of input
a tiny integer value. To reduce hardware complexity, ‘i’ samples. It only has 15 registers to aggregate the pre-
places increase the amount of shifts in the t and ‘I’ places computed sums of partial products of the input words. It
increases the input to the barrel shifters. takes only four clock cycles to compute all 15 products for
input bits data length of 8 bits.
DISTRIBUTED ARITHMETIC (DA)
It is widely used technique for implementing sum- Rather than providing x(k+1) input samples to the
of-products computations without the use of multipliers. adders and register every time, the pipelined DA table
Designers frequently use DA to build efficient Multiply- architecture uses prior register samples recovered from the
Accumulate Circuitry (MAC) for filters and other DSP registers and returned as inputs to the adder to accomplish
applications. The main advantages of DA is its high the same DA table features. There are 15 registers and 7
computational efficiency. DA distributes multiply and adders in total, requiring hardware.

IJERTV12IS040305 www.ijert.org 500

(This work is licensed under a Creative Commons Attribution 4.0 International License.)
Published by : International Journal of Engineering Research & Technology (IJERT)
http://www.ijert.org ISSN: 2278-0181
Vol. 12 Issue 04, April-2023

Fig.3. Partial product outputs of DA tables

To construct X(k-1) +x(k+1), the inputs x(k) and

x(k+1) are added and transferred via the register x(k). As a COMPRESSOR ADDER
result, the register and adders will produces outputs like x(k-
2) +x(k), x(k), x(k-2) +x(k-1) ….., which will delivered in to
a 16:1 multiplexer with filter coefficient as selected lines.

ADAPTIVE FILTER ALGORITHM

For every clock cycle the filter coefficient can be

updated in adaptive filter to find filter output and error value.
The error value achieved is used for filter coefficient
updating process.

Input data 𝑋(𝑘) ,

𝑋(𝑘) = [𝑥(𝑘),…...𝑥(𝑘 − 𝐾 + 1)]𝑇 ……………(1) Fig.4. Compressor adder
‘T’ = Transposed form.
Output signal 𝑌 (𝑘) , The size of DA-based adaptive filters may be
𝑌 (𝑘) = ℎ(𝑘)𝑋𝑇 (𝑘) ……………(2) lowered by adopting the design, and to reduce the adders, a
h(k) = filter coefficient vector 3:2 compressor adder with two XOR gates and a 2:1
Weight updating of the LMS algorithm is : multiplexer. a, b, c are the inputs with sum and carry as
ℎ(𝑘 + 1) = 𝜇𝑒(𝑘)𝑋(𝑘) + ℎ(𝑘) …………….(3) outputs. The signal a, b are passed to first XOR gate, the
Eq. (3) is the increment of filter coefficient output of first XOR gate will passed as one input to the
Where 𝜇 = Step size , e(k) = error signal second XOR gate and c is the second input to the second
𝑒(𝑘) = (𝐷(𝑘) − 𝑌 (𝑘)) ……... (4) XOR gate. Both the signals are passed and get final sum.
𝐷(𝑘) = desired signal Whereas for getting carry a, c are passed as inputs to the 2:1

IJERTV12IS040305 www.ijert.org 501

(This work is licensed under a Creative Commons Attribution 4.0 International License.)
Published by : International Journal of Engineering Research & Technology (IJERT)
http://www.ijert.org ISSN: 2278-0181
Vol. 12 Issue 04, April-2023

MUX to get carry as output. By using this method the generation while providing best-in class transceivers and
number of gates are going to reduced in adder gates which signal processing capabilities for high bandwidth
are shown in Fig.4. As a result, the number of adders applications. Built on the 28nm HPL process, together with
required decreases as the area decreases. the MicroBlaze (TM) soft processor, Artix-7 FPGAs are
ideal for products like portable medical equipment, military
IV. SYSTEM DESIGN REQUIREMENTS radios, and compact wireless infrastructure. Artix-7 FPGA
MATALB meet the need of size, weight, power, and cost sensitive
MATLAB is a software package for high markets.
performance mathematical computation, visualization, and
programming environment. It provides an interactive V. RESULTS AND DISCUSSION
environment with hundreds of built-in functions for Low-pass filters are often used to clean up signals,
technical computing, graphics and animations. MATLAB remove noise, create a smoothing effect, perform data
stands for Matrix Laboratory. MATLAB is a modern averaging, and design decimators and interpolators. Low-
programming language environment, and it has refined data pass filters produce slow changes in output values to make
structure, includes built-in editing and debugging tools, and it easier to see trends and boost the overall signal-to-noise
support object oriented programming. MATLAB is Multi- ratio with minimal signal degradation.
paradigm. So it can work with multiple types of FIR filters are very attractive because they are
programming approaches, such as functional, object- inherently stable. They can be designed to have linear phase
oriented and visual. that introduces a delay in the filtered signal while
Filter design using MATLAB with different maintaining the waveform shape. Nonetheless, these filters
windows are taken for the verification of signal with noise can have long transient response and might prove
filtering. The different windows frequency spectrum, signal- computationally expensive in certain applications. FIR
to-noise ratio and magnitude response are taken from the filters are useful in audio, biomedical, radar, and other
MATLAB. The kaiser window, equiripple method, applications where the waveform shape provides useful
hamming window and hanning window are used for the filter information. Common design methods for low-pass FIR-
design. The input sine wave with high frequency noise are based filters include Kaiser window, Least squares, and
filtered into original signal using MATLAB. The sampling equiripple.
frequency 1000Hz, passband frequency 500Hz and stopband The filter coefficient from MATLAB are the
frequency 600Hz are provided to design the low pass filter. numerical value is converted into hexadecimal for assign in
The filter coefficients are taken from the MATLAB and it is Verilog. The normal sine wave with high frequency noise
converted into hexadecimal for assigned in Xilinx Vivado added are filtered to extract original and spectrum as shown
for Verilog implementation. in Fig.5, 6 and 7. The 300Hz sine wave, 1000 HZ sine Fig.8.
The different window such as equiripple, Kaiser window,
XILINX VIVADO hanning window and hamming window are designed in
Vivado design suite is a software suite produced by MATLAB for verifying the Original signal with its
Xilinx for synthesis and analysis of hardware description spectrums are shown in Fig.9, 10,11and 12. The adaptive
language (HDL) designs, superseding Xilinx ISE with FIR filter using DA are designed in Verilog implementation
additional features for system on a chip development and using vivado and its behavioral simulation as shown in Fig
high-level synthesis. Vivado includes the in-built logic 13and is implemented in Artix 7 FPGA. The power
simulator. Vivado also introduces high-level synthesis, with consumption, area , signal-to-noise ratio and mean square
a toolchain that converts C code into programmable logic. error are calculated in vivado.
The framework was executed in Xilinx vivado
using Verilog programming along the test bench and results.
The filter design is taken in Xilinx vivado using distributed
arithmetic with the behavioral simulation of waveform
shows the filtering of input sine wave with noise will extract
the original signal. The vivado platform is used to implement
in the hardware Artix 7 FPGA. The Signal-to-noise ratio,
power consumption, area are identified by the vivado
platform.
ARTIX 7 FPGA
Artix 7 FPGA provides high performance-per-watt
fabric, DSP processing and analog mixed signal integration
in a cost optimized FPGA. The Xilinx Artix-7 FPGA board
is flexible enough for different application reprogramming.
Artix 7 FPGA have about 50% lesser total power
consumption than earlier generation. The Xilinx Artix-7
FPGA board features 32 MB of SDRAM memory. The
Fig.5. Basic sine wave developed in MATLAB
Xilinx Artix-7 FPGA has redefined cost-sensitive solutions
by cutting power consumption in half from the previous

IJERTV12IS040305 www.ijert.org 502

(This work is licensed under a Creative Commons Attribution 4.0 International License.)
Published by : International Journal of Engineering Research & Technology (IJERT)
http://www.ijert.org ISSN: 2278-0181
Vol. 12 Issue 04, April-2023

Fig.6.Sine wave added with high frequency noise

Fig.9 Spectrum of input and output signals FIR filter designed in
equiripple method

Fig.7. Extracted original signal using low pass filter

Fig .10 Spectrum of input and output signals of FIR filter designed using
kaiser window

Fig.8. 300Hz and 1000Hz waveforms and these are added to form the
distorted waveform

Fig.11 Spectrum of input signals of FIR filter designed using hanning

window

IJERTV12IS040305 www.ijert.org 503

(This work is licensed under a Creative Commons Attribution 4.0 International License.)
Published by : International Journal of Engineering Research & Technology (IJERT)
http://www.ijert.org ISSN: 2278-0181
Vol. 12 Issue 04, April-2023

more clears and illustrative the simulations waveforms and

finally implemented on the board Xilinx Artix 7 FPGA.
Then analysed the power consumption, area and Signal-to-
noise ratio. And is suitable for all signal processing
applications such as audio, biomedical, radar etc.

REFERENCES
[1] K. Vijetha, Rajendra Naik B, “Low power low area VLSI
implementation of adaptive FIR filter using DA for decision
feedback equalizer”, University College of Engineering Osmania
University, Hyderabad, Telangana, India, Elsevier B.V.,2022.
[2] Swetaleena Sahoo, Yash Keju Barapatre, Harish Kumar Sashoo,
Sarita Nanda, “FPGA implementation of fuzzy sparse adaptive
equalizer for indoor wireless communication systems”,
Department of Electronics and Telecommunication Engineering,
2021.
[3] Yanjie Xu, “Design of FIR filter with several window functions”,
Air Force Engineering University,2021.
[4] Krishna Kumar, Nithin V. George, “A generalized maximum
Fig.12 Spectrum of input and output signals of FIR filter designed using correntropy criterion based robust sparse adaptive room
hamming window equalization”, Department of Electrical Engineering Indian
Institute of Technology Gandhinagar,2020.
[5] Jyothi Granda Naga, Sridevi Sriadibhatla, “ASIC implementation
of low power, area efficient adaptive FIR filter using DA”, in:
Microelectronics, Electromagnetics and Telecommunications,
Springer, Singapore,2019, pp,385-394.
[6] M.T Khan, S. R. Ahamed, “A new high performance VLSI
architecture for LMS adaptive filter using distributed arithmetic”,
IEEE computer society annual sympositum on VLSI,2017, pp.219-
224.
[7] Rushi Jariwala, Ishan Upadhyaya, Nithin V. George, “ Robust
equalizer design for adaptive room impulse response
compensation”, Department of Electrical Engineering,2017.
[8] Park Sang Yoon, Pramod Kumar Meher, “Low-power, high-
throughtput , and low-area adaptive FIR filter based on distributed
arithmetic”, IEEE Trans. Circuits Sys:Express brief.60.6 (2013)
346-350.
[9] H Xiangping Zeng aiquan Zhao, Xiaoqiang Zhang, jiashu Zhang,
Yangguang Liu, Tiao Wei, “An adaptive decision feedback
equalizer based on the combination of the FIR and FLNN”,
National Science Foundation of PR China, 2011.
[10] R.Guo and L.S Debrunner, “Two high performance adaptive filter
implementation schemes using distributed srithmetic”, IEEE
Fig .13. Verilog implementation of DA based FIR filter Trans. Circuits Syst ,Sep2011.
[11] P. K Meher and S. Y. Park, “High-throughput pipelined realization
of adaptive FIR filter based on distributed arithmetic”, In VLSI
I. Table .Comparison of Existing method and symp Tech Dig, Oct 2011
proposed method with power [12] D.J. Allred H.Yoo, V. Krishnan, W huang, and D V Anderson,
“LMS adaptive filters using distributed arithmetic for high
throughput”, IEEE trand.circuits syst, July 2005.
Design Filter length Power(W) [13] Taek Lim, LG, “Pipelined FIR filter architecture and increasing
Allred [12] 16 24.39 performance of decision-feedback equalizer”, Electronics
R.Guo [10] 16 21.36 Research Center, IEEE publication, 1996.
Meher [11] 16 12.08
Sang Yoon [8] 16 9.41
proposed 16 7.965

VI. CONCLUSION
In this paper a basic design of adaptive FIR filter to
remove the noise with low power and low area. The
conventional adaptive FIR filter the adder-based shift
accumulation is replaced by compressor adder are used to
reduce area and the critical path is large to obtain filter
response so pipelined concept are introduced in the Least
Mean Square algorithm (LMS). It was analysed the value of
outputs are changing when the clock is changing. The
designed are executed using Verilog coding along with the
test bench. This framework was executed in Xilinx Vivado
using Verilog coding and test bench for the design also
introduced in order to test the design, to make the things

IJERTV12IS040305 www.ijert.org 504

(This work is licensed under a Creative Commons Attribution 4.0 International License.)