QCA Based Design of Cost-Efficient Code Converter With Temperature Stability and Energy Efficiency Analysis

Materials Today: Proceedings xxx (xxxx) xxx
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Materials Today: Proceedings

journal homepage: www.elsevier.com/locate/matpr
QCA based design of cost-efficient code converter with temperature

stability and energy efficiency analysis
Dhrubajyoti Bhowmik a, Jayanta Pal b, Munesh Chandra a, Apu Kumar Saha c, Nitendra Kumar d,⇑
a
Department of Computer Science and Engineering, NIT Agartala, India
b
Department of Information Technology, Tripura University, India
c
Department of Mathematics, NIT Agartala, India
d
Department of Applied Sciences and Humanities, IIMT College of Engineering, Greater Noida, India
a r t i c l e i n f o a b s t r a c t
Article history: Quantum dot Cellular Automata (QCA) are a prominent nanotechnology that is widely employed in dig-
Received 28 July 2021 ital circuits and systems. In comparison to complementary metal–oxide semiconductor (CMOS) technol-
Accepted 14 August 2021 ogy, QCA is a remarkable and challenging alternative with many attractive aspects such as fast execution
Available online xxxx
and low power use. To accomplish all arithmetic processes, code converters are the fundamental unit of
information change. Most of the converters, out of many designed for far in QCA, did not considered tem-
Keywords: perature stability, energy dissipation which may contribute to propagate as a non-operational circuit in
Quantum cellular dot automata
various temperatures. This paper proposes a novel concept for a binary-to-gray code and a BCD-to-Excess
Gray code
BCD–Excess3 code
3 code converter based on QCA. The promised structure diminishes the number of cells, area utilized to
Temperature stability make the design cost effective. The fundamental purpose of this research is to give a temperature stable
Energy dissipation and energy efficient converter design. The operability of the introduced design is verified with the
QCADesigner2.0.3 tool and the temperature stability factor and energy waste are evaluated with
QCADesignerE2.0.3.
Copyright Ó 2020 Elsevier Ltd. All rights reserved.
Selection and peer-review under responsibility of the scientific committee of the National Conference on
Functional Materials: Emerging Technologies and Applications in Materials Science
1. Introduction external clock signal operation in QCA. A polarized cell state is

passed on via QCA wire to transfer the data with assist of the
The technology, CMOS is arriving at the physical pick margin four-phase clocking system [4]. There exists enormous QCA based
after which any additional downscaling in dimension is a concern research work in every section of digital logic. It does not exclude
of possibility. High power consumption, high leakage current, and one of the essential sections, a code converter [5]. Code convert-
high-density design scale the performance of CMOS. A promising ers are useful circuit that converts from one code to another
and acceptable technology with the capability to outperform which is programmed in the logic array and utilized in many
these loopholes is highly demanded. One such nanotechnology, areas, like data protection and increment data adaptability [5].
the QCA, is found suitable for designing the structure to reduce Excess-3 code and Gray code are non-weighted code with self-
cost and enhance energy-efficiency [1,2]. The striking features like complementary and cyclic code in nature respectively. The earlier
low power consumption in signal propagation, fast and high- proposals have focused on designing converter in QCA with a
density design have attracted researchers to look into the require- reduction in cell number or area. Most of the work does not pro-
ments of its visibility and implementation [3]. A QCA cell is pose any design for gray to binary converter. In no design in the
accounted of a couple of free electrons, confined inside the well literature have important features like the feasibility of working
potential. Not likely the conventional CMOS technology, instead under various temperatures and the amount of energy dissipated
of any current flow, signal transfer and propagation occurs under from the circuit. This somehow strikes the momentum of the
work in this paper.
⇑ Corresponding author. This paper has proposed a design for the development of Binary
E-mail address: [email protected] (N. Kumar). to Gray Code converter in QCA &vice versa along with this page has
https://doi.org/10.1016/j.matpr.2021.08.119
2214-7853/Copyright Ó 2020 Elsevier Ltd. All rights reserved.
Selection and peer-review under responsibility of the scientific committee of the National Conference on Functional Materials: Emerging Technologies and Applications in
Materials Science
Please cite this article as: D. Bhowmik, J. Pal, M. Chandra et al., QCA based design of cost-efficient code converter with temperature stability and energy
efficiency analysis, Materials Today: Proceedings, https://doi.org/10.1016/j.matpr.2021.08.119
D. Bhowmik, J. Pal, M. Chandra et al. Materials Today: Proceedings xxx (xxxx) xxx
proposed the conversion of BCD to Excess-3 code. In the mentioned 2.2. Wire
work, we confront a novel design of converter gates that acquires
the desired output by concentrating in the conventional metrics QCA wire constructed as a cluster of cells regulated in a row and
for a cost-effective design. The main motive of this research is to each cell’s polarization is heavily influenced by neighboring cell
suggest an advanced temperature stable and energy-efficient code polarization owing to the electrostatic repulsion [6].
converter design (BCD to Excess-3 and Binary to Gray code).
The promising research attributes of the proposed design are:
2.3. Wire crossing
A new design for the Binary to Gray code converter & code con-
verter like BCD to Excess 3 code IIS introduced.
In QCA, there are two sorts of QCA wire-crossing is available,
The introduced design is the simple, coplanar, robust, and effi-
which are perceptible in the coplanar Fig. 1(e) The coplanar wire
cient converter.
crossing in QCA calls for the cells to be in a pair of distinct orienta-
The temperature stability and the power dissipation analysis for
tions, a 900 (X – cell) and a 450 (+ – cell) though multiple-layer
the introduced design are carried out.
wire intersection is recognized with the singly oriented cells.
A comprehensive comparative study is explored to exploit the
acceptability of the proposed designs.
The operations are verified using QCADesigner and QCADe- 2.4. Basic gates
signerE simulation tool was used for the temperature stability
and energy dissipation measurements. The essential primitive structure in QCA is the majority gate
Circuit suggested Useful at clock wire crossing. with three inputs, MV (A, B, C) = Maj (A, B, C) = AB + BC + CA as
The circuits proposed may be implemented to minimize the shown in Fig. 1(c). The majority gate may likewise work as an
logic circuit. AND with 2-inputs or an OR with 2-inputs by getting one from
The remaining of the article is constructed as following-- three of the input cells set to P = 1 or P = +1 gradually. The trans-
Section 2 contains the fundamentals of QCA design. Section 3 position should be possible in the Quantum-dot Cellular Automata
gives prior connected work in the domain of code converters. wire to put the wire off-centered somehow. This is distinguished in
The proposed design of code converters is represented in Section 4. a couple of distinct directions as appeared in Fig. 1(d).
Simulation results in the QCA are shown in Section 5. Section 6
exhibits the energy consumption and consistency of the promised 2.5. QCA clocking
design. At last, Section 6 introduces the conclusion & the end to
future functions. In QCA, timing or synchronization is accomplished through the
plunging clocking of 4 (four) distinct and periodic stages (Fig. 2).
The clock gives the power necessary to work on the QCA [6]. The
tunneling barrier into a pair of dots of a Quantum-dot Cellular
Automata cell begins to increase in the first (switch) period of
2. Preliminaries
the clock. This is the stage that leads to the actual computation.
When the tunneling barriers are large enough to prevent electrons
2.1. QCA cell
from tunneling, the second (hold) stage begins. The barrier lowers
from higher to lower in the third (relax) step. The final stage (relax)
In design-based on QCA, a solitary device (QCA-cell) is
employed for the maturation of the considerable number of con-
stituents of a circuit (computing components and wires). A 4
(four)-dot QCA cell symbolic diagram appears in Fig. 1(a). It con-
tains two pairs of quantum dots placed at the diagonal corner of
the square-shaped structure &a pair of untied electrons [2]. A
Quantum dot is the region for an electron to become quantum-
mechanically confined, Fig. 1(a). The coulomb repulsion restricts
the definitive model of electrons possess any two diagonally oppo-
site corners of the four corners of QCA cell, getting about either
polarization P = (1) (logic 0) or in P = 1 (logic 1) as appeared in
Fig. 1(b).
Fig. 1. QCA Basic. Fig. 2. Clocking.
2
of clocking ensures that there is no inter-dot barrier and that the enhance the adaptability for information and hold outsiders
cell is not polarized. informed. Binary code is how communication takes place and
obtains user data using the number system. For example, the
seven-bit binary sequence 1,100,100 is identical to the decimal
3. Related work
number 100. Gray code, being a numeral scheme, is defined by dif-
fering each value only by a single number from the previous num-
This section discusses the previous designs in the context of
ber. Gray code is a numeral structure program where each value
code converters. It includes Binary to Gray converter as well as
differs from the previous number. The gray code, which functions
BCD to Excess 3 converters. A conversion circuit should be planted
as an analog-to-digital converter has various useful uses; simplifies
connecting the pair of systems when they use various codes for
fault detection and peripheral tools [19,1].
standardized information. In this way, a code converter circuit
forms the pair of systems perfect even though each one an alter-
nate binary code [11]. In this regard, numerous research has taken
place for the implementation of the converters as discussed below. 4.1. Binary to Gray converter
Several research articles have been reported for the method of
designing binary to gray code converter [1,8,10,11,14,19]. In this A Binary to Gray Code Converter is a combinational logic circuit
design [11] reported that, the circuit is not expandable or scalable. that converts a binary number to its equivalent gray code which is
An XOR based design of converter has been reported in this paper a non-weighted code. To convert binary to gray code, consider the
[14]. The use of a signal distribution network for the design was significant most digit of the given binary number, as the significant
proposed in [19], however, it was not properly used in the QCA most digit of the gray code number is almost similar as in the bin-
implementation. A similar design can be reported in [1] with low ary code. The biggest benefit is the very low amount of power con-
energy consumption analysis. In [8], a new XOR gate is presented sumption. Table 1 describes the output combination for the
in QCA and a different layout for binary to gray code is also pre- sequence of inputs, in form of a truth table for a converter of 4-
sented using multi-layer cross over technique. However, no design bit binary to gray code converter. On observing the truth Table 1,
was found in the literature to propose the design to get back the the outputs can be expressed as:
binary value in return, i.e. gray to binary converter. The concept
of energy dissipation was introduced in [19], but without any G1 ¼ A
proper illustration. The temperature stability factor still remains
an issue to be addressed. Along with the converter for the conver-
G2 ¼ A XOR B
sion of binary to gray code, a similar type of purpose i.e. binary to
excess-3 code conversion is also practiced in QCA in [2,11,18], pop-
ularly known as BCD to Excess-3 code converter. A design for BCD G3 ¼ B XOR C
to Excess-3 Code Converter in QCA is proposed in using multi-layer
approach. It is not considered to be a suitable candidate for the fab-
rication. A coplanar approach for the BCD to Excess-3 code con- G4 ¼ C XOR D
verter circuit can be found in [11], which used the simple QCA
Accordingly, the set of inputs and outputs are depicted in Fig. 3,
logic circuit using NAND and NOR. Whereas, another coplanar
which represents the block diagram of the converter from binary to
design with a modified logic in the circuit in reported in [1], but
gray code along with the circuit diagram. It is clear that the design
suffered with issues like cell count, area and scalability. At the
of code converter (Binary to Gray code) circuit we applied XOR
same, no design in the literature have concentrated on tempera-
gate. So, an efficient XOR gate design will serve the purpose. In this
ture variable applicability and energy dissipation. Moreover, the
regard, we have chosen the design for the XOR gate as proposed in
mentioned works have concentrated in the concise design,
[4]. The XOR design was chosen for its property like low power
restricted to cell count only. No such design has been reported to
consumption, performance in different order than the conventional
describe the feasibility of working on the design in various temper-
design using cell interaction as shown in Fig. 4. The exact same
atures. Additionally, the energy dissipation for the converter
XOR gate is implemented for the design of gray to binary code con-
design was ignored in most of the previous cases. As each and
verter also. With these design principles, the QCA layout and the
every code use two couple of bits for representing a decimal digit,
simulation wave form for the same are depicted in Fig. 7(a) and
4 (four) input and 4 (four) output variables must be there is
Fig. 7(b) shows the simulation result of the Binary to Gray code
reported in [1]. These lead us to design a cost-effective converter
converter. The design is entirely utilizing the property of the cell-
and analysis of temperature operability and energy dissipation
level methodology of QCA. It does not help to design an ultra-
also.
low power-based model, also reduces the necessary clock cycle
in producing the result. As it can be seen that, only two clock cycle
4. Proposed design methodology is needed in for the proposed design, i.e. having latency of 0.5 only.
This in terns reduces the QCA cost of the circuit and makes the
In this section, the design principle and the QCA layout for the design an efficient one. With these design principles, the QCA lay-
converters are discussed. The simulated results are also illustrated out and the simulation waveform for the same is depicted in Fig. 7
to establish the functionality of the proposed design. The QCA com- (a) and Fig. 7(b) shows the simulation result of Binary to Gray code
putation proceeds by cell direction dependent on neighboring cell converter. The design is completely using the property of cell-level
polarization. Estimates are designed for understanding the appro- methodology of QCA. It not helps to design a ultra-low power
priate techniques and promoting the strategy proposed. QCADe- based model, also reduces the necessary clock cycle in producing
signer 2.0.3 is chosen at that level & that simulation method is the result. As it can be seen that only two clock cycle is needed
described in [27]. QCADesigner 2.0.3 reinforces the usefulness of in for the proposed design, i.e. having latency of 0.5 only. This in
the aim, which contains default values such as cell size, reduces terns reduces the QCA cost of the circuit and makes the design
impact, total relaxation time, relative primitively, etc. Code con- an efficient one. The simulate waveform as shown in Fig. 7(b) ver-
verters are Circuits for interpreting a provided code into another, ifies how the design operates in compliance with the truth table.
which is concealed in the logical array & run in a few regions to The simulation is carried out by QCADesigner version 2.0.3 (Fig. 5).
3
Table 1
Truth Table for Binary to Gray Code converter.
Truth Table
Input Output
Binary Code Gray Code
D C B A G4 G3 G2 G1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
B3 ¼ G3
B2 ¼ G XOR G2
B1 ¼ G XOR GXOR G1
B0 ¼ G3 XOR G2 XOR G1 XOR G0

In the 4-bit binary to gray code converter, input B3 is the same
as output G3, output G2 is XOR with input value B3 and B2, output
G1 and G0, with corresponding input value B2, B1 and B1, B0 being
Fig. 3. Binary to gray code converter. XOR. Fig. 6(a) and Fig. 6(b) demonstrate the simulated circuit lay-
out of proposed 4-bit Gray to Binary code convert.
4.3. BCD-to-EXCESS-3 code converter
Table 3 shows the BCD combination number and the code

excess-3 [2]. Four input and four output variables must be there
for any code which represent a decimal digit by using 4 bits. Let’s
mark the four binary input variables using the symbols B3, B2, B1
B0 and the four output ones using E3, E2, E1 and E0. In Table 3, find
a truth table that relates the input and output variables. The input
combination of the bit and its corresponding output is precisely
obtained from Table 3. We note that there may be 4binary vari-
ables with 16bit combinations, of which only ten (10) are reported
in the Truth table. A don’t-care combination is a six-bit combina-
tion not registered for the input variables. Since they never occur,
we are free to assign either a ‘1’ or a ‘0’ to the output variables,
which leads to an equivalent circuit. As seen below, the BCD-to-
excess code conversion function, reflects the adaptability obtained
by various output systems when performed with at least three gate
levels [14].
Fig. 4. The cell level based XOR design proposed in [5].
E0 ¼ B0 0
4.2. Gray to Binary converter

E1 ¼ B0 B1 þ B0 0 B1 0
A Gray to Binary code Converter is a combinational logic circuit
E2 ¼ B2 0 ðB1 þ B0 Þ þ B2 ðB1 þ B0 Þ0
that transforms a Gray code to it equivalent binary code. Table2
represents the truth table for a 4-bit Gray Code to Binary converter.
E3 ¼ B3 þ ðB1 þ B0 Þ
Accordingly, the set of inputs and outputs are depicted in Fig. 6(a),
which presents the block diagram of gray to binary code converter The BCD-to-excess-3 code converter gate, shown in Fig. 8, is the
and Fig. 6(b) represented the circuit diagram of Gray to Binary code diagrammatic diagram of QCA. As indicated in Table 3, the con-
converter. On observing the truth Table 2, the outputs can be verter gate for the BCD-to-excess-3 code has 4 (four) inputs and
expressed as: 4 (four) outputs. In QCA, the BCD-code converter is designed using
4
Fig. 5. (a) QCA Design for Binary to Gray Code Converter (b) QCA simulation for Binary to Gray Code Converter.
Fig. 6. (a) Block diagram for Gray to Binary Code Converter, (b) Circuit diagram for Gray to Binary Code Converter.
Table 2
Truth Table Gray to Binary Code converter
Truth Table
Input Output
Gray Code Binary Code
A B C D G1 G2 G3 G4
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
0
nine majority voting (MV) entry gates and five NOT gates, which is E0 ¼ B0 ;
shown in Fig. 9(a) which consists of one seventy-hundred (176)
cells with an aggregate area of 0.27 m2. Four of these are labelled 0
E1 ¼ B0 B1 þ B0 B1 0 ;
B0, B1, B2, and B3, representing the inputs to the cell. The middle
cell is the ‘‘device cell” which in QCA works out counting for three 0 0
E2 ¼ B2 ðB1 þ B0 Þ þ B2 ðB1 þ B0 Þ ;
input majority gates. The rest of the labeling out is giving output.
The circuit simulation that is depicted in Fig. 9(b), executes the
E3 ¼ B3 þ ðB1 þ B0 Þ:
Boolean function
5
Table 3
BCD to Excess-3 Output Truth Table
Input BCD Output Excess -3 code

B0 B1 B2 B3 E0 E1 E2 E3
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
Fig. 7. (a) QCA design for Gray to binary code converter, (b) Gray to binary code converter simulation result.
diagram is drawn at gate level after the logic behind the proposed
circuit is concluded. The gate-level circuit is then transformed to
QCA layout implementing majority gates, inverters, etc. as defined
in the sections above and these very designs are then simulated in
QCA Designer which leads to the result of running research efforts.
4.4. Result and performance analysis
The relative study of the introduced Gray code to Binary code

converter is presented in Table 4. It analyses the design with the
previously proposed designs in comparison to the metrics like
number of cells area utilized, number of clock cycles, latency, num-
ber of majority voter gate used, number of inverters, and wire
crossing. It can be observer that, the proposed design imparts a
great improvement in clock cycle and latency. It also reduces num-
ber of inverters and wire crossing which intern improves in circuit
cost. The relative study of the introduced Gray code to Binary code
Fig. 8. BCD to Excess-3 code converter Schematic diagram.
converter is presented in Table 5. It analyses the design with the
previously proposed designs in comparison to the metrics like
A transformation circuit has to be implemented from one sys- number of cells area utilized, number of clock (Table 6).
tem to another because each system makes use of codes for similar
data. To switch from binary code A to binary code B, the informa- 4.5. Temperature stability analysis and energy dissipation
tion lines must contain a bit of component combination as illus-
trated by code A, and a combinational circuit executes this QCA Designer has provided developers another platform; the
enhancement by using logic gate mechanism. Fig. 9(a) shows the simulation outcome, using these tools, has been distributed across
QCA design and simulation waveform for the Binary to Excess-3 various global groups [15–20]. The temperature solidity may be
code converter, and Fig. 9(b) depicts the simulation result of the optimized by determining the minimum optimum temperature
Binary to Excess-3 code converter. For a special example of trans- stability factors and maximum optimum temperature stability fac-
formation from the BCD to the excess-3 code, the code converter tors that consider both the minimum and maximum variability in
design strategy will be specified by a process. Firstly, the circuit the result polarizations for a provided Design simulation of
6
Fig. 9. (a) QCA design for BCD to Excess-3 code, (b) QCA simulation for BCD to Excess-3 code.
Table 4
Comparison on various parameters for the proposed Binary to Gray code
Binary to GrayCode Converter Cell Out Area (lm2) Clock deley Letency MV Inverter
In [24] 92 0.10 3 0.75 42 9
In [7] 137 0.16 3 0.75 6 6
In [25] 56 0.20 2 0.5 3 3
In [26] 105 0.09 3 0.75 9 6
In [27] 131 0.18 3 0.75 9 6
In [28] 255 0.43 4 1 9 3
Proposed 48 0.06 2 0.5 3 0
Table 5
Comparison on various parameters for the proposed Gray to Binary code
Gray to Binary Code Converter Cell Out Area (lm2) Clock deley Letency MV Inverter
In [24] 69 0.10 4 1 5 2
Proposed 50 0.13 1.5 0.75 3 0
Table 6
Comparison on various parameters for the proposed Binary to Excess- 3 code
Binary to Excess 3 Code Converter Cell Out Area (lm2) Clock deley Letency MV Inverter
In [14] 200 0.06 4 1 8 4
In [13] 143 0.22 2 6 8 3
Proposed 176 0.02 1 0.25 9 5
Quantum-dot Cellular Automata as suggested in [21]. This tends to shows the MIN polarization TSF which indicates that it has tem-
be used to determine the temperature range that a QCA circuit will perature stability from 1 K and 10 K. Fig. 10(b) also states that
usually operate in. MAX polarizations have a range between 1 K and 9 K. Thus,
The parameters like dissipation of energy and stability factor for the entire circuit is stable within the temperature range from
temperature are described as follows here. The pattern was tested 1 K to 9 K. If the temperature reaches beyond 9 k, and the circuit
for operation by implementing the Simulation Engine Setup as is seen to not react properly as desired. For that circuit the TSF
‘‘Coherence Vector” in the QCADesignerE instrument under a tem- limit specified is 9 K. After 6 k temperature circuit goes to unsta-
perature range starting from 1 K to 10 K. ble circuit not properly working its show in Fig. 10(a) and Fig. 10
Another aspect that can be implemented to evaluate a range of (b) with graph. The evolution of Binary to Gray code was accom-
temperatures for which the QCA circuit can be executed for its plished using the tool ‘‘Simulation engine setup” in the QCADe-
function effectively with the least energy dissipation possible signerE to execute a range of temperatures ranging from 1 K to
[2223]. 23 K.
Looking into the described result, we may easily execute that
4.5.1. Temperature stability for Binary to Gray code converter the circuit will remain active and up to 9 K temperature, it is per-
The temperature stability factor indicates how stable a circuit fectly operational. The accompanying graph indicates the differ-
remains when treated to a temperature attack. The QCA circuits ence and variation in average energy dissipation per cycle with
may control within a specified temperature range, however as the temperature rise. The temperature variation of the Binary to
the design strategy changes, the operating temperature changes Gray code code converter is shown in Table 7. The introduced cir-
as well [22]. In Fig. 10(a) and (b)10 of the 1 k to –10 k plot, it cuit will operate normally as expected up to 9 K temperature but it
is reported that temperature stability within a temperature range is found that as per temperature is increases the circuit will not
is preferable for the Binary to Gary code converter. Fig. 10(a) operate normally.
7
Fig. 10. (a) MIN polarization vs temperature, (b) MAX polarization vs temperature.
Table 7 Table 8
Average energy dissipation per cycle (ev) with varying temperatures for binary to Average energy dissipation per cycle (ev) With varying temperatures for Gray to
gray code binary code
Temp (k) Average energy dissipation (EV) Operation Status Temp (k) Average energy dissipation (EV) Operation Status
1 .00135E06 Functional 1 .00135E06 Functional
10 .00119E06 Not Functional 10 .00119E06 Not Functional
unstable circuit not properly working its show in Fig. 11(a) and
4.5.2. Temperature stability for Gray code to binary Fig. 11(b) with graph. The Gray code to Binary was tested and
In this plot it is stated that temperature stability within temper- examined for operating under a range of temperatures starting
ature range is the best for the Gary to Binary code converter in from 1 K to 18 K using the ‘‘Simulation engine setup” tool in the
Fig. 11(a) and Fig. 11(b) from 1 k to 6 k for Gray to Binary code con- QCA Designer E. We may effectively decide that the circuit will
verter. Fig. 1(a) shows the TSF of the MIN polarization, indicating it remain active and operational up to a temperature of 6 K based
has a temperature stability between 1 K and 6 K. Fig. 11(b) also on the aforementioned outcome. The graph below depicts the
notes that there is a spectrum between 1 K and 6 K for MAX polar- change and variation in average energy dissipation each cycle as
ization. Therefore, the entire circuit is stable within the range of 1– temperature rises. Table 8 demonstrates the temperature variation
6 K. If the temperature reaches beyond 6 K then it is seen that the of the Gray to Binary code converter; the suggested circuit will per-
circuit does not respond properly as desired. For that circuit the form normally as expected up to 6 K temperature, but as the tem-
specified TSF limit is 6 K. After 6 k temperature circuit goes to perature rises, the circuit will not operate correctly.
8
Table 9 the proposed designs with the previous designs. It can be noticed
Average energy dissipation per cycle (ev) for Varying temperatures that, the designs out performed the previous design in metrics like
majority gate, latency, area as well as cross over. Apart from that,
Temp (k) Average energy dissipation per cycle (EV) Operation Status
the study also includes different operational parameters such as
1 .00135E06 Functional
Energy dissipation, Temperature Stability. The result analysis com-
3 .00139E06 Functional plies that, the stable temperature regions for in which the respec-
4 .00141E06 Functional tive proposed circuits for the Binary to Gray code circuit the TSF-
5 .00142E06 Functional MAX polarizations range is l K to 11 K and TSF-MIN polarization
6 .00142E06 Functional range is 1–9 k, in case of Gray Code to Binary converter the mea-
sure for the same is recorded as 1–6 k. The result for Binary to
9 .00119E06 Functional Excess-3 code converter shows both TFS–MAX & TFS–MIN polar-
10 .00119E06 Not Functional ization is 1–9 k. The proposed designs were simulated using QCA-
11 .00124E06 Not Functional DesignerE2.0.3 The circuits will hold their operational stability on
12 .00128E06 Not Functional
exceeding their respective stable ranges during sole implementa-
14 .00124E06 Not Functional tions, but operating in the stable range will enable best output
15 .00123E06 Not Functional polarizations with the least amount of dissipation when they are
16 .00121E06 Not Functional integrated with other circuits.
Declaration of Competing Interest
4.5.3. Temperature stability for BCD to Excess-3 code The authors declare that they have no known competing finan-
In this plot, it is reported that temperature stability within the cial interests or personal relationships that could have appeared
temperature range is the best for Binary to Excess-3 code converter to influence the work reported in this paper.
of 1 k to 9 k. Fig. 12(a) shows the MAX and MIN polarization TSF
which means that it has a temperature stability between 1 K and
9 K. Fig. 12(b) also states that MIN polarizations have a stability References
between 1 K and 9 K. Thus the entire circuit is stable within the
[1] Mrinal Goswami, Anindan Mondal, Mahabub Hasan Mahalat, Bibhash Sen,
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QCA Based Design of Cost-Efficient Code Converter With Temperature Stability and Energy Efficiency Analysis

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Materials Today: Proceedings xxx (xxxx) xxx

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Materials Today: Proceedings

QCA based design of cost-efficient code converter with temperature

1. Introduction external clock signal operation in QCA. A polarized cell state is

Fig. 1. QCA Basic. Fig. 2. Clocking.

B0 ¼ G3 XOR G2 XOR G1 XOR G0

4.3. BCD-to-EXCESS-3 code converter

Table 3 shows the BCD combination number and the code

4.2. Gray to Binary converter

Input BCD Output Excess -3 code

4.4. Result and performance analysis

The relative study of the introduced Gray code to Binary code

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