Wideband Synthesizer with Integrated VCO

ADF4350
FEATURES GENERAL DESCRIPTION
Output frequency range: 137.5 MHz to 4400 MHz The ADF4350 allows implementation of fractional-N or
Fractional-N synthesizer and integer-N synthesizer integer-N phase-locked loop (PLL) frequency synthesizers
Low phase noise VCO if used with an external loop filter and external reference
Programmable divide-by-1/-2/-4/-8/-16 output frequency.
Typical rms jitter: 0.5 ps rms
The ADF4350 has an integrated voltage controlled oscillator
Power supply: 3.0 V to 3.6 V
(VCO) with a fundamental output frequency ranging from
Logic compatibility: 1.8 V
2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16
Programmable dual-modulus prescaler of 4/5 or 8/9
circuits allow the user to generate RF output frequencies as low
Programmable output power level
as 137.5 MHz. For applications that require isolation, the RF
RF output mute function
output stage can be muted. The mute function is both pin- and
3-wire serial interface
software-controllable. An auxiliary RF output is also available,
Analog and digital lock detect
which can be powered down if not in use.
Switched bandwidth fast-lock mode
Cycle slip reduction Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
APPLICATIONS from 3.0 V to 3.6 V and can be powered down when not in use.
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,
GSM, PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation
FUNCTIONAL BLOCK DIAGRAM
SDVDD AVDD DVDD VP RSET VVCO

MULTIPLEXER MUXOUT
10-BIT R ÷2
×2 COUNTER DIVIDER
REFIN DOUBLER LOCK
DETECT FLO SWITCH SW

LD
CLK
DATA DATA REGISTER FUNCTION CHARGE
LE LATCH CPOUT
PUMP
PHASE
COMPARATOR
VTUNE
VREF
VCO VCOM
CORE TEMP
INTEGER FRACTION MODULUS
REG REG REG
RFOUTA+
THIRD-ORDER OUTPUT
÷1/2/4/8/16
FRACTIONAL STAGE
RFOUTA–
INTERPOLATOR
PDBRF
MULTIPLEXER

OUTPUT RFOUTB+
N COUNTER STAGE RFOUTB–

MULTIPLEXER
ADF4350
07325-001

CE AGND DGND CPGND SDGND AGNDVCO

Figure 1.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
ADF4350

TABLE OF CONTENTS
Features .............................................................................................. 1 Register 1 ..................................................................................... 18
Applications ....................................................................................... 1 Register 2 ..................................................................................... 18
General Description ......................................................................... 1 Register 3 ..................................................................................... 20
Functional Block Diagram .............................................................. 1 Register 4 ..................................................................................... 20
Revision History ............................................................................... 2 Register 5 ..................................................................................... 20
Specifications..................................................................................... 3 Initialization Sequence .............................................................. 21
Timing Characteristics ................................................................ 5 RF Synthesizer—A Worked Example ...................................... 21
Absolute Maximum Ratings............................................................ 6 Modulus ....................................................................................... 21
Transistor Count ........................................................................... 6 Reference Doubler and Reference Divider ............................. 21
ESD Caution .................................................................................. 6 12-Bit Programmable Modulus ................................................ 21
Pin Configuration and Function Descriptions ............................. 7 Cycle Slip Reduction for Faster Lock Times ........................... 22
Typical Performance Characteristics ............................................. 9 Spurious Optimization and Fast lock ...................................... 22
Circuit Description ......................................................................... 11 Fast-Lock Timer and Register Sequences ............................... 22
Reference Input Section ............................................................. 11 Fast Lock—An Example ............................................................ 22
RF N Divider ............................................................................... 11 Fast Lock—Loop Filter Topology............................................. 23
INT, FRAC, MOD, and R Counter Relationship.................... 11 Spur Mechanisms ....................................................................... 23
INT N MODE ............................................................................. 11 Spur Consistency and Fractional Spur Optimization ........... 24
R Counter .................................................................................... 11 Phase Resync ............................................................................... 24
Phase Frequency Detector (PFD) and Charge Pump ............ 11 Applications Information .............................................................. 25
MUXOUT and LOCK Detect ................................................... 12 Direct Conversion Modulator .................................................. 25
Input Shift Registers ................................................................... 12 Interfacing ................................................................................... 26
Program Modes .......................................................................... 12 PCB Design Guidelines for a Chip Scale Package ................. 26
VCO.............................................................................................. 12 Output Matching ........................................................................ 27
Output Stage ................................................................................ 13 Outline Dimensions ....................................................................... 28
Register Maps .................................................................................. 14 Ordering Guide .......................................................................... 28
Register 0 ..................................................................................... 18

REVISION HISTORY
11/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 28
 ADF4350

SPECIFICATIONS
AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating
temperature range is −40°C to +85°C.
Table 1.
B Version
Parameter Min Typ Max Unit Conditions/Comments
REFIN CHARACTERISTICS
Input Frequency 10 105 MHz For f < 10 MHz ensure slew rate > 21 V/μs
Input Sensitivity 0.7 AVDD V p-p Biased at AVDD/2 1
Input Capacitance 10 pF
Input Current ±60 μA
PHASE DETECTOR
Phase Detector Frequency 2 32 MHz
CHARGE PUMP
ICP Sink/Source 3 With RSET = 5.1 kΩ
High Value 5 mA
Low Value 0.312 mA
RSET Range 2.7 10 kΩ
Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ 2.5 V
ICP vs. VCP 1.5 % 0.5 V ≤ VCP ≤ 2.5 V
ICP vs. Temperature 2 % VCP = 2.0 V
LOGIC INPUTS
Input High Voltage, VINH 1.5 V
Input Low Voltage, VINL 0.6 V
Input Current, IINH/IINL ±1 μA
Input Capacitance, CIN 3.0 pF
LOGIC OUTPUTS
Output High Voltage, VOH DVDD − 0.4 V CMOS output chosen
Output High Current, IOH 500 μA
Output Low Voltage, VOL 0.4 V IOL = 500 μA
POWER SUPPLIES
AVDD 3.0 3.6 V
DVDD, VVCO, SDVDD, VP AVDD These voltages must equal AVDD
DIDD + AIDD 4 21 27 mA
Output Dividers 6 to 24 mA Each output divide-by-2 consumes 6 mA
IVCO4 70 80 mA
IRFOUT4 21 26 mA RF output stage is programmable
Low Power Sleep Mode 7 1000 μA
RF OUTPUT CHARACTERISTICS
Maximum VCO Output Frequency 4400 MHz
Minimum VCO Output Frequency 2200 MHz Fundamental VCO mode
Minimum VCO Output Frequency 137.5 MHz 2200 MHz fundamental output and divide by 16 selected
Using Dividers
VCO Sensitivity 33 MHz/V
Frequency Pushing (Open-Loop) 1 MHz/V
Frequency Pulling (Open-Loop) 90 kHz Into 2.00 VSWR load
Harmonic Content (Second) −19 dBc Fundamental VCO output
Harmonic Content (Third) −13 dBc Fundamental VCO output
Harmonic Content (Second) −20 dBc Divided VCO output
Harmonic Content (Third) −10 dBc Divided VCO output
Minimum RF Output Power 5 −4 dBm Programmable in 3 dB steps
Maximum RF Output Power5 5 dBm
Output Power Variation ±1 dB
Minimum VCO Tuning Voltage 0.5 V
Maximum VCO Tuning Voltage 2.5 V

Rev. 0 | Page 3 of 28
ADF4350
B Version
Parameter Min Typ Max Unit Conditions/Comments
NOISE CHARACTERISTICS
VCO Phase-Noise Performance 6 −89 dBc/Hz 10 kHz offset from 2.2 GHz carrier
−114 dBc/Hz 100 kHz offset from 2.2 GHz carrier
−134 dBc/Hz 1 MHz offset from 2.2 GHz carrier
−148 dBc/Hz 5 MHz offset from 2.2 GHz carrier
−86 dBc/Hz 10 kHz offset from 3.3 GHz carrier
−111 dBc/Hz 100 kHz offset from 3.3 GHz carrier
−134 dBc/Hz 1 MHz offset from 3.3 GHz carrier
−145 dBc/Hz 5 MHz offset from 3.3 GHz carrier
−83 dBc/Hz 10 kHz offset from 4.4 GHz carrier
−110 dBc/Hz 100 kHz offset from 4.4 GHz carrier
−132 dBc/Hz 1 MHz offset from 4.4 GHz carrier
−145 dBc/Hz 5 MHz offset from 4.4 GHz carrier
Normalized In-Band Phase Noise Floor 7 −213 dBc/Hz
In-Band Phase Noise 8 −97 dBc/Hz 3 kHz offset from 2113.5 MHz carrier
Integrated RMS Jitter 9 0.5 ps
Spurious Signals Due to PFD Frequency −70 dBc
Level of Signal With RF Mute Enabled −40 dBm
1
AC coupling ensures AVDD/2 bias.
2
Guaranteed by design. Sample tested to ensure compliance.
3
ICP is internally modified to maintain constant loop gain over the frequency range.
4
TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; prescaler = 8/9; fREFIN = 100 MHz; fPFD = 25 MHz; fRF = 4.4 GHz.
5
Using 50 Ω resistors to VVCO, into a 50 Ω load. Power measured with auxiliary RF output disabled. The current consumption of the auxiliary output is the same as for the
main output.
6
The noise of the VCO is measured in open-loop conditions.
7
This figure can be used to calculate phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output use the following formula: −213 +
10log(fPFD) + 20logN . The value given is the lowest noise mode.
8
fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 10 kHz; VCO frequency = 4227 MHz, output divide by two enabled. RFOUT = 2113.5 MHz; N = 169; loop BW = 40 kHz,
ICP = 313 μA; low noise mode. The noise was measured with an EVAL-ADF4350EB1Z and the Agilent E5052A signal source analyzer.
9
fREFIN = 100 MHz; fPFD = 25 MHz; VCO frequency = 4400 MHz, RFOUT = 4400 MHz; N = 176; loop BW = 40 kHz, ICP = 313 μA; low noise mode. The noise was measured with
an EVAL-ADF4350EB1Z and the Agilent E5052A signal source analyzer.

Rev. 0 | Page 4 of 28
 ADF4350
TIMING CHARACTERISTICS
AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless
otherwise noted.

Table 2.
Parameter Limit (B Version) Unit Test Conditions/Comments
t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width

t4 t5

CLK

t2 t3

DB2 DB1 DB0 (LSB)

DATA DB31 (MSB) DB30 (CONTROL BIT C3) (CONTROL BIT C2) (CONTROL BIT C1)

t7

LE

t1 t6

07325-002
LE

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 28
ADF4350

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
Table 3. rating only; functional operation of the device at these or any
Parameter Rating other conditions above those indicated in the operational
AVDD to GND1 −0.3 V to +3.9 V section of this specification is not implied. Exposure to absolute
AVDD to DVDD −0.3 V to +0.3 V maximum rating conditions for extended periods may affect
VVCO to GND −0.3 V to +3.9 V device reliability.
VVCO to AVDD −0.3 V to +0.3 V This device is a high-performance RF integrated circuit with an
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V ESD rating of <0.5 kV and is ESD sensitive. Proper precautions
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V should be taken for handling and assembly.
REFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to +85°C TRANSISTOR COUNT
Storage Temperature Range −65°C to +125°C 24202 (CMOS) and 918 (bipolar)
Maximum Junction Temperature 150°C
LFCSP θJA Thermal Impedance 27.3°C/W ESD CAUTION
(Paddle-Soldered)
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
1
GND = AGND = DGND = 0 V

Rev. 0 | Page 6 of 28
 ADF4350

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

MUXOUT
SDVDD
SDGND

PDBRF
DGND
REFIN
DVDD

LD
32
31
30
29
28
27
26
25
CLK 1 24 VREF
DATA 2 PIN 1 23 VCOM
INDICATOR
LE 3 22 RSET
CE 4
ADF4350 21 AGNDVCO
SW 5
TOP VIEW 20 VTUNE
VP 6 (Not to Scale) 19 TEMP
CPOUT 7 18 AGNDVCO
CPGND 8 17 VVCO

AGNDVCO 11
AGND 9
AVDD 10

RFOUTA+ 12
RFOUTA− 13
RFOUTB+ 14
RFOUTB− 15
VVCO 16

07325-003
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
2 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register
that is selected by the three LSBs.
4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
A logic high on this pin powers up the device depending on the status of the power-down bits.
5 SW Fast-Lock Switch. A connection should be made from the loop filter to this pin when using the fast-lock mode.
6 VP Charge Pump Power Supply. This pin is to be equal to AVDD. Decoupling capacitors to the ground plane are to
be placed as close as possible to this pin.
7 CPOUT Charge Pump Output. When enabled, this provides ±ICP to the external loop filter. The output of the loop filter is
connected to VTUNE to drive the internal VCO.
8 CPGND Charge Pump Ground. This is the ground return pin for CPOUT.
9 AGND Analog Ground. This is a ground return pin for AVDD.
10 AVDD Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are
to be placed as close as possible to this pin. AVDD must have the same value as DVDD.
11, 18, 21 AGNDVCO VCO Analog Ground. These are the ground return pins for the VCO.
12 RFOUTA+ VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.
13 RFOUTA− Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided
down version is available.
14 RFOUTB+ Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down
version is available.
15 RFOUTB− Complementary Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a
divided down version is available.
16, 17 VVCO Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to these pins. VVCO must have the same value as AVDD.
19 TEMP Temperature Compensation Output. Decoupling capacitors to the ground plane are to be placed as close as
possible to this pin.
20 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage.

Rev. 0 | Page 7 of 28
ADF4350
Pin No. Mnemonic Description
22 RSET Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage
bias at the RSET pin is 0.55 V. The relationship between ICP and RSET is
25.5
I CP =
R SET
where:
RSET = 5.1 kΩ
ICP = 5 mA
23 VCOM Internal Compensation Node Biased at Half the Tuning Range. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin.
24 VREF Reference Voltage. Decoupling capacitors to the ground plane should be placed as close as possible to this pin.
25 LD Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock. A logic low output indicates loss of PLL lock.
26 PDBRF RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
27 DGND Digital Ground. Ground return path for DVDD.
28 DVDD Digital Power Supply. This pin should be the same voltage as AVDD. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin.
29 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
30 MUXOUT Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
31 SDGND Digital Sigma-Delta (Σ-Δ) Modulator Ground. Ground return path for the Σ-Δ modulator.
32 SDVDD Power Supply Pin for the Digital Σ-Δ Modulator. Should be the same voltage as AVDD. Decoupling capacitors to
the ground plane are to be placed as close as possible to this pin.
33 EP Exposed Pad.

Rev. 0 | Page 8 of 28
 ADF4350

TYPICAL PERFORMANCE CHARACTERISTICS

–40 –70
FUND
–50 –80 DIV2
DIV4
–60 DIV8
–90
DIV16
–70
PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

–100
–80

–90 –110

–100 –120

–110 –130
–120
–140
–130
–150
–140

–150 –160

–160 –170

07325-028

07325-031
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 4. Open-Loop VCO Phase Noise, 2.2 GHz Figure 7. Closed-Loop Phase Noise, Fundamental VCO and Dividers,
VCO = 2.2 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz

–40 –70
FUND
–50 –80 DIV2
DIV4
–60 DIV8
–90
DIV16
–70
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)

–100
–80

–90 –110

–100 –120

–110 –130
–120
–140
–130
–150
–140
–150 –160

–160 –170

07325-032
1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
07325-029

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 5. Open-Loop VCO Phase Noise, 3.3 GHz Figure 8. Closed-Loop Phase Noise, Fundamental VCO and Dividers,
VCO = 3.3 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz
–40 –70
FUND
–50 –80 DIV2
DIV4
–60 DIV8
–90
DIV16
–70
PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

–100
–80

–90 –110

–100 –120
–110 –130
–120
–140
–130
–150
–140

–150 –160

–160 –170
1k 10k 100k 1M 10M 100M
07325-030

1k 10k 100k 1M 10M 100M

07325-033

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 6. Open-Loop VCO Phase Noise, 4.4 GHz Figure 9. Closed-Loop Phase Noise, Fundamental VCO and Dividers,
VCO = 4.4 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz

Rev. 0 | Page 9 of 28
ADF4350
0 0

–20 –20

–40 –40
PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

–60 –60

–80 –80

–100 –100

–120 –120

–140 –140

–160 –160

07325-034

07325-037
1k 10k 100k 1M 10M 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 10. Integer-N Phase Noise and Spur Performance. GSM900 Band, Figure 13. Fractional-N Spur Performance. Low Noise Mode, RFOUT =
RFOUT = 904 MHz, REFIN = 100 MHz, PFD = 800 kHz, Output Divide-by-4 2.591 GHz, REFIN = 105 MHz, PFD = 17.5 MHz, Output Divide-by-1 Selected;
Selected; Loop-Filter Bandwidth = 16 kHz, Channel Spacing = 200 kHz. Loop Filter Bandwidth = 20 kHz, Channel Spacing = 100 kHz.

0 0

–20 –20

–40 –40
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)

–60 –60

–80 –80

–100 –100

–120 –120

–140 –140

–160 –160

07325-038
07325-035

1k 10k 100k 1M 10M 1k 10k 100k 1M 10M

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 11. Fractional-N Spur Performance; Low Noise Mode. W-CDMA Band, Figure 14. Fractional-N Spur Performance. Low Spur Mode RFOUT =
RFOUT = 2113.5 MHz, REFIN = 100 MHz, PFD = 25 MHz, Output Divide-by-2 2.591 GHz, REFIN = 105 MHz, PFD = 17.5 MHz, Output Divide-by-1 Selected.
Selected; Loop Filter Bandwidth = 40 kHz, Channel Spacing = 200 kHz. Loop Filter Bandwidth = 20 kHz, Channel Spacing = 100 kHz (Note That
Fractional Spurs Are Removed and Only the Integer Boundary Spur Remains
in Low Spur Mode).

0 3.02

CSR OFF
–20 3.01
CSR ON

–40
3.00
PHASE NOISE (dBc/Hz)

FREQUENCY (GHz)

–60
2.99
–80
2.98
–100
2.97
–120

2.96
–140

–160 2.95
07325-036

07325-039

1k 10k 100k 1M 10M 0 100 200 300 400 500 600

FREQUENCY (Hz) TIME (µs)

Figure 12. Fractional-N Spur Performance. Low Spur Mode, W-CDMA Band Figure 15. Lock Time for 100 MHz Jump from 3070 MHz to 2970 MHz with
RFOUT = 2113.5 MHz, REFIN = 100 MHz, PFD = 25 MHz, Output Divide-by-2 CSR On and Of f, PFD = 25 MHz, ICP = 313 μA, Loop Filter Bandwidth = 20 kHz
Selected; Loop Filter Bandwidth = 40 kHz, Channel Spacing = 200 kHz

Rev. 0 | Page 10 of 28
 ADF4350

CIRCUIT DESCRIPTION
RF N DIVIDER N = INT + FRAC/MOD
REFERENCE INPUT SECTION FROM
VCO OUTPUT/
The reference input stage is shown in Figure 16. SW1 and SW2 OUTPUT DIVIDERS TO PFD
N COUNTER
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are THIRD-ORDER
FRACTIONAL
opened. This ensures that there is no loading of the REFIN pin INTERPOLATOR

during power-down.
POWER-DOWN INT MOD FRAC
CONTROL REG REG VALUE

07325-006
NC 100kΩ

SW2
REFIN NC TO R COUNTER Figure 17. RF INT Divider
BUFFER
SW1
INT N MODE

07325-005
SW3
NO
If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the
Figure 16. Reference Input Stage synthesizer operates in integer-N mode. The DB8 in Register 2
(LDF) should be set to 1 to get integer-N digital lock detect.
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback R COUNTER
path. The division ratio is determined by INT, FRAC and MOD The 10–bit R counter allows the input reference frequency
values, which build up this divider. (REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 1023 are allowed.
INT, FRAC, MOD, AND R COUNTER RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the PHASE FREQUENCY DETECTOR (PFD) AND
R counter, make it possible to generate output frequencies CHARGE PUMP
that are spaced by fractions of the PFD frequency. See the RF The phase frequency detector (PFD) takes inputs from the
Synthesizer—A Worked Example section for more information. R counter and N counter and produces an output proportional
The RF VCO frequency (RFOUT) equation is to the phase and frequency difference between them. Figure 18
RFOUT = fPFD × (INT + (FRAC/MOD)) (1) is a simplified schematic of the phase frequency detector. The
PFD includes a fixed delay element that sets the width of the
where RFOUT is the output frequency of external voltage antibacklash pulse, which is typically 3 ns. This pulse ensures
controlled oscillator (VCO). there is no dead zone in the PFD transfer function, and gives a
INT is the preset divide ratio of the binary 16-bit counter consistent reference spur level.
(23 to 65535 for 4/5 prescaler, 75 to 65,535 for 8/9 prescaler).
UP
MOD is the preset fractional modulus (2 to 4095). HIGH D1 Q1

FRAC is the numerator of the fractional division (0 to MOD − 1). U1

+IN CLR1
fPFD = REFIN × [(1 + D)/(R × (1 + T))] (2)
where: CHARGE
DELAY U3 CP
REFIN is the reference input frequency. PUMP

D is the REFIN doubler bit.

T is the REFIN divide-by-2 bit (0 or 1).
R is the preset divide ratio of the binary 10-bit programmable CLR2 DOWN
HIGH D2 Q2
reference counter (1 to 1023).
U2
07325-007

–IN

Figure 18. PFD Simplified Schematic

Rev. 0 | Page 11 of 28
ADF4350
MUXOUT AND LOCK DETECT (R0) must be written to, to ensure the modulus value is loaded
The output multiplexer on the ADF4350 allows the user correctly. Divider select in Register 4 (R4) is also double buf-
to access various internal points on the chip. The state of fered, but only if DB13 of Register 2 (R2) is high.
MUXOUT is controlled by M3, M2, and M1 (for details, VCO
see Figure 26). Figure 19 shows the MUXOUT section in The VCO core in the ADF4350 consists of three separate VCOs
block diagram form. each of which uses 16 overlapping bands, as shown in Figure 20,
R COUNTER INPUT
to allow a wide frequency range to be covered without a large
DVDD
VCO sensitivity (KV) and resultant poor phase noise and spu-
rious performance.
THREE-STATE-OUTPUT
The correct VCO and band are chosen automatically by the
DVDD
VCO and band select logic at power-up or whenever Register 0
DGND
(R0) is updated.
R COUNTER OUTPUT
MUX CONTROL
N COUNTER OUTPUT MUXOUT VCO and band selection take 10 PFD cycles × band select clock
ANALOG LOCK DETECT divider value. The VCO VTUNE is disconnected from the output
DIGITAL LOCK DETECT
of the loop filter and is connected to an internal reference voltage.
RESERVED 2.8
07325-008

2.4
DGND

Figure 19. MUXOUT Schematic 2.0

INPUT SHIFT REGISTERS 1.6

VTUNE (V)

The ADF4350 digital section includes a 10–bit RF R counter,

1.2
a 16–bit RF N counter, a 12-bit FRAC counter, and a 12–bit
modulus counter. Data is clocked into the 32–bit shift register 0.8
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of six latches 0.4

on the rising edge of LE. The destination latch is determined by

0
the state of the three control bits (C3, C2, and C1) in the shift

07325-009
1800

2000

2200

2400

2600

2800

3000

3200

3400

3600

3800

4000

4200

4400
4600
register. These are the 3 LSBs, DB2, DB1, and DB0, as shown
FREQUENCY (MHz)
in Figure 2. The truth table for these bits is shown in Table 5. Figure 20. VTUNE vs. Frequency
Figure 23 shows a summary of how the latches are programmed.
The R counter output is used as the clock for the band select
Table 5. C3, C2, and C1 Truth Table logic. A programmable divider is provided at the R counter
Control Bits output to allow division by 1 to 255 and is controlled by
C3 C2 C1 Register Bits [BS8:BS1] in Register 4 (R4). When the required PFD
0 0 0 Register 0 (R0) frequency is higher than 125 kHz, the divide ratio should be
0 0 1 Register 1 (R1) set to allow enough time for correct band selection.
0 1 0 Register 2 (R2) After band select, normal PLL action resumes. The nominal
0 1 1 Register 3 (R3) value of KV is 33 MHz/V when the N-divider is driven from the
1 0 0 Register 4 (R4) VCO output or this value divided by D. D is the output divider
1 0 1 Register 5 (R5) value if the N-divider is driven from the RF divider output
PROGRAM MODES (chosen by programming Bits [D12:D10] in Register 4 (R4).
The ADF4350 contains linearization circuitry to minimize
Table 5 and Figure 23 through Figure 29 show how the program
any variation of the product of ICP and KV to keep the loop
modes are to be set up in the ADF4350.
bandwidth constant.
A number of settings in the ADF4350 are double buffered.
These include the modulus value, phase value, R counter value,
reference doubler, reference divide-by-2, and current setting.
This means that two events have to occur before the part uses
a new value of any of the double buffered settings. First, the
new value is latched into the device by writing to the appropriate
register. Second, a new write must be performed on Register R0.
For example, any time the modulus value is updated, Register 0
Rev. 0 | Page 12 of 28
 ADF4350
The VCO shows variation of KV as the VTUNE varies within the OUTPUT STAGE
band and from band-to-band. It has been shown for wideband The RFOUTA+ and RFOUTA− pins of the ADF4350 are connected
applications covering a wide frequency range (and changing to the collectors of an NPN differential pair driven by buffered
output dividers) that a value of 33 MHz/V provides the most outputs of the VCO, as shown in Figure 22. To allow the user to
accurate KV as this is closest to an average value. Figure 21 optimize the power dissipation vs. the output power requirements,
shows how KV varies with fundamental VCO frequency along the tail current of the differential pair is programmable by
with an average value for the frequency band. Users may prefer Bits [D2:D1] in Register 4 (R4). Four current levels may be set.
this figure when using narrowband designs. These levels give output power levels of −4 dBm, −1 dBm, +2
80
dBm, and +5 dBm, respectively, using a 50 Ω resistor to AVDD
and ac coupling into a 50 Ω load. Alternatively, both outputs
70 can be combined in a 1 + 1:1 transformer or a 180° microstrip
60
coupler (see the Output Matching section). If the outputs are
VCO SENSITIVITY (MHz/V)

used individually, the optimum output stage consists of a shunt

50
inductor to VVCO. The unused complementary output must
40 be terminated with a similar circuit to the used output.

30
An auxiliary output stage exists on Pins RFOUTB+ and RFOUTB−
providing a second set of differential outputs which can be
20 used to drive another circuit, or which can be powered down
10
if unused.
07325-133

Another feature of the ADF4350 is that the supply current to

0
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 the RF output stage can be shut down until the part achieves
FREQUENCY (GHz)
lock as measured by the digital lock detect circuitry. This is
Figure 21. KV vs. Frequency enabled by the mute till lock detect (MTLD) bit in Register 4 (R4).
In fixed frequency applications, the ADF4350 VTUNE may RFOUTA+ RFOUTA–

vary with ambient temperature switching from hot to cold.

In extreme cases, the drift causes VTUNE to drop to a very low
level (<0.25 V) and can cause loss of lock. This becomes an
BUFFER/
issue only at fundamental VCO frequencies less than 2.95 GHz VCO DIVIDE-BY-
1/2/4/8/16
and at ambient temperatures below 0°C.
In cases such as these, if the ambient temperature decreases

07325-010
below 0°C, the frequency needs to be reprogrammed (R0 updated)
to avoid VTUNE dropping to a level close to 0 V. Reprogramming Figure 22. Output Stage
the part chooses a more suitable VCO band, and thus avoids
the low VTUNE issue. Any further temperature drops of more
than 20°C (below 0°C) also require further reprogramming.
Any increases in the ambient temperature do not require repro-
gramming.

Rev. 0 | Page 13 of 28
ADF4350

REGISTER MAPS
REGISTER 0
RESERVED

CONTROL
16-BIT INTEGER VALUE (INT) 12-BIT FRACTIONAL VALUE (FRAC)
BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(0)

REGISTER 1
PRESCALER

CONTROL
RESERVED 12-BIT PHASE VALUE (PHASE) DBR1 12-BIT MODULUS VALUE (MOD) DBR 1
BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 PR1 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)

REGISTER 2
DOUBLER DBR 1

DBR 1

DOUBLE BUFF
REFERENCE
RESERVED

CP THREE-
LOW CHARGE

COUNTER
POLARITY
NOISE AND PUMP

RESET
STATE
RDIV2

LOW SPUR CURRENT

LDF

LDP
MODES MUXOUT 10-BIT R COUNTER DBR 1 SETTING DBR 1 CONTROL

PD
PD
BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 L2 L1 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 C3(0) C2(1) C1(0)

REGISTER 3
RESERVED

CLK
DIV
RESERVED RESERVED
CSR

MODE 12-BIT CLOCK DIVIDER VALUE CONTROL

BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 0 0 0 0 F1 0 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(1)

REGISTER 4
AUX OUTPUT

AUX OUTPUT
VCO POWER

RF OUTPUT
FEEDBACK

DBB 2
ENABLE
SELECT

ENABLE
SELECT

AUX
DOWN

MTLD

RESERVED DIVIDER OUTPUT OUTPUT

SELECT 8-BIT BAND SELECT CLOCK DIVIDER VALUE POWER CONTROL
POWER BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)

REGISTER 5
RESERVED

LD PIN CONTROL
RESERVED MODE RESERVED RESERVED BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 D15 D14 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(0) C1(1)

07325-011

1 DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

2 DBB = DOUBLE BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0, IF AND ONLY IF DB13 OF REGISTER 2 IS HIGH.

Figure 23. Register Summary

Rev. 0 | Page 14 of 28
 RESERVED
ADF4350

CONTROL
16-BIT INTEGER VALUE (INT) 12-BIT FRACTIONAL VALUE (FRAC) BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(0)

N16 N15 ... N5 N4 N3 N2 N1 INTEGER VALUE (INT) F12 F11 .......... F2 F1 FRACTIONAL VALUE (FRAC)
0 0 ... 0 0 0 0 0 NOT ALLOWED 0 0 .......... 0 0 0
0 0 ... 0 0 0 0 1 NOT ALLOWED 0 0 .......... 0 1 1
0 0 ... 0 0 0 1 0 NOT ALLOWED 0 0 .......... 1 0 2
. . ... . . . . . ... 0 0 .......... 1 1 3
0 0 ... 1 0 1 1 0 NOT ALLOWED . . .......... . . .
0 0 ... 1 0 1 1 1 23 . . .......... . . .
0 0 ... 1 1 0 0 0 24 . . .......... . . .
. . ... . . . . . ... 1 1 .......... 0 0 4092
1 1 ... 1 1 1 0 1 65533 1 1 .......... 0 1 4093
1 1 ... 1 1 1 1 0 65534 1 1 .......... 1 0 4094

07325-012
1 1 ... 1 1 1 1 1 65535 1 1 ......... 1 1 4095

INTmin = 75 with prescaler = 8/9

Figure 24. Register 0 (R0)

PRESCALER

CONTROL
RESERVED 12-BIT PHASE VALUE (PHASE) DBR 12-BIT MODULUS VALUE (MOD) DBR BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 PR1 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)

P1 PRESCALER P12 P11 .......... P2 P1 PHASE VALUE (PHASE) M12 M11 .......... M2 M1 INTERPOLATOR MODULUS (MOD)
0 4/5 0 0 .......... 0 0 0 0 0 .......... 1 0 2
1 8/9 0 0 .......... 0 1 1 (RECOMMENDED) 0 0 .......... 1 1 3

0 0 .......... 1 0 2 . . .......... . . .
. . .......... . . .
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 4092
. . .......... . . .
1 1 .......... 0 1 4093
. . .......... . . . 1 1 .......... 1 0 4094
1 1 .......... 0 0 4092 1 1 .......... 1 1 4095
1 1 .......... 0 1 4093

07325-013
1 1 .......... 1 0 4094
1 1 .......... 1 1 4095

Figure 25. Register 1 (R1)

Rev. 0 | Page 15 of 28
ADF4350

DOUBLER DBR

POWER-DOWN
DOUBLE BUFF
DBR
REFERENCE
RESERVED

CP THREE-

COUNTER
POLARITY
LOW CHARGE

RESET
PUMP

STATE
NOISE AND

RDIV2
CURRENT CONTROL

LDF

LDP
LOW SPUR

PD
MODES MUXOUT 10-BIT R COUNTER DBR SETTING BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 L2 L1 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 C3(0) C2(1) C1(0)

RD2 REFERENCE COUNTER

L1 L2 NOISE MODE DOUBLER D1 DOUBLEBUFFER U6 LDF U1
R4 DB22-20 RESET
0 0 LOW NOISE MODE 0 DISABLED 0 FRAC-N
0 DISABLED 0 DISABLED
0 1 RESERVED 1 ENABLED 1 INT-N
1 ENABLED 1 ENABLED
1 0 RESERVED
RD1 REFERENCE DIVIDE BY 2
1 1 LOW SPUR MODE ICP (mA) U2 CP
U5 LDP THREE-STATE
0 DISABLED CP4 CP3 CP2 CP1 5.1kΩ
0 10ns 0 DISABLED
1 ENABLED 0 0 0 0 0.31
0 0 0 1 0.63 1 6ns 1 ENABLED
0 0 1 0 0.94
R10 R9 .......... R2 R1 R DIVIDER (R)
0 0 1 1 1.25 U4 PD POLARITY U3 POWER DOWN
0 0 .......... 0 1 1 0 1 0 0 1.56
0 NEGATIVE 0 DISABLED
0 0 .......... 1 0 2 0 1 0 1 1.88
1 POSITIVE 1 ENABLED
. . .......... . . . 0 1 1 0 2.19
. . .......... . . . 0 1 1 1 2.50
1 0 0 0 2.81
. . .......... . . .
1 0 0 1 3.13
1 1 .......... 0 0 1020
1 0 1 0 3.44
1 1 .......... 0 1 1021
1 0 1 1 3.75
1 1 .......... 1 0 1022 1 1 0 0 4.06
1 1 .......... 1 1 1023 1 1 0 1 4.38
1 1 1 0 4.69
1 1 1 1 5.00
M3 M2 M1 OUTPUT
0 0 0 THREE-STATE OUTPUT
0 0 1 DVDD
0 1 0 DGND
0 1 1 R DIVIDER OUTPUT
1 0 0 N DIVIDER OUTPUT
1 0 1 ANALOG LOCK DETECT

07325-014
1 1 0 DIGITAL LOCK DETECT
1 1 1 RESERVED

Figure 26. Register 2 (R2)

RESERVED

RESERVED

CLK
DIV CONTROL
CSR

RESERVED MODE 12-BIT CLOCK DIVIDER VALUE BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 0 0 0 0 F1 0 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(1)

CYCLE SLIP D12 D11 .......... D2 D1 CLOCK DIVIDER VALUE

F1
REDUCTION 0 0 .......... 0 0 0
0 DISABLED 0 0 .......... 0 1 1
1 ENABLED 0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
C2 C1 CLOCK DIVIDER MODE
. . .......... . . .
0 0 CLOCK DIVIDER OFF
1 1 .......... 0 0 4092
0 1 FAST-LOCK ENABLE 1 1 .......... 0 1 4093
07325-015

1 0 RESYNC ENABLE 1 1 .......... 1 0 4094

1 1 RESERVED 1 1 .......... 1 1 4095

Figure 27. Register 3 (R3)

Rev. 0 | Page 16 of 28
 ADF4350

VCO POWER-

AUX OUTPUT

AUX OUTPUT

RF OUTPUT
FEEDBACK

ENABLE
SELECT

ENABLE
SELECT
AUX

DOWN

MTLD
DIVIDER OUTPUT OUTPUT CONTROL
RESERVED SELECT DBB 8-BIT BAND SELECT CLOCK DIVIDER VALUE POWER POWER BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)

FEEDBACK VCO
D13 SELECT D2 D1 OUTPUT POWER
D9 POWER-DOWN
0 DIVIDED 0 VCO POWERED UP 0 0 -4
1 FUNDAMENTAL 1 VCO POWERED DOWN 0 1 -1
1 0 +2
D12 D11 D10 RF DIVIDER SELECT MUTE TILL 1 1 +5
D8 LOCK DETECT
0 0 0 ÷1
0 MUTE DISABLED D3 RF OUT
0 0 1 ÷2
1 MUTE ENABLED 0 DISABLED
0 1 0 ÷4
0 1 1 ÷8 1 ENABLED
AUX OUTPUT
1 0 0 ÷16 D7 SELECT
0 D5 D4 AUX OUTPUT POWER
DIVIDED OUTPUT
BS8 BS7 .......... BS2 BS1 BAND SELECT CLOCK DIVIDER (R) 0 0 -4
1 FUNDAMENTAL
0 1 -1
0 0 .......... 0 1 1
D6 AUX OUT 1 0 +2
0 0 .......... 1 0 2
0 DISABLED 1 1 +5
. . .......... . . .
. . .......... . . . 1 ENABLED
. . .......... . . .
1 1 .......... 0 0 252
1 1 .......... 0 1 253

07325-016
1 1 .......... 1 0 254
1 1 .......... 1 1 255

Figure 28. Register 4 (R4)

RESERVED

LD PIN CONTROL
RESERVED MODE RESERVED RESERVED BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 D15 D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(0) C1(1)

D1 5 D1 4 LOCK DETECT PIN OPERATION

0 0 LOW
0 1 DIGITAL LOCK DETECT

07325-017
1 0 LOW
1 1 HIGH

Figure 29. Register 5 (R5)

Rev. 0 | Page 17 of 28
ADF4350
REGISTER 0 If neither the phase resync nor the spurious optimization
Control Bits functions are being used, it is recommended the PHASE
word be set to 1.
With Bits [C3:C1] set to 0, 0, 0, Register 0 is programmed.
Figure 24 shows the input data format for programming this 12-Bit Interpolator MOD Value
register. This programmable register sets the fractional modulus. This
16-Bit INT Value is the ratio of the PFD frequency to the channel step resolution
on the RF output. See the RF Synthesizer—A Worked Example
These sixteen bits set the INT value, which determines the
section for more information.
integer part of the feedback division factor. It is used in
Equation 1 (see the INT, FRAC, MOD, and R Counter REGISTER 2
Relationship section). All integer values from 23 to 65,535 Control Bits
are allowed for 4/5 prescaler. For 8/9 prescaler, the minimum With Bits [C3:C1] set to 0, 1, 0, Register 2 is programmed.
integer value is 75. Figure 26 shows the input data format for programming this
12-Bit FRAC Value register.
The 12 FRAC bits set the numerator of the fraction that is input Low Noise and Low Spur Modes
to the Σ-Δ modulator. This, along with INT, specifies the new The noise modes on the ADF4350 are controlled by DB30 and
frequency channel that the synthesizer locks to, as shown in the DB29 in Register 2 (see Figure 26). The noise modes allow the
RF Synthesizer—A Worked Example section. FRAC values from user to optimize a design either for improved spurious perfor-
0 to MOD − 1 cover channels over a frequency range equal to mance or for improved phase noise performance.
the PFD reference frequency.
When the lowest spur setting is chosen, dither is enabled. This
REGISTER 1 randomizes the fractional quantization noise so it resembles
Control Bits white noise rather than spurious noise. As a result, the part is
With Bits [C3:C1] set to 0, 0, 1, Register 1 is programmed. optimized for improved spurious performance. This operation
Figure 25 shows the input data format for programming would normally be used when the PLL closed-loop bandwidth
this register. is wide, for fast-locking applications. Wide loop bandwidth is
seen as a loop bandwidth greater than 1/10 of the RFOUT channel
Prescaler Value
step resolution (fRES). A wide loop filter does not attenuate the
The dual modulus prescaler (P/P + 1), along with the INT, spurs to the same level as a narrow loop bandwidth.
FRAC, and MOD counters, determines the overall division
For best noise performance, use the lowest noise setting option.
ratio from the VCO output to the PFD input.
As well as disabling the dither, this setting also ensures that the
Operating at CML levels, the prescaler takes the clock from the charge pump is operating in an optimum region for noise
VCO output and divides it down for the counters. It is based on performance. This setting is extremely useful where a narrow
a synchronous 4/5 core. When set to 4/5, the maximum RF loop filter bandwidth is available. The synthesizer ensures
frequency allowed is 3 GHz. Therefore, when operating the extremely low noise and the filter attenuates the spurs. The
ADF4350 above 3 GHz, this must be set to 8/9. The prescaler typical performance characteristics give the user an idea of
limits the INT value, where P is 4/5, NMIN is 23 and P is 8/9, the trade-off in a typical W-CDMA setup for the different
NMIN is 75. noise and spur settings.
In the ADF4350, PR1 in Register 1 sets the prescaler values. MUXOUT
12-Bit Phase Value The on-chip multiplexer is controlled by Bits [DB28:DB26] (see
These bits control what is loaded as the phase word. The word Figure 26).
must be less than the MOD value programmed in Register 1. Reference Doubler
The word is used to program the RF output phase from 0° to
Setting DB25 to 0 feeds the REFIN signal directly to the 10–bit
360° with a resolution of 360°/MOD. See the Phase Resync
R counter, disabling the doubler. Setting this bit to 1 multiplies
section for more information. In most applications, the phase
the REFIN frequency by a factor of 2 before feeding into the
relationship between the RF signal and the reference is not
10-bit R counter. When the doubler is disabled, the REFIN
important. In such applications, the phase value can be used
falling edge is the active edge at the PFD input to the fractional
to optimize the fractional and subfractional spur levels. See the
synthesizer. When the doubler is enabled, both the rising and
Spur Consistency and Fractional Spur Optimization section for
falling edges of REFIN become active edges at the PFD input.
more information.

Rev. 0 | Page 18 of 28
 ADF4350
When the doubler is enabled and the lowest spur mode is Lock Detect Precision (LDP)
chosen, the in-band phase noise performance is sensitive to When DB7 is set to 0, 40 consecutive PFD cycles of 10 ns must
the REFIN duty cycle. The phase noise degradation can be as occur before digital lock detect is set. When this bit is programmed
much as 5 dB for the REFIN duty cycles outside a 45% to 55% to 1, 40 consecutive reference cycles of 6 ns must occur before
range. The phase noise is insensitive to the REFIN duty cycle digital lock detect is set. This refers to fractional-N digital lock
in the lowest noise mode and when the doubler is disabled. detect (set DB8 to 0). With integer–N digital lock detect activated
The maximum allowable REFIN frequency when the doubler (set DB8 to 1), and DB7 set to 0, then five consecutive cycles of
is enabled is 30 MHz. 6 ns need to occur before digital lock detect is set. When DB7 is
set to 1, five consecutive cycles of 10 ns must occur.
RDIV2
Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop Phase Detector Polarity
between the R counter and PFD, which extends the maximum DB6 sets the phase detector polarity. When a passive loop filter,
REFIN input rate. This function allows a 50% duty cycle signal or noninverting active loop filter is used, this should be set to 1.
to appear at the PFD input, which is necessary for cycle slip If an active filter with an inverting characteristic is used, it
reduction. should be set to 0.
10–Bit R Counter Power-Down
The 10–bit R counter allows the input reference frequency DB5 provides the programmable power-down mode. Setting this
(REFIN) to be divided down to produce the reference clock bit to 1 performs a power-down. Setting this bit to 0 returns the
to the PFD. Division ratios from 1 to 1023 are allowed. synthesizer to normal operation. When in software power-down
Double Buffer mode, the part retains all information in its registers. Only if the
DB13 enables or disables double buffering of Bits [DB22:DB20] supply voltages are removed are the register contents lost.
in Register 4. The Divider Select section explains how double When a power-down is activated, the following events occur:
buffering works.
• The synthesizer counters are forced to their load state
Charge Pump Current Setting conditions.
Bits [DB12:DB09] set the charge pump current setting. This • The VCO is powered down.
should be set to the charge pump current that the loop filter • The charge pump is forced into three-state mode.
is designed with (see Figure 26). • The digital lock detect circuitry is reset.
LDF • The RFOUT buffers are disabled.
Setting DB8 to 1 enables integer–N digital lock detect, • The input register remains active and capable of loading
when the FRAC part of the divider is 0; setting DB8 to 0 and latching data.
enables fractional–N digital lock detect. Charge Pump Three-State
DB4 puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
Counter Reset
DB3 is the R counter and N counter reset bit for the ADF4350.
When this is 1, the RF synthesizer N counter and R counter are
held in reset. For normal operation, this bit should be set to 0.

Rev. 0 | Page 19 of 28
ADF4350
REGISTER 3 Band Select Clock Divider Value
Control Bits Bits [DB19:DB12] set a divider for the band select logic
With Bits [C3:C1] set to 0, 1, 1, Register 3 is programmed. clock input. The output of the R counter, is by default, the
Figure 27 shows the input data format for programming this value used to clock the band select logic, but, if this value is
register. too high (>125 kHz), a divider can be switched on to divide
the R counter output to a smaller value (see Figure 28).
CSR Enable
VCO Power-Down
Setting DB18 to 1 enables cycle slip reduction. This is a method
for improving lock times. Note that the signal at the phase fre- DB11 powers the VCO down or up depending on the chosen value.
quency detector (PFD) must have a 50% duty cycle for cycle slip Mute Till Lock Detect
reduction to work. The charge pump current setting must also If DB10 is set to 1, the supply current to the RF output stage is shut
be set to a minimum. See the Cycle Slip Reduction for Faster down until the part achieves lock as measured by the digital lock
Lock Times section for more information. detect circuitry.
Clock Divider Mode AUX Output Select
Bits [DB16:DB15] must be set to 1, 0 to activate PHASE resync DB9 sets the auxiliary RF output. The selection can be either
or 0, 1 to activate fast lock. Setting Bits [DB16:DB15] to 0, 0 the output of the RF dividers or fundamental VCO frequency.
disables the clock divider. See Figure 27.
AUX Output Enable
12-Bit Clock Divider Value
DB8 enables or disables auxiliary RF output, depending on the
The 12-bit clock divider value sets the timeout counter for chosen value.
activation of PHASE resync. See the Phase Resync section for
more information. It also sets the timeout counter for fast lock. AUX Output Power
See the Fast-Lock Timer and Register Sequences section for Bits [DB7:DB6] set the value of the auxiliary RF output power
more information. level (see Figure 28).
REGISTER 4 RF Output Enable
Control Bits DB5 enables or disables primary RF output, depending on the
With Bits [C3:C1] set to 1, 0, 0, Register 4 is programmed. chosen value.
Figure 28 shows the input data format for programming this Output Power
register. Bits [DB4:DB3] set the value of the primary RF output power
Feedback Select level (see Figure 28).
DB23 selects the feedback from the VCO output to the REGISTER 5
N counter. When set to 1, the signal is taken from the VCO Control Bits
directly. When set to 0, it is taken from the output of the output
With Bits [C3:C1] set to 1, 0, 1, Register 5 is programmed.
dividers. The dividers enable covering of the wide frequency band
Figure 29 shows the input data form for programming this
(137.5 MHz to 4.4 GHz). When the divider is enabled and the
register.
feedback signal is taken from the output, the RF output signals
of two separately configured PLLs are in phase. This is useful in Lock Detect Pin Operation
some applications where the positive interference of signals is Bits [DB23:DB22] set the operation of the lock detect pin (see
required to increase the power. Figure 29).
Divider Select
Bits [DB22:DB20] select the value of the output divider (see
Figure 28).

Rev. 0 | Page 20 of 28
 ADF4350
INITIALIZATION SEQUENCE Channel resolution (fRESOUT) or 200 kHz is required at the output
The following sequence of registers is the correct sequence for of the RF divider. Therefore, channel resolution at the output of
initial power-up of the ADF4350 after the correct application of the VCO (fRES) is to be twice the fRESOUT, that is 400 kHz.
voltages to the supply pins: MOD = REFIN/fRES
MOD = 10 MHz/400 kHz = 25
• Register 5
• Register 4 From Equation 4,
• Register 3 fPFD = [10 MHz × (1 + 0)/1] = 10 MHz (5)
• Register 2 2112.6 MHz = 10 MHz × (INT + FRAC/25)/2 (6)
• Register 1
where:
• Register 0
INT = 422
RF SYNTHESIZER—A WORKED EXAMPLE FRAC = 13
The following is an example how to program the ADF4350 MODULUS
synthesizer: The choice of modulus (MOD) depends on the reference signal
RFOUT = [INT + (FRAC/MOD)] × [fPFD]/RF divider (3) (REFIN) available and the channel resolution (fRES) required at
where: the RF output. For example, a GSM system with 13 MHz REFIN
RFOUT is the RF frequency output. sets the modulus to 65. This means the RF output resolution (fRES)
INT is the integer division factor. is the 200 kHz (13 MHz/65) necessary for GSM. With dither off,
FRAC is the fractionality. the fractional spur interval depends on the modulus values chosen
MOD is the modulus. (see Table 6).
RF divider is the output divider that divides down the VCO REFERENCE DOUBLER AND REFERENCE DIVIDER
frequency.
The reference doubler on-chip allows the input reference signal
fPFD = REFIN × [(1 + D)/(R × (1+T))] (4) to be doubled. This is useful for increasing the PFD comparison
where: frequency. Making the PFD frequency higher improves the
REFIN is the reference frequency input. noise performance of the system. Doubling the PFD frequency
D is the RF REFIN doubler bit. usually improves noise performance by 3 dB. It is important to
T is the reference divide-by-2 bit (0 or 1). note that the PFD cannot operate above 32 MHz due to a limi-
R is the RF reference division factor. tation in the speed of the Σ-Δ circuit of the N-divider.

For example, in a UMTS system, where 2112.6 MHz RF The reference divide-by-2 divides the reference signal by 2,
frequency output (RFOUT) is required, a 10 MHz reference resulting in a 50% duty cycle PFD frequency. This is necessary
frequency input (REFIN) is available, and a 200 kHz channel for the correct operation of the cycle slip reduction (CSR)
resolution (fRESOUT) is required on the RF output. Note that function. See the Cycle Slip Reduction for Faster Lock Times
the ADF4350 operates in the frequency range of 2.2 GHz to section for more information.
4.4 GHz. Therefore, the RF divider of 2 should be used (VCO 12-BIT PROGRAMMABLE MODULUS
frequency = 4225.2 MHz, RFOUT = VCO frequency/RF divider =
Unlike most other fractional-N PLLs, the ADF4350 allows the
4225.2 MHz/2 = 2112.6 MHz).
user to program the modulus over a 12–bit range. This means
It is also important where the loop is closed. In this example, the user can set up the part in many different configurations for
the loop is closed (see Figure 30). the application, when combined with the reference doubler and
fPFD the 10-bit R counter.
RFOUT
PFD VCO ÷2
For example, consider an application that requires 1.75 GHz RF
and 200 kHz channel step resolution. The system has a 13 MHz
07325-027

N reference signal.
DIVIDER

Figure 30. Loop Closed Before Output Divider One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. This 26 MHz is then fed
into the PFD programming the modulus to divide by 130. This
also results in 200 kHz resolution and offers superior phase
noise performance over the previous setup.

Rev. 0 | Page 21 of 28
ADF4350
The programmable modulus is also very useful for multi- Up to seven extra charge pump cells can be turned on. In most
standard applications. If a dual-mode phone requires PDC applications, it is enough to eliminate cycle slips altogether,
and GSM 1800 standards, the programmable modulus is a giving much faster lock times.
great benefit. PDC requires 25 kHz channel step resolution, Setting Bit DB18 in the Register 3 to 1 enables cycle slip
whereas GSM 1800 requires 200 kHz channel step resolution. reduction. Note that the PFD requires a 45% to 55% duty cycle
A 13 MHz reference signal can be fed directly to the PFD, and for CSR to operate correctly. If the REFIN frequency does not
the modulus can be programmed to 520 when in PDC mode have a suitable duty cycle, the RDIV2 mode ensures that the
(13 MHz/520 = 25 kHz). input to the PFD has a 50% duty cycle.
The modulus needs to be reprogrammed to 65 for GSM 1800 SPURIOUS OPTIMIZATION AND FAST LOCK
operation (13 MHz/65 = 200 kHz). Narrow loop bandwidths can filter unwanted spurious signals,
It is important that the PFD frequency remain constant (13 MHz). but these usually have a long lock time. A wider loop bandwidth
This allows the user to design one loop filter for both setups will achieve faster lock times, but a wider loop bandwidth may
without running into stability issues. It is important to remem- lead to increased spurious signals inside the loop bandwidth.
ber that the ratio of the RF frequency to the PFD frequency The fast lock feature can achieve the same fast lock time as the
principally affects the loop filter design, not the actual channel wider bandwidth, but with the advantage of a narrow final loop
spacing. bandwidth to keep spurs low.
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES FAST-LOCK TIMER AND REGISTER SEQUENCES
As outlined in the Low Noise and Low Spur Mode section, the If the fast-lock mode is used, a timer value is to be loaded into
ADF4350 contains a number of features that allow optimization the PLL to determine the duration of the wide bandwidth mode.
for noise performance. However, in fast locking applications,
the loop bandwidth generally needs to be wide, and therefore, When Bits [DB16:DB15] in Register 3 are set to 0, 1 (fast-lock
the filter does not provide much attenuation of the spurs. If enable), the timer value is loaded by the 12–bit clock divider
the cycle slip reduction feature is enabled, the narrow loop value. The following sequence must be programmed to use
bandwidth is maintained for spur attenuation but faster lock fast lock:
times are still possible. 1. Initialization sequence (see the Initialization Sequence
Cycle Slips section) occurs only once after powering up the part.
2. Load Register 3 by setting Bits [DB16:DB15] to 0, 1 and
Cycle slips occur in integer-N/fractional-N synthesizers when
the chosen fast-lock timer value [DB14:DB3]. Note that
the loop bandwidth is narrow compared to the PFD frequency.
the duration the PLL remains in wide bandwidth is equal
The phase error at the PFD inputs accumulates too fast for the
to the fast-lock timer/fPFD.
PLL to correct, and the charge pump temporarily pumps in the
wrong direction. This slows down the lock time dramatically. FAST LOCK—AN EXAMPLE
The ADF4350 contains a cycle slip reduction feature that extends If a PLL has reference frequencies of 13 MHz and fPFD = 13 MHz
the linear range of the PFD, allowing faster lock times without and a required lock time of 50 μs, the PLL is set to wide bandwidth
modifications to the loop filter circuitry. for 40 μs. This example assumes a modulus of 65 for channel
When the circuitry detects that a cycle slip is about to occur, spacing of 200 kHz.
it turns on an extra charge pump current cell. This outputs a If the time period set for the wide bandwidth is 40 μs, then
constant current to the loop filter, or removes a constant
current from the loop filter (depending on whether the VCO Fast-Lock Timer Value = Time in Wide Bandwidth × fPFD/MOD
tuning voltage needs to increase or decrease to acquire the new Fast-Lock Timer Value = 40 μs × 13 MHz/65 = 8
frequency). The effect is that the linear range of the PFD is Therefore, a value of 8 must be loaded into the clock divider
increased. Loop stability is maintained because the current value in Register 3 in Step 1 of the sequence described in the
is constant and is not a pulsed current. Fast-Lock Timer and Register Sequences section.
If the phase error increases again to a point where another cycle
slip is likely, the ADF4350 turns on another charge pump cell.
This continues until the ADF4350 detects the VCO frequency
has gone past the desired frequency. The extra charge pump
cells are turned off one by one until all the extra charge pump
cells have been disabled and the frequency is settled with the
original loop filter bandwidth.

Rev. 0 | Page 22 of 28
 ADF4350
FAST LOCK—LOOP FILTER TOPOLOGY In low noise mode (dither disabled) the quantization noise from
To use fast-lock mode, the damping resistor in the loop filter the Σ-Δ modulator appears as fractional spurs. The interval
is reduced to ¼ of its value while in wide bandwidth mode. To between spurs is fPFD/L, where L is the repeat length of the code
achieve the wider loop filter bandwidth, the charge pump sequence in the digital Σ-Δ modulator. For the third-order
current increases by a factor of 16 and to maintain loop sta- modulator used in the ADF4350, the repeat length depends on
bility the damping resistor must be reduced a factor of ¼. the value of MOD, as listed in Table 6.
To enable fast lock, the SW pin is shorted to the GND pin by Table 6. Fractional Spurs with Dither Disabled
settings Bits [DB16:DB15] in Register 3 to 0, 1. The following Repeat
two topologies are available: Condition (Dither Disabled) Length Spur Interval
• The damping resistor (R1) is divided into two values (R1 If MOD is divisible by 2, but not 3 2 × MOD Channel step/2
and R1A) that have a ratio of 1:3 (see Figure 31). If MOD is divisible by 3, but not 2 3 × MOD Channel step/3
If MOD is divisible by 6 6 × MOD Channel step/6
• An extra resistor (R1A) is connected directly from SW, as
Otherwise MOD Channel step
shown in Figure 32. The extra resistor is calculated such
that the parallel combination of an extra resistor and the In low spur mode (dither enabled), the repeat length is extend-
damping resistor (R1) is reduced to ¼ of the original value ed to 221 cycles, regardless of the value of MOD, which makes
of R1 (see Figure 32). the quantization error spectrum look like broadband noise.
ADF4350 This may degrade the in-band phase noise at the PLL output
R2
CP VCO by as much as 10 dB. For lowest noise, dither disabled is a better
C1 C2 C3 choice, particularly when the final loop bandwidth is low
R1 enough to attenuate even the lowest frequency fractional spur.
SW Integer Boundary Spurs
R1A Another mechanism for fractional spur creation is the inter-
07325-018

actions between the RF VCO frequency and the reference

frequency. When these frequencies are not integer related (the
Figure 31. Fast-Lock Loop Filter Topology—Topology 1
point of a fractional-N synthesizer) spur sidebands appear on
the VCO output spectrum at an offset frequency that corres-
ADF4350 ponds to the beat note or difference frequency between an
R2
CP VCO integer multiple of the reference and the VCO frequency. These
C1 C2 C3 spurs are attenuated by the loop filter and are more noticeable
on channels close to integer multiples of the reference where the
R1A R1
difference frequency can be inside the loop bandwidth, there-
fore, the name integer boundary spurs.
SW
Reference Spurs
07325-019

Reference spurs are generally not a problem in fractional-N

Figure 32. Fast-Lock Loop Filter Topology—Topology 2 synthesizers because the reference offset is far outside the loop
SPUR MECHANISMS bandwidth. However, any reference feed-through mechanism
that bypasses the loop may cause a problem. Feed through of
This section describes the three different spur mechanisms that
low levels of on-chip reference switching noise, through the
arise with a fractional-N synthesizer and how to minimize them
RFIN pin back to the VCO, can result in reference spur levels as
in the ADF4350.
high as –90 dBc. PCB layout needs to ensure adequate isolation
Fractional Spurs between VCO traces and the input reference to avoid a possible
The fractional interpolator in the ADF4350 is a third-order feed through path on the board.
Σ-Δ modulator (SDM) with a modulus (MOD) that is program-
mable to any integer value from 2 to 4095. In low spur mode
(dither enabled) the minimum allowable value of MOD is 50.
The SDM is clocked at the PFD reference rate (fPFD) that allows
PLL output frequencies to be synthesized at a channel step
resolution of fPFD/MOD.

Rev. 0 | Page 23 of 28
ADF4350
SPUR CONSISTENCY AND FRACTIONAL SPUR When a new frequency is programmed, the second sync pulse
OPTIMIZATION after the LE rising edge is used to resynchronize the output
phase to the reference. The tSYNC time is to be programmed to
With dither off, the fractional spur pattern due to the quantiza-
a value that is as least as long as the worst-case lock time. This
tion noise of the SDM also depends on the particular phase
guarantees the phase resync occurs after the last cycle slip in the
word with which the modulator is seeded.
PLL settling transient.
The phase word can be varied to optimize the fractional and
In the example shown in Figure 33, the PFD reference is 25 MHz
subfractional spur levels on any particular frequency. Thus, a
and MOD = 125 for a 200 kHz channel spacing. tSYNC is set to
look-up table of phase values corresponding to each frequency
400 μs by programming CLK_DIV_VALUE = 80.
can be constructed for use when programming the ADF4350.
If a look-up table is not used, keep the phase word at a constant LE
tSYNC
value to ensure consistent spur levels on any particular frequency.
SYNC
PHASE RESYNC (INTERNAL) LAST CYCLE SLIP

The output of a fractional-N PLL can settle to any one of the

MOD phase offsets with respect to the input reference, where FREQUENCY

MOD is the fractional modulus. The phase resync feature in the PLL SETTLES TO
INCORRECT PHASE
ADF4350 produces a consistent output phase offset with respect
PLL SETTLES TO
to the input reference. This is necessary in applications where the CORRECT PHASE
AFTER RESYNC
output phase and frequency are important, such as digital beam PHASE

forming. See the Phase Programmability section to program a

07325-020
specific RF output phase when using phase resync.
–100 0 100 200 300 400 500 600 700 800 900 1000
Phase resync is enabled by setting Bits [DB16:DB15] in TIME (µs)
Register 3 to 1, 0. When phase resync is enabled, an internal Figure 33. Phase Resync Example
timer generates sync signals at intervals of tSYNC given by the
Phase Programmability
following formula:
The phase word in Register 1 controls the RF output phase. As
tSYNC = CLK_DIV_VALUE × MOD × tPFD
this word is swept from 0 to MOD, the RF output phase sweeps
where: over a 360° range in steps of 360°/MOD.
tPFD is the PFD reference period.
CLK_DIV_VALUE is the decimal value programmed in
Bits [DB14:DB3] of Register 3 and can be any integer in the
range of 1 to 4095.
MOD is the modulus value programmed in Bits [DB14:DB3] of
Register 1 (R1).

Rev. 0 | Page 24 of 28
 ADF4350

APPLICATIONS INFORMATION
DIRECT CONVERSION MODULATOR The LO ports of the ADL5375 can be driven differentially from
Direct conversion architectures are increasingly being used to the complementary RFOUTA and RFOUTB outputs of the ADF4350.
implement base station transmitters. Figure 34 shows how Analog This gives better performance than a single-ended LO driver
Devices, Inc., parts can be used to implement such a system. and eliminates the use of a balun to convert from a single-ended
LO input to the more desirable differential LO input for the
The circuit block diagram shows the AD9761 TxDAC® being ADL5375. The typical rms phase noise (100 Hz to 5 MHz)
used with the ADL5375. The use of dual integrated DACs, such of the LO in this configuration is 0.61°rms.
as the AD9788 with its specified ±0.02 dB and ±0.001 dB gain
and offset matching characteristics, ensures minimum error The AD8349 accepts LO drive levels from −10 dBm to 0 dBm.
contribution (over temperature) from this portion of the The optimum LO power can be software programmed on the
signal chain. ADF4350, which allows levels from −4 dBm to +5 dBm from
each output.
The local oscillator (LO) is implemented using the ADF4350.
The low-pass filter was designed using ADIsimPLL™ for a channel The RF output is designed to drive a 50 Ω load, but must be
spacing of 200 kHz and a closed-loop bandwidth of 35 kHz. ac-coupled, as shown in Figure 34. If the I and Q inputs are
driven in quadrature by 2 V p-p signals, the resulting output
power from the modulator is approximately 2 dBm.

51Ω 51Ω
REFIO
IOUTA
LOW-PASS
IOUTB FILTER
MODULATED
AD9761
DIGITAL TxDAC
DATA
QOUTA
LOW-PASS
FILTER
QOUTB
FSADJ 51Ω 51Ω

2kΩ

LOCK
VVCO VDD DETECT

16 17 28 10 4 26 6 32 30 25
VVCO DVDD AVDD CE PDB RF VP SDVDD MUXOUT LD
1nF 1nF IBBP ADL5375
FREF IN 29 REF IN RFOUTB+ 14
VVCO
51Ω IBBN
1 CLK RFOUTB– 15
2 DATA 3.9nH 3.9nH
3 LE 1nF
QBBP
SPI-COMPATIBLE SERIAL BUS

ADF4350 RFOUTA+ 12 QUADRATURE RFO

PHASE
22 RSET QBBN SPLITTER
RFOUTA– 13
4.7kΩ 1nF

VTUNE 20 DSOP
680Ω
CPOUT 7 LOIP

39nF LOIN
2700pF 1200pF
SW 5
360Ω
CPGND SDGND AGND AGNDVCO DGND TEMP VCOM VREF
8 31 9 11 18 21 27 19 23 24

10pF 0.1µF 10pF 0.1µF 10pF 0.1µF

07325-021

Figure 34. Direct Conversion Modulator

Rev. 0 | Page 25 of 28
ADF4350
INTERFACING ADSP-21xx Interface
The ADF4350 has a simple SPI-compatible serial interface for Figure 36 shows the interface between the ADF4350 and the
writing to the device. CLK, DATA, and LE control the data ADSP-21xx digital signal processor. The ADF4350 needs a
transfer. When LE goes high, the 32 bits that have been clocked 32-bit serial word for each latch write. The easiest way to
into the appropriate register on each rising edge of CLK are accomplish this using the ADSP-21xx family is to use the
transferred to the appropriate latch. See Figure 2 for the timing autobuffered transmit mode of operation with alternate
diagram and Table 5 for the register address table. framing. This provides a means for transmitting an entire
block of serial data before an interrupt is generated.
ADuC812 Interface
Figure 35 shows the interface between the ADF4350 and the
SCLK CLK
ADuC812 MicroConverter®. Because the ADuC812 is based on
MOSI SDATA
an 8051 core, this interface can be used with any 8051-based
TFS LE ADF4350
microcontroller. The MicroConverter is set up for SPI master ADSP-21xx
CE
mode with CPHA = 0. To initiate the operation, the I/O port I/O PORTS
MUXOUT
driving LE is brought low. Each latch of the ADF4350 needs a (LOCK DETECT)

07325-023
32-bit word, which is accomplished by writing four 8-bit bytes
from the MicroConverter to the device. When the fourth byte
Figure 36. ADSP-21xx to ADF4350 Interface
has been written, the LE input should be brought high to
complete the transfer. Set up the word length for 8 bits and use four memory locations
for each 32-bit word. To program each 32-bit latch, store the 8-bit
bytes, enable the autobuffered mode, and write to the transmit
SCLOCK CLK
register of the DSP. This last operation initiates the autobuffer
MOSI SDATA
transfer.
ADuC812 LE ADF4350
I/O PORTS CE PCB DESIGN GUIDELINES FOR A CHIP SCALE
MUXOUT PACKAGE
(LOCK DETECT)
07325-022

The lands on the chip scale package (CP-32-2) are rectangular.

The PCB pad for these is to be 0.1 mm longer than the package
Figure 35. ADuC812 to ADF4350 Interface land length and 0.05 mm wider than the package land width.
I/O port lines on the ADuC812 are also used to control power- The land is to be centered on the pad. This ensures the solder
down input (CE) and lock detect (MUXOUT configured as lock joint size is maximized. The bottom of the chip scale package
detect and polled by the port input). When operating in the has a central thermal pad.
described mode, the maximum SCLOCK rate of the ADuC812 The thermal pad on the PCB is to be at least as large as the
is 4 MHz. This means that the maximum rate at which the exposed pad. On the PCB, there is to be a minimum clearance
output frequency can be changed is 125 kHz. of 0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, they
are to be incorporated in the thermal pad at 1.2 mm pitch grid.
The via diameter is to be between 0.3 mm and 0.33 mm, and the
via barrel is to be plated with 1 oz. of copper to plug the via.

Rev. 0 | Page 26 of 28
 ADF4350
OUTPUT MATCHING VVCO

There are a number of ways to match the output of the ADF4350

for optimum operation; the most basic is to use a 50 Ω resistor to 3.9nH
VVCO. A dc bypass capacitor of 100 pF is connected in series as
1nF
shown in Figure 37. Because the resistor is not frequency
RFOUT
dependent, this provides a good broadband match. Placing

07325-025
50Ω
the output power in this circuit into a 50 Ω load typically
gives values chosen by Bit D2 and Bit D1 in Register 4 (R4).
Figure 38.Optimum ADF4350 Output Stage
VVCO
If differential outputs are not needed, the unused output can be
50Ω terminated or combined with both outputs using a balun.
100pF VVCO
RFOUT 07325-021

50Ω L2 L1

RFOUTA+
Figure 37. Simple ADF4350 Output Stage C1 C2

A better solution is to use a shunt inductor (acting as an RF 50Ω

L1
choke) to VVCO. This gives a better match and, therefore, more RFOUTA–

07325-132
output power. C1

Experiments have shown the circuit shown in Figure 38

Figure 39. ADF4350 LC Balun
provides an excellent match to 50 Ω for the W-CDMA UMTS
Band 1 (2110 MHz to 2170 MHz). The maximum output power A balun using discrete inductors and capacitors may be
in that case is about 5 dBm. Both single-ended architectures can implemented with the architecture in Figure 39.
be examined using the EVAL-ADF4350EB1Z evaluation board. Component L1 and Component C1 comprise the LC balun, L2
provides a dc path for RFOUTA−, and Capacitor C2 is used for dc
blocking.

Table 7. LC Balun Components

Frequency RF Choke DC Blocking Measured Output
Range (MHz) Inductor L1 (nH) Capacitor C1 (pF) Inductor (nH) Capacitor (pF) Power (dBm)
137 to 300 100 10 390 1000 9
300 to 460 51 5.6 180 120 10
400 to 600 30 5.6 120 120 10
600 to 900 18 4 68 120 10
860 to 1240 12 2.2 39 10 9
1200 to 1600 5.6 1.2 15 10 9
1600 to 3600 3.3 0.7 10 10 8
2800 to 3800 2.2 0.5 10 10 8

Rev. 0 | Page 27 of 28
ADF4350

OUTLINE DIMENSIONS
5.00 0.60 MAX
BSC SQ 0.60 MAX PIN 1
INDICATOR
25 32
24 1
PIN 1
INDICATOR 0.50
TOP 4.75 BSC EXPOSED 3.25
VIEW BSC SQ PAD 3.10 SQ
(BOTTOM VIEW) 2.95
0.50
0.40 17 8
16 9
0.30
0.25 MIN
0.80 MAX 3.50 REF
12° MAX 0.65 TYP

0.05 MAX FOR PROPER CONNECTION OF

1.00 0.02 NOM THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
0.85 0.30 FUNCTION DESCRIPTIONS
COPLANARITY
0.80 0.23 0.20 REF SECTION OF THIS DATA SHEET.
SEATING 0.08
PLANE 0.18

011708-A
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADF4350BCPZ 1 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2
ADF4350BCPZ-RL1 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2
ADF4350BCPZ-RL71 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2
EVAL-ADF4350EB1Z1 Evaluation Board
1
Z = RoHS Compliant Part.

©2008 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D07325-0-11/08(0)

Rev. 0 | Page 28 of 28