DESIGN OF 14-BIT MULTI-CHANNEL FULLY

DIFFERENTIAL SAR ADC FOR LOW

FREQUENCY APPLICATIONS IN SCL 180nm
TECHNOLOGY
SUBMITTED IN THE REQUIREMENT OF PARTIAL FULFILMENT
FOR
THE DEGREE OF MASTER OF TECHNOLOGY
IN
VLSI DESIGN
BY
SABARNO CHOWDHURY
ROLL NO. – 325417003

UNDER THE GUIDANCE OF

PROF. HAFIZUR RAHAMAN & SUBHAJIT DAS
SCHOOL OF VLSI TECHNOLOGY,
INDIAN INSTITUTE OF ENGINEERING, SCIENCE AND
TECHNOLOGY,
SHIBPUR, HOWRAH-711103
 SCHOOL OF VLSI TECHNOLOGY,
INDIAN INSTITUTE OF ENGINEERING, SCIENCE
AND TECHNOLOGY,
SHIBPUR, HOWRAH-711103

CERTIFICATE
This is to certify that the project entitled “Design of 14-bit Multi-Channel Fully Differential
SAR ADC for low frequency applications in SCL 180nm Technology” which is being
submitted by Sabarno Chowdhury (Roll No. – 325417003 of 2017-18) in partial fulfilment of the
criterion for the Master of Technology coursework, has been carried out by him under my
supervision and guidance.

Prof. Hafizur Rahaman Subhajit Das

Supervisor Supervisor
Head of Department, School of VLSI Technology,
Information Technology, IIEST, Shibpur
IIEST, Shibpur

Prof. Jaya Sil Prof. Susanta Chakraborty

Head of Department, Dean (Academic Affairs),
School of VLSI Technology, IIEST, Shibpur
IIEST, Shibpur

External Examiners
 ACKNOWLEDGEMENT

I would like to take this opportunity to express my heartiest gratitude and deepest regards to my
project guides Prof. Hafizur Rahaman and Subhajit Das for their valuable guidance, constant
support and inspiration throughout the course of the project. It has been a worthwhile experience
being mentored by him.
I am highly obliged to my Head of Department, Prof. Jaya Sil for creating such a wonderful
environment to work and successfully progress with the project and also allowing us to use the
university equipment as and when required.
I am very grateful to our seniors and research scholars for showering their invaluable knowledge
on me and providing me with significant suggestions for my project work whenever deemed
necessary.
Lastly and most importantly, I would like to thank my parents for their immense contribution in
my life and also for their constant encouragement for the completion of this report.
Regards,
DATE:
PLACE: IIEST, Shibpur Sabarno Chowdhury
Roll No. – 325417003
School of VLSI Technology,
IIEST, Shibpur
 CONTENTS

List of Figures
List of Tables
Abstract 1
Chapter 1 2
Introduction 2
Chapter 2 5
2.1 Motivation 5
2.2 Organization of Thesis 6
Chapter 3 7
3.1 What is an ADC? 7
3.2 Working Principle of ADC 8
3.3 Parameters of ADC 9
3.4 Errors associated with ADC 12
Chapter 4 16
4.1 ADC Architectures 16
4.1.1 Flash ADC 16
4.1.2 Successive Approximation Register (SAR) ADC 18
4.1.1 Sigma Delta ADC 20
4.2 Justification of choice of ADC 21
4.3 Types of SAR ADC 22
4.4 Specifications of ADC 25
Chapter 5 26
5.1 Fully Differential SAR ADC 26
5.2 Advantages of Differential-ended ADC over Single-ended ADC 26
5.3 Multi-Channel Fully Differential SAR ADC 27
5.4 Architecture of Multi-Channel Driver Buffer 31
5.5 Architecture of Sample and Hold Array 32
5.6 Architecture of SAR Logic (Synchronous Shift Register) 37
5.7 Architecture of ADC 41
5.7.1 Architecture of Split Capacitive DAC and its Switches 42
5.7.2 Architecture of Calibration DAC (CDAC) 45
5.7.3 Architecture of Comparator with Calibration 51
5.7.4 Architecture of DAC Control Logic 56
5.7.5 Architecture of Delay Buffer 61
5.8 Architecture of Clock Network 62
5.9 Architecture of Register Control 67
5.10 Architecture of 14-bit Demultiplexer 70
 5.11 Architecture of 14-bit Multiplexer 73
5.12 Architecture of 14-bit Output Register 77
Chapter 6 80
6.1 Validation of Multi-Channel Fully Differential SAR ADC 80
6.2 Mathematical Relationships between SINAD, SNR and THD 84
6.3 Results 85
Chapter 7 89
7.1 Conclusion 89
7.2 Future Work 89
References 90
 LIST OF FIGURES

Fig. 1.1 Different types of frequencies 2

Fig. 1.2 Low frequency antenna for military applications 3
Fig. 1.3 Internal circuitry of a Seismic Sensor 3
Fig. 3.1 ADC Symbol 7
Fig. 3.2 Analog to digital conversion process 7
Fig. 3.3 Sample and Hold Circuit 8
Fig. 3.4 Stages of analog to digital conversion 9
Fig. 3.5 Offset Error 12
Fig. 3.6 Gain Errors 13
Fig. 3.7 Full Scale Error 13
Fig. 3.8 Differential Non-Linearity (DNL) 14
Fig. 3.9 Integral Non-Linearity (INL) 14
Fig. 3.10 Missing Codes 15
Fig. 4.1 Architecture of a 3-bit Flash ADC 16
Fig. 4.2 Architecture of a 3-bit Flash ADC with XOR gates 17
Fig. 4.3 Analog input and Digital output of a Flash ADC 18
Fig. 4.4 SAR ADC Architecture 19
Fig. 4.5 Operation of a 4-bit SAR ADC 19
Fig. 4.6 Sigma-Delta ADC Architecture 21
Fig. 4.7 ADC architectures, applications, resolution and sampling rates 22
Fig. 4.8 (a) Single-Ended Unipolar (b) Single-Ended True Bipolar 23
Fig. 4.9 (a) Pseudo-Differential Unipolar (b) Pseudo-Differential Bipolar (c) Pseudo – Differential
True Bipolar 24
Fig. 4.10 (a) Fully Differential (b) Fully Differential True Bipolar 24
Fig. 5.1 Block diagram of Multi-Channel Fully Differential SAR ADC 28
Fig. 5.2 Operation of Multi-Channel Fully Differential SAR ADC 29
Fig. 5.3 Internal architecture of Fully Differential SAR ADC 29
Fig. 5.4 Timing diagram of Fully Differential SAR ADC 30
Fig. 5.5 Block Diagram of Multi-Channel Driver Buffer 32
Fig. 5.6 NMOS switch for Sample and Hold 32
Fig. 5.7 Track and Hold Concept 33
Fig. 5.8 Circuit diagram of Track and Hold arrangement 34
Fig. 5.9 Schematic of Non-Overlapping Clock 35
Fig. 5.10 Waveform of pre-layout simulation of Sample and Hold Circuit 35
Fig. 5.11 Layout of Sample and Hold Circuit 36
Fig. 5.12 Waveform of post-layout simulation of Sample and Hold Circuit 36
Fig. 5.13 Comparison of pre-layout and post-layout simulation of Sample and Hold Circuit 37
Fig. 5.14 Schematic of a TG based DFF 38
Fig. 5.15 Layout of TG based DFF 38
Fig. 5.16 Waveform of pre-layout simulation of TG based DFF 39
Fig. 5.17 14-bit Shift Register using TG based DFF 39
Fig. 5.18 Schematic of 14-bit Shift Register using TG based DFF 39
Fig. 5.19 Waveform of pre-layout simulation of 14-bit Shift Register using TG based DFF 40
Fig. 5.20 Layout of 14-bit Shift Register using TG based DFF 40
Fig. 5.21 Waveform of post- layout simulation of 14 -bit Shift Register using TG based
DFF 41
Fig. 5.22 Comparison of pre-layout and post-layout simulations of 14 -bit Shift Register
using TG based DFF 41
Fig. 5.23 Split Capacitive DAC implementation with Timing Diagram 42
Fig. 5.24 Schematic of Split Capacitive DAC 43
Fig. 5.25 Layout of Split Capacitive DAC 43
Fig. 5.26 Schematic of DAC Switch 44
Fig. 5.27 Layout of DAC Switch 44
Fig. 5.28 Schematic of DAC Switch Array 45
Fig. 5.29 Layout of DAC Switch Array 45
Fig. 5.30 Schematic of Calibration DAC with switches 46
Fig. 5.31 Schematic of p-side CDAC 47
Fig. 5.32 Schematic of n-side CDAC 47
Fig. 5.33 Layout of p-side CDAC with switches and dummies 48
Fig. 5.34 Layout of n-side CDAC with switches and dummies 48
Fig. 5.35 Schematic of CDAC Control Logic 49
Fig. 5.36 Layout of CDAC Control Logic 49
Fig. 5.37 Waveform of simulation of CDAC Control Logic 49
Fig. 5.38 Schematic of Calibration Control 50
Fig. 5.39 Layout of Calibration Control 50
Fig. 5.40 Waveform of simulation of one side of CDAC with Calibration Control 50
Fig. 5.41 Schematic of Double Tail Dynamic Comparator 51
Fig. 5.42 Layout of Double Tail Dynamic Comparator 52
Fig. 5.43 Schematic of Comparator Control Circuit 53
Fig. 5.44 Layout of Comparator Control Circuit 53
Fig. 5.45 Schematic of Comparator Calibration Circuit 54
Fig. 5.46 Layout of Comparator Calibration Circuit 54
Fig. 5.47 Schematic of Comparator Calibration Control Circuit 55
Fig. 5.48 Layout of Comparator Calibration Control Circuit 55
Fig. 5.49 Schematic of Comparator with Calibration 55
Fig. 5.50 Layout of Comparator with Calibration 56
Fig. 5.51 Waveform of Comparator with Calibration 56
Fig. 5.52 Circuit diagram of 1-bit DAC Control 57
Fig. 5.53 Timing diagram of 1-bit DAC Control 57
Fig. 5.54 Circuit diagram of DAC Control with Switch to control Capacitor 58
Fig. 5.55 Circuit diagram of DAC Control with SAR Logic 58
Fig. 5.56 Schematic of 1-bit DAC Control 59
Fig. 5.57 Layout of 1-bit DAC Control 59
Fig. 5.58 Schematic of 14-bit DAC Control 59
Fig. 5.59 Layout of 14-bit DAC Control 60
Fig. 5.60 Waveform of pre-layout s i m u l a t i o n of 14-bit DAC Control 60
Fig. 5.61 Waveform of post-layout s i m u l a t i o n of 14-bit DAC Control 60
Fig. 5.62 Comparison of pre-layout and post-layout simulations of 14-bit DAC Control 61
Fig. 5.63 Schematic of Delay Buffer 61
Fig. 5.64 Layout of Delay Buffer 62
Fig. 5.65 Block diagram of the clock network 63
Fig. 5.66 Schematic of Counter reset to ‗48‘ 63
Fig. 5.67 Layout of Counter reset to ‗48‘ 63
Fig. 5.68 Waveform of pre-layout simulation of Counter reset to ‗48‘ 64
Fig. 5.69 Schematic of 6:64 Decoder 64
Fig. 5.70 Layout of 6:64 Decoder 64
Fig. 5.71 Waveform of pre-layout simulation of 6:64 Decoder 65
Fig. 5.72 Schematic of Crossbar architecture using NMOS 65
Fig. 5.73 Layout of Crossbar architecture using NMOS 65
Fig. 5.74 Layout of Clock Control Unit developed using SPC 66
Fig. 5.75 Waveform of pre-layout simulation of Clock Control Unit developed using
SPC 66
Fig. 5.76 Waveform of post-layout simulation of Clock Control Unit developed using
SPC 66
Fig. 5.77 Comparison of pre-layout and post-layout simulations of Clock Control Unit
developed using SPC 67
Fig. 5.78 Schematic of Register Control 67
Fig. 5.79 Layout of Register Control 68
Fig. 5.80 Waveform of pre-layout simulation of Register Control 69
Fig. 5.81 Waveform of post-layout simulation of Register Control 69
Fig. 5.82 Comparison of pre-layout and post-layout simulations of Register Control 69
Fig. 5.83 Schematic of 1-bit Demultiplexer 70
Fig. 5.84 Schematic of 14-bit Demultiplexer 70
Fig. 5.85 Layout of 1-bit Demultiplexer 71
Fig. 5.86 Waveform of pre-layout simulation of 1-bit Demultiplexer 71
Fig. 5.87 Layout of 14-bit Demultiplexer 72
Fig. 5.88 Waveform of post-layout simulation of 1-bit Demultiplexer 73
Fig. 5.89 Comparison of pre-layout and post-layout simulations of 1-bit Demultiplexer 73
Fig. 5.90 Schematic of 1-bit Multiplexer 74
Fig. 5.91 Schematic of 14-bit Multiplexer 74
Fig. 5.92 Layout of 1-bit Multiplexer 75
Fig. 5.93 Layout of 14-bit Multiplexer 75
Fig. 5.94 Waveform of pre-layout of 1-bit Multiplexer 75
Fig. 5.95 Waveform of post-layout of 1-bit Multiplexer 76
Fig. 5.96 Comparison of pre-layout and post-layout simulations of 1-bit Multiplexer 76
Fig. 5.97 Schematic of 14-bit Output Register 77
Fig. 5.98 Waveform of pre-layout simulation of 14-bit Output Register 77
Fig. 5.99 Layout of 14-bit Output Register 78
Fig. 5.100 Waveform of post-layout simulation of 14-bit Output Register 79
Fig. 5.101 Comparison of pre-layout and post-layout simulations of 14-bit Output Register 79
Fig. 6.1 Complete layout of the 14-bit Multi Channel Fully Differential SAR ADC 80
Fig. 6.2 Output waveform of 14-bit ADC with Vip=0.825 mV and Vin=0.975 mV 81
Fig. 6.3 Output waveform of 14-bit ADC with Vip=0. 900062V and Vin=0. 899938V 81
Fig. 6.4 Reconstructed analog signal after an ideal DAC for input frequency 500Hz and sampling
frequency 31.3 KHz 82
Fig. 6.5 FFT of a reconstructed signal of ADC 83
Fig. 6.6 FFT diagram of ADC with input frequency 50Hz and sampling frequency
25KSPS 86
Fig. 6.7 FFT diagram of ADC with input frequency 100Hz and sampling frequency
25KSPS 86
Fig. 6.8 Comparison of performance parameter with Sampling Frequency 87
Fig. 6.9 Comparison of performance parameter with Input Frequency 87
 LIST OF TABLES

Table 4.1 Specifications of the required 14-bit Multi Channel Fully Differential SAR ADC 25
Table 5.1 SAR Logic Implementation 40
Table 6.1 Comparison of performance parameters with the 100Hz as Input frequency with
25KSPS Sampling Rate 88
Table 6.2 Comparison of specifications for the 14-bit ADC 88
 ABSTRACT

The following thesis presents the design of a 14-bit Multi Channel Fully Differential SAR
(Successive Approximation Register) ADC (Analog to Digital Converter). The ADC has been
designed suitable for the use of low frequency applications, such as in seismic sensors, in
biomedical electronics and so on. The reason for the choice of SAR ADC has been duly justified
after researching the various architectures of ADC. All the individual components of this ADC
have been carefully designed and tested in both schematic and layout views in Cadence
Virtuoso® under SCL 180nm technology. The relevant schematics, layouts and simulation results
of the individual blocks have been included here. After completion of all the components, they
have been integrated to form the desired ADC. Integration was followed by measurement of
ADC parameters, such as, ENOB, SINAD, SFDR and SNDR.

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CHAPTER 1

Introduction

Low frequency (LF) is the radio frequency (RF) in the range of 30–300 kilohertz (kHz)
and having a wavelength of 1-10 km. Due to its wavelength range, it is also known as
the kilometer band or kilometer wave.
LF radio waves exhibit low signal attenuation and high signal penetration, thus suffering
less from scattering. This makes them suitable for long-distance communications. Low
frequency radio waves can diffract over obstacles like mountain ranges due to their
long wavelength and travel beyond the horizon following the contour of the Earth. This mode of
propagation, called ground wave, is the main mode in the LF band. Low frequency ground waves
can be received up to 2,000 km from the transmitting antenna. Low frequency waves can also
occasionally travel long distances by reflecting from the ionosphere.

Fig. 1.1 Different types of frequencies

The above features of LF waves make them suitable for the following applications:
 Military applications - Low frequency signals (below 50 kHz) are capable of
penetrating ocean depths to approximately 200 meters. The longer the wavelength, the
deeper the penetration. This property of low frequency waves finds application in
submarines.

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 Fig. 1.2 Low frequency antenna for military applications

 Seismic applications - Due to high signal penetration and low signal attenuation, low
frequency waves can travel through various layers of the earth. This enables seismic
sensors (which use low frequency waves) to detect tremors under the earth‘s surface with
good precision and accuracy.

Fig. 1.3 Internal circuitry of a Seismic Sensor

 Standard time signals - Many low-cost consumer devices contain radio clocks with an
LF receiver. Since these frequencies propagate by ground wave only, the precision of
time signals is not affected by varying propagation paths between the transmitter, the
ionosphere and the receiver.

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  Biomedical applications - Biomedical electronics involve active filters with very low
cutoff frequencies due to the relatively slow electrical activity of the human body. This
requires low frequency signal processing.
 Miscellaneous applications – Low frequency waves find applications in detecting holes
in underground pipes and also in mining activities for communication and investigation
of various materials.
The aforementioned applications of low frequency waves require proper processing of low
frequency signals and their conversion from analog to digital domain. Here comes the use of
analog to digital converters, abbreviated as ADCs. The following thesis contains the design of a
14-bit ADC, tailor-made for low frequency applications.

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CHAPTER 2

2.1 Motivation

The world around us is full of only analog signals, that is, signals that are continuous
over time and have infinite values at any instant of time. The output of a microphone, the voltage
at a photodiode or the signal of an accelerometer are all examples of analog signals that need to
be converted so that they can be processed and/or stored. Both processing and storing of analog
signals are troublesome. So, analog signals are converted into digital signals, that is, signals that
are discrete over time and have definite values at any instant of time. This is where analog to
digital converters (ADCs) come into the picture.
The use of ADCs for low frequency applications is very significant. They are an integral
part of the military and seismic sensors. The military use them to locate enemies and/or
obstacles, especially in submarines. This becomes very useful during critical situations. Seismic
sensors are detrimental in predicting earthquakes. They can potentially locate the origin of the
tremors under the earth‘s surface (epicentre). This helps in taking preventive measures and
minimize casualties. The use of LF in the health sector is also crucial. The human body produces
very slow electrical signals, requiring low frequency signal processing. LF is vital detecting
signals generated by various parts of the body, especially nerves. The information collected by
LF signals can be used to detect life threatening diseases or check the condition of vital organs of
the human body. Apart from these, LF finds applications in mining too. LF is highly effective in
communication among mine workers due to its high penetrating property. This can be a potential
life-saver disasters occur inside mines. Moreover, with the help of LF waves, holes and leakages
can be detected in underground pipelines.
Hence, it is clear that LF plays a key role in several sectors and somehow or the other
affects our day to day lives, be it directly or indirectly. This is enough motivation to design an
ADC suited for LF applications such as the aforementioned and have it integrated on a silicon
chip for use in various sectors. The choice and design of ADC from scratch has been discussed
hereafter.

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2.2 Organization of Thesis

The remaining thesis has been arranged as follows:

Chapter 3 describes the working principle of an ADC. This chapter also discusses the various
parameters that define an ADC and the errors associated with the same.
Chapter 4 discusses in details the various architectures of ADC that are available. The
justification for the best suitable choice of ADC as per the requirement is concluded inthis
chapter after thorough research.
Chapter 5 includes the description of all the individual components that have been designed for
constructing the required ADC. The operation of all the components is discussed in this chapter.
It also contains the circuits in schematic and layout formats, accompanied by their corresponding
simulation waveforms.
Chapter 6 involves test results of the complete ADC. It also includes the measurement of a few
performance parameters with respect to a certain input frequency and sampling frequency.
Chapter 7 concludes the whole work that has been performed. This chapter also includes the
future work to be undertaken.

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CHAPTER 3

3.1 What is an ADC?

Since the computers are the heart of all data processing, the analog signals must be

converted to numbers. The process of converting a continuous analog signal (usually a voltage)
to a series of numbers representing the signal at discrete intervals (digital signal) is called
analog to digital conversion and is performed by an electronic component known as analog to
digital converters (ADC). The ADCs are at the front-end of any digital circuit that needs to
process signals coming from the exterior world.

Fig. 3.1 ADC Symbol

Figure 3.2 shows a signal, where the amplitude is measured at regular intervals Δt. In its
simplest form, it can be simply envisaged a s measuring the amplitude of a slowly changing
signal with an analog voltmeter and writing down the numbers.

Fig. 3.2 Analog to digital conversion process. The arrows show the location and values (amplitudes) of the samples

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3.2 Working Principle of ADC

Almost all ADCs operate on the same principle. The conversion of analog signals to digital
signals is a 2-step process, which is as follows:
 Sample and Hold - An analog signal continuously changes with time. In order to
measure the signal, it needs to be kept steady for a short duration so that it can be
sampled. To obtain this, the analog signal is held for a specific duration and then the
value is sampled. This is done by a sample and hold circuit.
The sample and hold circuit is simply a switch driving a hold capacitor followed
by a high input impedance buffer. The input impedance of the buffer must be high
enough so that the capacitor is discharged by less than 1 LSB during the hold time. The
circuit samples the signal in the sample mode, and holds the signal constant during the
hold mode. Sampling is done at nyquist frequency, which is twice the frequency value of
the analog signal being sampled.

Fig. 3.3 Sample and Hold Circuit

 Quantization and Encoding - The output of the sample and hold circuit gives a certain
voltage level, to which a numerical value has to be assigned. The nearest value, in
correspondence with the amplitude of sampling and holding signal, is searched. This
value depends on the range of the quantizer and the range in given in a power of 2. After
identifying the closest value, a numerical value is assigned to it and it is encoded in the
form of a binary number, represented by ‗n‘ bits.
The values achieved after the quantization and encoding process are not
completely accurate. The accuracy of the quantizer highly depends on the resolution of

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 the qunatizer; greater the resolution, more accurate will be the values. The errors
generated from these inaccuracies are termed as quantization noise.

Fig. 3.4 Stages of analog to digital conversion

3.3 Parameters of ADC

The performance of an analog-to-digital converter depends on various parameters that define

the circuitry of the converter and also determine the choice of ADC to be used as per the
requirements. The parameters of ADC are as follows:
 Input Voltage Range - The input voltage range of an ADC is determined by the
reference voltage (Vref) applied to the ADC. A reference voltage can be either internal
voltage or external voltage. ADC will saturate to an analog voltage higher than the
reference voltage, so the designer must make sure that the analog input voltage does not
exceed the reference voltage. The input voltage range is also called as conversion range.
 Resolution - The entire input voltage range (from 0V to Vref) is divided into a number of
sub-ranges. Each sub range is assigned a single output digital code. A sub range is also
called LSB (least significant bits) and the number of sub ranges is usually in powers of
two. The total number of sub ranges is called the resolution of the ADC. For an example,
an ADC with 8 LSBs has the resolution of three bits (23 = 8). If an ADC‘s resolution is
three bits then it also means that the code width of the output is three bits.
[n – Number of bits]

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 Dynamic Range - Dynamic range is the ratio of the largest possible output (full-scale
voltage) to the smallest possible output (the least significant bit or quantum voltage),
mathematically 20log102N ≈ 6N.
 Signal to Noise Ratio (SNR) – Signal to Noise Ratio (SNR) is defined as the ratio of the
output signal voltage level to the output noise level. It is usually represented in decibels
(dBs) and calculated with the formula as follows:
( )
( ) ( )
( )

 Signal to Noise and Distortion Ratio (SNDR) – Signal to Noise and Distortion Ratio
(S/N+D, SINAD, or SNDR) is the ratio of the input signal amplitude to the rms sum of
all other spectral components. For an M-point FFT of a sine wave test, if the fundamental
is in frequency bin m (with amplitude Am), the SNDR can be calculated from the FFT
amplitudes.

(∑ ∑ )

 Effective Number Of Bits (ENOB) - Effective Number of Bits (ENOB) is the number of
bits with which the ADC behaves like a perfect ADC. It is simply the signal-to-noise-
and-distortion ratio expressed in bits rather than decibels.

 Spurious Free Dynamic Range (SFDR) - Spurious-free dynamic range (SFDR) is the
ratio of the input signal to the peak spurious or peak harmonic component. Spurs can be
created at harmonics of the input frequency due to nonlinearities in the ADC, or at sub-
harmonics of the sampling frequency due to mismatch or clock coupling in the circuit.
The SFDR of an A/D converter can be larger than the SNDR.
 Total Harmonic Distortion (THD) – Whenever an input signal of a particular frequency
passes through a non-linear device, additional content is added at the harmonics of the
original frequency. For example, assume an input signal having frequency f. Then the
harmonic frequencies are 2f, 3f, 4f, etc. So nonlinearity in the converter will produce
harmonics that were not present in the original signal. These harmonic frequencies
usually distort the output which degrades the performance of the system. This effect can

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 be measured using the term called total harmonic distortion (THD). THD is defined as
the ratio of the sum of powers of the harmonic frequency (usually first 5) components to
the power of the fundamental/original frequency component.

( )

V1 - Amplitude of the fundamental, Vn - Amplitude of the nth harmonic

 Effective Resolution Band Width (ERBW) – Eff ective Resolution Band Width
(ERBW) is the input-signal frequency where the SNDR of the ADC has fallen by 3 dB
(0.5 bit) from its value for low-frequency input signals.
 Full Power Band Width (FPBW) – Full Power Band Width (FPBW) is the maximum
frequency at which the ADC can reproduce a full-scale sinusoidal output without
distortion or where the amplitude of full-scale sinusoid is reduced by 3 dB.
 Sample and Hold Time – Usually after giving a trigger to an ADC to start a conversion,
it takes some time (in clock cycles) to charge the internal capacitor to a stable value so
that the conversion result is accurate. This time is called as sample time. This time must
be considered carefully especially when multiple channels are used during conversion. In
such case, there is a minimum time (in clock cycles) needed to guarantee the best
converted value between two ADC channel switching. After the sampling time, the
number of clock cycles it takes to convert the charge or the voltage across the internal
sampling capacitor into corresponding digital code is called the hold time.
 Settling Time – When using multiple channels, there may be cases in which each
channel may have different gain and offset configurations. Switching between these
channels requires some amount of time, before beginning the sample and hold phase, in
order to have good results. Especially care should be taken when switching between
differential channels. Once a differential channel is selected, the ADC should wait for
some amount of time for some of the analog circuits (for example the automatic offset
cancellation circuitry) to stabilize to the new value. This time is called as settling time.
So, ADC conversion should not be started before this time. Doing so will produce an
erroneous output. The same settling time should be observed for the first differential
conversion after changing the ADC reference.

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  Conversion Time – Conversion time is the combination of the sampling time and the
hold time, usually represented in number of clock cycles. The conversion time is the main
parameter in deciding the speed of the ADC.

3.4 Errors associated with ADC

No ADC is ideal and all of them experience several errors which need to be minimized. The
errors of ADC are as follows:
 Offset Error – Off set error is the deviation in the A/D converter‘s behavior at zero. The
first transition voltage should be 1/2 LSB above analog ground. Off set error is the
deviation of the actual transition voltage from the ideal 1/2 LSB. Off set error is easily
trimmed by calibration. With positive offset errors, the output value is larger than 0 when
the input voltage is less than 0.5LSB from below. With negative offset errors, the input
value is larger than 0.5LSB when the first output value transition occurs.

Fig. 3.5 Offset Error

 Gain Error – The gain error is defined as the deviation of the last step‘s midpoint of the
actual ADC from the last step‘s midpoint of the ideal ADC, after compensated for offset
error. After compensating for offset errors, applying an input voltage of 0 always give an
output value of 0. However, gain errors cause the actual transfer function slope to deviate
from the ideal slope. This gain error can be measured and compensated for by scaling the
output values.

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 Fig. 3.6 Gain Errors

 Full Scale Error – Full scale error is the deviation of the last transition (full scale
transition) of the actual ADC from the last transition of the perfect ADC, measured in
LSB or volts. Full scale error is due to both gain and offset errors.

Fig. 3.7 Full Scale Error

 Differential Non-Linearity (DNL) – Differential nonlinearity (DNL) is the deviation of

the code transition widths from the ideal width of 1 LSB. All code widths in the ideal
A/D converter are 1 LSB wide, so the DNL would be zero everywhere. Non-linearity
produces quantization steps with varying widths, some narrower and some wider.

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 Fig. 3.8 Differential Non-Linearity (DNL)

 Integral Non-Linearity (INL) – Integral nonlinearity (INL) is the distance of the code
centers in the ADC characteristic from the ideal line. If all code centers land on the ideal
line, the INL is zero everywhere.

Fig. 3.9 Integral Non-Linearity (INL)

 Missing Codes – Missing codes are output digital codes that are not produced for any
input voltage, usually due to large DNL. In the example below, the first code transition
(from 000 to 001) is caused by an input change of 250mV. This is exactly as it should be.

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The second transition, from 001 to 010, has an input change that is 1.25LSB, so is too
large by 0.25LSB. The input change for the third transition is exactly the right size. The
digital output remains constant when the input voltage changes from 1000mV to 1500mV
and the code 100 can never appear at the output. It is missing the higher the resolution of
the ADC is, the less severity the missing code is.

Fig. 3.10 Missing Codes

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CHAPTER 4

4.1 ADC Architectures

A large number of ADC architectures have been proposed till date. Out of them, a few have
been discussed in the following report, namely,
 Flash ADC
 Successive Approximation Register (SAR) ADC
 Sigma-Delta ADC
After the above discussion, the most suitable choice of ADC for low frequency applications will
be justified and concluded.

4.1.1 Flash ADC

Flash ADC, also called the parallel ADC is formed of a series of comparators, each one

comparing the input signal to a unique reference voltage. The comparator outputs connect to the
inputs of a priority encoder circuit, which then produces a binary output.

Fig. 4.1 Architecture of a 3-bit Flash ADC

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 Vref is a stable reference voltage provided by a precision voltage regulator as part of the
converter circuit, not shown in the schematic. As the analog input voltage exceeds the reference
voltage at each comparator, the comparator outputs will sequentially saturate to a high state. The
priority encoder generates a binary number based on the highest-order active input, ignoring all
other active inputs. The Priority Encoder has to find the position of the last comparator with high
output, starting from the bottom. That means that it should find the position where neighboring
comparators have different outputs (all below have output high and all above have output low).
That can be simply done by XORing the outputs of neighboring comparators and feeding their
outputs to a digital encoder. Only one XOR has its output active and the encoder will translate
that position into a binary representation. If there are 2N comparators, the encoder outputs an N-
bit number.

Fig. 4.2 Architecture of a 3-bit Flash ADC with XOR gates

When operated, the flash ADC produces an output that looks something like this:

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 Fig. 4.3 Analog input and Digital output of a Flash ADC

Advantages
 Simplest in terms of operational theory
 Most efficient in terms of speed, very fast and converts almost instantly
Disadvantages
 Doubles in size for each bit added to the representation (n bits require 2n-1 comparators)
 Highly expensive and requires a lot of space
 Has a high input capacitance (the input capacitance of a comparator multiplied by 2n-1)
 Large power consumption
 Resolution is low

4.1.2 Successive Approximation Register (SAR) ADC

The SAR ADC circuit typically consists of four chief sub-circuits:

 A sample and hold circuit to acquire the input voltage (Vin).
 An analog voltage comparator that compares Vin to the output of the internal DAC and
outputs the result of the comparison to the successive approximation register (SAR).
 A successive approximation register sub-circuit designed to supply an approximate
digital code of Vin to the internal DAC.
 An internal reference DAC that, for comparison with VREF, supplies the comparator with
an analog voltage equal to the digital code output of the SAR.

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 Fig. 4.4 SAR ADC Architecture

In the above circuit, the analog input voltage (VIN) is held on a track/hold. Initially, the
N-bit register is first set to midscale (that is, 100... .00, where the MSB is set to 1). This forces
the DAC output (VDAC) to be VREF/2, where VREF is the reference voltage provided to the ADC.
A comparison is then performed to determine if VIN is less than, or greater than, VDAC. If VIN is
greater than VDAC, the comparator output is logic high, or 1, and the MSB of the N-bit register
remains at 1. Conversely, if VIN is less than VDAC, the comparator output is logic low and the
MSB of the register is cleared to logic 0. The SAR control logic then moves to the next bit down,
forces that bit high, and does another comparison. The sequence continues all the way down to
the LSB. Once this is done, the conversion is complete and the N-bit digital word is available in
the register. The conversion time is directly proportional to the number of bits of the SAR ADC.

Fig. 4.5 Operation of a 4-bit SAR ADC

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 In the above example, the first comparison shows that VIN < VDAC. Thus, bit 3 is set to 0.
The DAC is then set to 01002 and the second comparison is performed. As VIN > VDAC, bit 2
remains at 1. The DAC is then set to 01102, and the third comparison is performed. Bit 1 is set to
0, and the DAC is then set to 01012 for the final comparison. Finally, bit 0 remains at 1 because
VIN > VDAC.
Advantages
 Low power consumption
 Capable of high speed and reliable
 Medium accuracy and higher resolution compared to other ADC types
 Good tradeoff between speed and cost
Disadvantages
 The DAC grows with the number of bits, thereby increasing the conversion time
 The higher the resolution, slower will be the ADC
 Speed is limited to about 5 MSPS

4.1.3 Sigma Delta ADC

Sigma-Delta ADC is one of the most advanced ADCs. In mathematics and physics, the
capital Greek letter delta (Δ) represents difference or change, while the capital letter sigma (Σ)
represents summation: the adding of multiple terms together. Sometimes this converter is
referred to by the same Greek letters: sigma-delta, or ΣΔ.
The sigma-delta converter is unique in that it samples the signal in a much higher
frequency than the Nyquist frequency. For that reason it is also called oversampling converter. It
converts the input signal Vin by integrating the error between a reference signal xdac that can be
either Vref or zero and the input signal. Then, the output of the integrator xint is compared with
zero. That comparator result xadc is sampled and sets the reference signal xdac to Vref or zero in the
next cycle. This process is repeated over and over and the streams of 1‘s and 0‘s coming out of
the second comparator average out to the input value. The stream of 1's and 0's is subsequently
digitally filtered (decimation filter) to produce a slower stream of multi-bit samples. The sigma-
delta modulator loop typically runs at a much higher frequency than the final output rate of the
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digital filter.

Fig. 4.6 Sigma-Delta ADC Architecture

For example, if Vin=1V, Vref=2.5V, the outputs from the comparator will be: 1, 0, 1, 1, 1, 0, 1, 1.
This means 6 of the 8 outputs have been a 1; i.e. output is 75% of full scale. The allowed input
range is -2.5 to +2.5 (+/-Vref) so the span is -2.5 to +2.5. With a 1V input, the input is 3.5V above
the bottom of the 5.0V span or 70% of full scale. If looping is continued, the ones density of the
above output stream will get closer and closer to 70%.
Advantages
 Due to a large oversampling, the quantization noise spectral density is reduced
 Allows noise shaping (quantization noise is attenuated at lower frequencies)
 High resolution
 No precision external components needed and very simple circuits
Disadvantages
 Speed is slow due to over sampling

4.2 Justification of choice of ADC

From the above discussion of the different ADC architectures, the following conclusion
has been reached. The Flash ADC architecture is not taken into consideration while designing an
ADC for LF applications because it hardly reaches a 14-bit resolution. From the remaining SAR
and Sigma-Delta ADC architectures, none has an obvious advantage at first sight. However, the

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SAR ADC architecture has been used extensively in multiplexed data acquisition systems, which
is perfect for our application. Sigma-Delta ADC architecture is typical for precision industrial
measurement as well as voice band and audio applications.

Fig. 4.7 ADC architectures, applications, resolution and sampling rates

Hence, a SAR ADC can be considered to be best suited for low frequency applications.

4.3 Types of SAR ADC

There are mainly 3 types of SAR ADC, which are discussed as follows:
 Single-Ended Inputs - An ADC with single-ended inputs digitizes the analog input
voltage relative to the ground. Single-ended inputs simplify ADC driver requirements,
reduce complexity and lower power dissipation in the signal chain. Single-ended
inputs can either be unipolar or bipolar, where the analog input on a single-ended
unipolar ADC swings only above GND (0V to VFS, where VFS is the full-scale input
voltage that is determined by a reference voltage) (Figure (a)) and the analog input on a
single-ended bipolar ADC also called true bipolar, swings above or below GND (±VFS)

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 Fig. 4.8 (a) Single-Ended Unipolar (b) Single-Ended True Bipolar

 Pseudo-Differential Inputs - An ADC with pseudo-differential inputs digitizes the

differential analog input voltage (IN+– IN–) over a limited range. The IN+ Input has
the actual analog input signal, while the IN–input has a restricted range. A pseudo-
differential unipolar ADC digitizes the differential analog input voltage (IN+ – IN–)
over a span of 0V to VFS. In this range, a single-ended unipolar input signal, driven on
the IN+ pin, is measured with respect to the signal ground reference level, driven on the
IN–pin. The IN+ pin is allowed to swing from GND to VFS, while the IN–pin is
restricted to around GND ± 100mV (Figure 4.9 (a)).
A pseudo-differential bipolar ADC digitizes the differential analog input voltage
(IN+ – IN–) over a span of ± VFS /2 n this range, a single-ended bipolar input signal,
driven on the IN+ pin, is measured with respect to the signal mid-scale reference level,
driven on the IN–pin. The IN+ pin is allowed to swing from GND to VFS, while the
IN– pin is restricted to around VFS /2 ± 100mV(Figure 4.9 (b)).
A pseudo-differential true bipolar ADC digitizes the differential analog input
voltage (IN+– IN–) over a span of ±VFS. In this range, a true bipolar input signal, driven
on the IN+ pin, is measured with respect to the signal ground reference level, driven on
the IN–pin. The IN+ pin is allowed to swing above or below GND to ±VFS, while the
IN–pin is restricted to around GND ± 100mV (Figure 4.9 (c)).
Pseudo-differential inputs help separate signal ground from the ADC ground,
allowing small common-mode voltages to be canceled. They also allow single-ended
input signals that are referenced to ADC ground. Pseudo-differential ADCs are ideal for
applications that require DC common-mode voltage rejection, for single-ended input

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 signals and for applications that do not want the complexity of differential drivers.
Pseudo-differential inputs simplify the ADC driver requirement; reduce complexity and
lower power dissipation in the signal chain.

Fig. 4.9 (a) Pseudo-Differential Unipolar (b) Pseudo-Differential Bipolar (c) Pseudo - Differential
True Bipolar

 Fully-Differential Inputs - An ADC with fully-differential inputs digitizes the

differential analog input voltage (IN+– IN–) over a span of ±VFS. In this range, the IN+
and IN– pins should be driven 180º out-of-phase with respect to each other, centered
on a fixed common mode voltage, for example, VREF/2 ±50mV. In most fully-
differential ADCs, both the IN+ and IN–pins are allowed to swing from GND to VFS
(Figure 4.10 (a)), while in fully-differential true bipolar ADCs, both the IN+ and IN–
pins are allowed to swing above or below GND to ±VFS (Figure 4.10 (b)). Fully-
differential inputs offer wider dynamic range and better SNR performance over single-
ended or pseudo-differential inputs. Fully differential ADCs are ideal for applications
that require the highest performance.

Fig. 4.10 (a) Fully Differential (b) Fully Differential True Bipolar

It is evident from the above discussion regarding the various kinds of SAR ADCs that the

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Fully Differential one provides the best performance among all the others. Thus, a Fully
Differential SAR ADC has been considered for designing the ADC for LF applications.

4.3 Specifications of ADC

The analog input range of the14-bit ADC is [109uV, 1.8V]. Assuming a Comparator gain
of 86dB full analog input range is used. The ADC will work on voltage signals, and neither on
current nor on charge signals. The length and width of the ADC are not specified. As most
implantable chips are battery-powered, Low Power ADC is required.

The ADC must have a Differential Non-Linearity smaller than 1 (DNL<1) and an Integral Non-
Linearity smaller than 1.5 (INL<1.5).
Table 4.1 Specifications of the required 14-bit Multi Channel Fully Differential SAR ADC

Type SAR

Topology Multi-Channel Fully Differential

Technology 180nm SCL

Supply voltage 1.8 V

Input voltage 1 V p-p

ENOB 12 bits

SINAD (dB) 80 dB

SFDR (dB) 90 dB

SNR (dB) 74 dB

Input signal frequency 10 Hz – 500 Hz

Sample Rate 100 Hz – 50kHz

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CHAPTER 5

5.1 Fully Differential SAR ADC

With a limited signal swing, the sampling capacitance must be large enough to achieve a
high signal-to-noise ratio (SNR), which leads to large current consumption. However, in SAR
architectures, no component consumes static power if pre-amplifiers are not used. A SAR ADC
can easily achieve a rail-to-rail signal swing, that is, a small sampling capacitance is
sufficient to achieve a high SNR. The conversion time and power dissipation become smaller
with the advancement of CMOS technologies. Since SAR ADCs take advantage of
technological progress, for some high-conversion-rate applications, power and area-efficient
SAR ADC can possibly replace pipelined ADCs in nanometer scaled CMOS processes. In
SAR ADC, the primary sources of power dissipation are the digital control circuit,
comparator, and capacitive reference DAC network. Digital power consumption becomes
lower with the advancement of technology. Technology scaling also improves the speed of
digital circuits. On the other hand, the power consumption of the comparator and capacitor
network is limited by mismatch and noise.

5.2 Advantages of Differential-ended ADC over Single-ended ADC

The primary advantage of differential ADC is high common-mode noise immunity

compared to single-ended ADC. This noise immunity is due to 1) the same noise being coupled
on both the inverting and non-inverting input signals of the ADC, and 2) this noise is rejected by
common-mode rejection capabilities of the differential ADC.
In differential ADCs, both input signals are physically run in parallel with each other.
Thus the same amount of noise gets coupled into both the signals. Moreover, when both signals
are running in parallel and run the same distance (same trace/wire length), they are in the same

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phase when they reach the ADC. As noise coupled on both signals has the same amplitude and
same phase, it gets rejected to provide very high noise immunity. This high noise immunity
makes differential ADCs the best fit in the applications where the output signal from a sensor is
very small and/or noise in the system is very high.
In differential ADCs, SNR is also improved because of the change in the dynamic
range. The dynamic range of a differential ADC is given by Vin- ± Vin+. In these ADCs,
generally, both inputs can range from VSS to VDD (low supply rail to high supply rail). This makes
the dynamic range twice as much as in case of single-ended ADC. Thus the SNR is improved by
6dB just because of a higher dynamic range in the differential ADC.
Also, any DC offset (limited only by common-mode voltage) can be provided for signals
that are too small and have amplitude close to the lower supply rail, or for signals that have a
voltage below the ADC ground. This DC offset gets removed by the common-mode rejection
characteristics of differential ADCs. It also reduces the significant overhead that would have
been required to remove the DC offset if a single-ended ADC was used.

5.3 Multi-Channel Fully Differential SAR ADC

For low frequency applications, the ADC requires at least 3 channels and has been designed so.

Moreover, the requirements of the project were:

 The user will supply a single-ended signal at the input. The ADC must convert it
to a differential-ended signal and subsequently, convert it to binary.
 The user must be able to access any of the output at any time during the conversion time.
 There must be a provision to use the ADC as single channel also.
To address the above issues, the following actions were taken:
 A Multi-Channel Driver Buffer has been designed to convert the single-ended (SE)
signal at the input to differential-ended (DE) signal and also make it suitable for
operation in other blocks.
 To allow access to any channel at any time, a combinational circuit has been designed. A
14-bit De-multiplexer and three Internal Registers have been designed to store the data
temporarily. If the user wants to access the output later on in the future, the binary data
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 will be fed to the user by a 14-bit Multiplexer and a Register.
 As the Clock control circuit was difficult to design by FSM, the clock network was
designed using Stored Procedure Control (SPC). The whole clock network was soft
coded i.e. programmed into a ROM so that the clock network can be changed at any
instant as and when needed. Since diode is not present in the SCL pdk, the ROM
was designed using NMOS only. This is because NMOS consumes less area than
PMOS. However, the challenge was to design the ROM such that the when a logic ‗1‘
arrives, the NMOS must charge the crossbar to a certain level such that the output
buffer pulls the in-between logic to Logic ‗1‘. The ROM is controlled by a Counter and
a Decoder. Both of them have been designed such that they are reset when they are
powered on.

Fig. 5.1 Block diagram of Multi-Channel Fully Differential SAR ADC

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Fig 5.2 Operation of Multi-Channel Fully Differential SAR ADC

Fig. 5.3 Internal architecture of Fully Differential SAR ADC

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.

Fig. 5.4 Timing diagram of Fully Differential SAR ADC

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The timing diagram can be summarized as follows:
 Ext_Clk, CS and Conversion Start Signal will be provided by the user.
 Internal_Clk will be generated when CS and Conversion Start signal are high.
 C0, C1 are internal signals generated to select the Analog Input Channel.
 Sample Signal is given to Sample & Hold block as Sample_Clock.
 ADC_Clk will generate at the positive edge of Internal_Clk after the negative edge of
Sample Clock and it will follow the Internal_Clk for 14 conversion cycles. After that, it
will stop to reduce the dynamic power.
 After 14 clock cycles, the Register_Clk will be enabled and depending upon C0 and C1, it
will transfer the output to the dedicated register. C0 and C1 have been started from ‘01‘
combination as ‗00‘ combination is a risk to false start the ADC core.

5.4 Architecture of Multi-Channel Driver Buffer

The Multi-Channel Driver Buffer is the interface between the outside world and the ADC
world. Its main purpose is to convert the single-ended (SE) signal received from the outside
world and convert it to a differential-ended (DE) signal with respect to a reference voltage,
suitable for conversion into binary by the ADC. It consists of 4 parts, namely:
 Input Differential Stage - This block receives the analog single-ended signal from
user/nature along with a reference voltage and converts the SE signal into a differential-
ended signal with respect to the reference voltage. This stage provides the signal a
constant value of transconductance.
 Cascode Stage - This stage consists of a folded cascade circuit having high output
impedance. High impedance increases the open loop gain of the Driver.
 CMFB Stage - This stage receives the differential output from the Cascode Stage and
after comparing it with a reference voltage, a bias voltage is fed back to the Cascode
Stage. This voltage is required to provide a constant bias to the Cascode Stage.
 Buffer Stage - The differential output of the Cascode Stage is fed to this stage also.
Here, the impedance of the signal is matched so that it can be matched with any low
impedance block being used in the upcoming blocks.
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 Fig. 5.5 Block Diagram of Multi-Channel Driver Buffer

5.5 Architecture of Sample and Hold Array

Conventional sample hold circuit is made either using transmission gate (TG) or simply,
a transistor and a holding capacitor. However, in these cases, the transistors must be kept in
linear region for switching purposes. To operate the MOS in linear region, must be constant or
. In case of Differential ADC, sampling voltage is the summation of common mode
voltage ( ) and input voltage ( ). Hence, source voltage of transistor depends on input
voltage. If the gate terminal of NMOS is kept at , then,

From the above equation, it is seen that depends on the input voltage which is varying
in nature. So, transistor‘s region of operation will change. Hence, sample and hold will not
operate in linear region. To solve this problem, some constant voltage must be added which will
compensate the effect of input voltage. Thus, track and hold switch or bootstrap switch is
implemented for the switching the transistor but, practically voltage source cannot be added
within the circuit. So, voltage source will be replaced by a capacitor ( ) which will store
the required voltage by some switching mechanism.

Fig. 5.6 NMOS switch for Sample and Hold

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 In Fig. 5.6, will be needed in the hold phase for charging and in the track phase, it
will provide the constant to keep the MOS‘s in linear region. Current through this
capacitor must be zero; otherwise charge will be lost and MOS‘s will no longer be in linear
region. In the hold phase, all the switches will be on and initially the capacitor ( ) will
charge through path 1 and in this stage, M1 transistor will be off through path 2. In the track
phase, all the switches will be on. Hence, will provide required voltage to the gate
terminal of M1 and the source voltage will pass to charge the holding capacitor. Now the
switches can be made using three combinations:
 NMOS must be used when switching node voltage will be low.
 PMOS must be used when switching node voltage will be high.
 TG must be used when switching node voltage will be varying in nature.

Fig. 5.7 Track and Hold Concept

Switch 1 will depend upon . Since the input voltage is varying in nature, it will vary
from 0.4V to 1.4V. Depending on the input voltage, different voltage will pass through switch
1. Hence, this switch will be replaced by TG based switch.
Switch 2 and 3 will be implemented by NMOS as the voltage is zero at the terminal. Switch
2 will complete the charging path of capacitor to ground. Hence, it is a low voltage switching
case. Similarly, switch 3 will help keep the M1 transistor off during the hold phase. M1 is
basically an NMOS transistor. So, to switch it off, low voltage has to be given in the gate
terminal of M1. Hence, it is also a low voltage switching case.
Switch 4 will be used in the tracking phase to provide the constant amount of voltage at
the gate terminal of M1 transistor through capacitor. In the track phase of this switch, high
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voltage is required. Hence, PMOS switch will be suitable here. The body of the PMOS is
connected to as it provides the higher voltage. If the body was connected to the other
terminal, then the transistor will be in saturation region and current will be drawn out form the
switching transistor.
Switch 5 will be used to charge in the hold phase. Hence, PMOS transistor is
suitable as needs to be charged at a high voltage which will be passed via this switch. For
this purpose, a certain amount of voltage is to be maintained at the gate terminal of the PMOS but
to control the switch, a voltage higher than is required to keep the transistor in linear
region. So, the controlling voltage must be . Now, in order to generate , a
capacitor and a switch are needed. The switch has t o be controlled by ̅̅̅ , and to
generate this voltage, another switch and capacitor are needed. This switch has to be controlled by
. So, two back to back switches, controlled by each other, are required. The input of the
capacitors are connected with and ̅̅̅. This circuit arrangement is known as charge pump
circuit or Nagakome Charge Pump circuit.

Fig. 5.8 Circuit diagram of Track and Hold arrangement

In the diagram of bootstrap switch, there are two phases - tracking or sampling phase and
holding phase. There are five switches present, in which two switches will be on in the tracking
phase and rest will be on in the holding phase. The most important criteria for operation of the
bootstrap switches 1, 4 and switches 2, 3, 5cannot be on at the same time, that is, when is
on, is off and vice versa. Hence, two non-overlapping pulses are required, which will
control these switches.

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 Fig. 5.9 shows a SR, latch which will create two non-overlapping pulses. Here, if the sample
signal is a pulse kept at 0, then one input of first NAND gate is 0 and another NAND gate is 1.
The output of second NAND will be 0 and that is fed back to the input of the first NAND.
Hence, the output of second NAND gate will be 1. This will continue until the sample signal
switches to 1. After sample signal‘s switches to 1, output of the first NAND will fall to zero which
will go to the input of the second NAND and make that output 1. However, it is visible from Fig.
5.9 that there is some delay in the output, which is nothing but the delay of an individual
NAND gate. After the NAND gates output we use an inverter and buffer to get the non-
overlapping signal according to sample signal.

Fig. 5.9 Schematic of Non-Overlapping Clock

Fig. 5.10 Waveform of pre-layout simulation of Sample and Hold Circuit

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 Fig. 5.11 Layout of Sample and Hold Circuit

Fig. 5.12 Waveform of post-layout simulation of Sample and Hold Circuit

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 Fig. 5.13 Comparison of pre-layout and post-layout simulation of Sample and Hold Circuit

5.6 Architecture of SAR Logic (Synchronous Shift Register)

The SAR Logic, that is, the Synchronous Shift Register is designed using D-flipflops

(DFF). The DFF is based on transmission gate to minimise the transistor count. The DFF has
Enable, Reset and Set pins. Initially, all the DFF‘s were reset to zero, then on each rising edge of
clock the data shifted from 1st output to last output. The Reset and Set pins are low enable in the
design but the Enable is High enable.
Fig. 5.14 shows the circuit diagram of TG based master-slave DFF having enabled
control. The first part of the circuit acts as master and the latter one behaves as slave. Initially,
reset and set are 1 (not active). When the clock signal is ‗0‘, then first and fourth TG will
switch on. Data will pass within the master block. When the clock signal will be ‗1‘ then it
will on the second and fourth TG to pass the data from master to slave cycle and from slave to
output cycle. Output data will be passed in the reversed form. Hence, an inverter is used. After
that, an AND gate is used to make the DFF enable dependent. In case the set signal is activated,
then output will be forced to ‗1‘. A similar case will happen for reset signal also which will
forcefully make the output ‗0‘.

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Fig. 5.14 Schematic of a TG based DFF

Fig. 5.15 Layout of TG based DFF

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 Fig. 5.16 Waveform of pre-layout simulation of TG based DFF

Fig. 5.17 14-bit Shift Register using TG based DFF

Fig. 5.18 Schematic of 14-bit Shift Register using TG based DFF

As seen in Fig. 5.18, the DFF labelled as Clk1 receives the input and its output is fed to the Clk2
DFF. The remaining DFFs are connected in a similar manner. In the 0th clock cycle, Clk1 is set to
logic ‗1‘ while the other DFFs are reset to logic ‗0‘. In the following clock cycles, the remaining
DFFs from Clk2 to Clk13 are set to logic ‗1‘. As the ‗1‘ shifts, the DFFs hold their respective

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values till the circuit is reset.
Table 5.1 SAR Logic Implementation
Cycle Clk1 Clk2 Clk3 Clk4 Clk5 Clk6 Clk7 Clk8 Clk9 Clk10 Clk11 Clk12 Clk13
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0
2 1 1 0 0 0 0 0 0 0 0 0 0 0
3 1 1 1 0 0 0 0 0 0 0 0 0 0
4 1 1 1 1 0 0 0 0 0 0 0 0 0
5 1 1 1 1 1 0 0 0 0 0 0 0 0
6 1 1 1 1 1 1 0 0 0 0 0 0 0
7 1 1 1 1 1 1 1 0 0 0 0 0 0
8 1 1 1 1 1 1 1 1 0 0 0 0 0
9 1 1 1 1 1 1 1 1 1 0 0 0 0
10 1 1 1 1 1 1 1 1 1 1 0 0 0
11 1 1 1 1 1 1 1 1 1 1 1 0 0
12 1 1 1 1 1 1 1 1 1 1 1 1 0
13 1 1 1 1 1 1 1 1 1 1 1 1 1

Fig. 5.19 Waveform of pre-layout simulation of 14-bit Shift Register using TG based DFF

Fig. 5.20 Layout of 14-bit Shift Register using TG based DFF

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 Fig. 5.21 Waveform of post- layout simulation of 14 -bit Shift Register using TG based DFF

Fig. 5.22 Comparison of pre-layout and post-layout simulations of 14 -bit Shift Register using TG based DFF

5.7 Architecture of ADC

The ADC is the heart of the whole design being developed. Its main components include
a self-calibrated Split Calibration DAC, a self-calibrated Double Tail Dynamic Comparator and
the SAR Logic. All the components of the ADC have been discussed hereafter.

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5.7.1 Architecture of Split Capacitive DAC and its switches

The Split Capacitive DAC implementation with a timing diagram has been shown in Fig.
5.23. For simplicity of understanding, single-ended circuit has been considered.
During calibration, all MSB-side capacitors except for the lowest bit are connected to
ground. When ϕS=1, both nodes P and Q are biased to common-mode voltage VCM. The lowest
bit of the MSB-side array is set to logic 0 and the LSB-side array is set to 11111. When ϕS=0,
both nodes P and Q become floating. Then, the lowest bit of the MSB-side array is set to logic 1
and the LSB-side array is set to 00000. The calibration capacitor CC is initially set to the smallest
value in its tunable range and thus, the total weight of the LSB-side array is initially larger than
the lowest bit of the MSB-side array. Since the charge in node P has to be kept constant during
ϕS=0, VP becomes smaller than VCM. The comparator compares VP and VCM and feeds back its
output to increase CC so that the weight of the LSB-side array becomes smaller. The process
repeats itself till VP becomes equal to VCM and the comparator output changes. This is the instant
when the LSB-side array has the same weight as the lowest bit of the MSB-side array and hence,
calibration is completed.

Fig. 5.23 Split Capacitive DAC implementation with Timing Diagram

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 The structure of the Split Capacitive DAC being implemented here includes 3 major parts
– Most Significant Bit set of capacitors (MSB), Least Significant Bit set of capacitors (LSB) and
a Bridge Capacitance (CB). The value of Bridge Capacitance (CB) is equal to that of the unit
capacitance (Cµ) being in the DAC. The MSB has 7 capacitors, whose top plates are connected to
each other and bottom plates are connected to either ground or a certain voltage as required via
switches. The MSB-side capacitors have values of Cµ, 2Cµ, 21Cµ, 22Cµ, 23Cµ, 24Cµ, 25Cµ and
26Cµ. The LSB-side capacitor array has a similar structure with the exception of an extra
capacitor of value Cµ. One terminal of CB is connected to the top plate of the LSB-side capacitor
array and the other to the top plate of the MSB capacitor array. The value of Cµ being used is 300
fF.

Fig. 5.24 Schematic of Split Capacitive DAC

Fig. 5.25 Layout of Split Capacitive DAC

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 The above DAC is controlled by an array of 14 switches. They control the voltage being
provided to each capacitor of the DAC. Each switch is made up of transmission gates, AND gate,
OR gate and a few inverters. It is a 2-way switch being controlled by 2 signals – one coming
from the DAC Control Logic and the other from the DAC calibration block.

Fig. 5.26 Schematic of DAC Switch

Fig. 5.27 Layout of DAC Switch

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 The above switch is used for each of the capacitors in the Split Capacitive DAC, that is,
an array of 14 switches has been used.

Fig. 5.28 Schematic of DAC Switch Array

Fig. 5.29 Layout of DAC Switch Array

5.7.2 Architecture of Calibration DAC (CDAC)

In practice, a DAC can never store the exact amount of charge required. Any deviation of
the charge from its value builds up gradually to give an erroneous output. This random variation
in charge of the DAC elements during the process is termed as mismatch. The higher the degree
of mismatch among the DAC elements, the worse will be the linearity of the DAC and
consequently, the worse will be the overall output of the SAR ADC. One solution for avoiding
mismatch is the use of calibration. In this method, the variation in charge of the DAC elements is
compensated by a separate set of capacitor array, named as calibration DAC (CDAC).
The structure of the CDAC is very simple. It consists of 16 capacitor elements. All of their top
plates are connected together while their bottom plates are connected to an NMOS switch. The
bottom plates of the CDAC elements are connected to the drain of the NMOS switches. The gate
of the NMOS is controlled by a specific logic, which will be discussed later in this chapter.

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Fig. 5.30 Schematic of Calibration DAC with switches
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From Fig. 5.30, it is seen that all the capacitor elements are not equal. Towards the output node
of the CDAC, the capacitor elements are of higher value than that of those away from the output
node. The design is purposely made such, so that the initial calibration is rapid (coarse tuning)
and as time progresses, the calibration becomes slower (fine tuning). The elements having values
of Cµ are responsible for fine tuning and those having values of multiples of Cµ are involved in
coarse tuning. The capacitor values of the p-side and n-side CDAC are different; the n-side
requires more calibration. The exact capacitance value has been fixed by trial and error.

Fig. 5.31 Schematic of p-side CDAC

Fig. 5.32 Schematic of n-side CDAC

The switch has been implemented using an NMOS. The bottom plates of the CDAC
elements are connected to the drain of the NMOS switches. The gate of the NMOS is controlled
by a specific logic. When the control voltage to the gate of the NMOS is zero, virtually no
current conducts through the NMOS and it acts an open circuit. Whereas when the control
voltage is positive, the NMOS acts a short circuit and conducts current, thereby allowing its
respective capacitor to discharge through itself.
The main advantage of this particular design is that it reduces the number of clock pulses
required to complete the calibration process mainly due to the rapid calibration technique.

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 Fig. 5.33 Layout of p-side CDAC with switches and dummies

Fig. 5.34 Layout of n-side CDAC with switches and dummies

The control logic driving the CDAC is based on the SAR Logic as discussed in 5.6. The
only difference between the two is that the CDAC control logic uses 28 shift registers as
compared to the 14 shift registers of the SAR Logic as shown in Fig. 5.35. Moreover, the Clk0
DFF is always set to ‗1‘, unlike that of the SAR Logic discussed in 5.6.

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 Fig. 5.35 Schematic of CDAC Control Logic

Fig. 5.36 Layout of CDAC Control Logic

Fig. 5.37 Waveform of simulation of CDAC Control Logic

The whole process of calibration needs to be controlled properly. This block receives the
comparator outputs and accordingly generates the clocks for both p and n-side DACs and also
the DAC charge distribution clocks. It also produces signals for reset and end of calibration.

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 Fig. 5.38 Schematic of Calibration Control

Fig. 5.39 Layout of Calibration Control

Fig. 5.40 Waveform of simulation of one side of CDAC with Calibration Control

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5.7.3 Architecture of Comparator with Calibration

The proper functioning of an ADC is massively dependent on Comparator, without

which conversion will fail. The performance of comparators depends upon factors such as, offset
voltage, resolution and power dissipation, of which offset voltage is critical. Lower the offset
voltage, better will be the performance. In this case, a Double Tail Dynamic Comparator has
been used as shown in Fig. 5.41. In order to reduce the effect of offset, a calibration technique
has been employed.

Fig. 5.41 Schematic of Double Tail Dynamic Comparator

The above comparator consists of 3 parts – an input gain stage (lower portion), an output
latch stage (upper portion) and an arrangement for offset calibration. and are the primary
inputs of the comparator whereas and are the inputs used for offset calibration. When
, M8 is off and so, power supply is cut off from the output latch stage. M11 is also off
and as a result, offset calibration does not happen. Moreover, M10 is off, thereby cutting off
ground from the input gain stage but M5, M6, M7 and M9 being on, nodes Di+ and Di- will hold
some voltage. This makes both the comparator outputs, and go to ‗1‘.

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 When , M10 is on but M5 and M6 are off. This allows the voltage developed at
nodes Di+ and Di- due to inputs and respectively, to switch on M15 and M4 respectively.
Since M11 is on, comparator is calibrated; and will adjust the voltages at nodes Di+ and
Di- respectively. Output latch stage is active because M8 is on. This stage determines which
node voltage is greater – if voltage at Di+ is more than that of Di-, then is set to ‗1‘ and
to ‗0‘ while the opposite happens if Di+ is less than Di-.

Fig. 5.42 Layout of Double Tail Dynamic Comparator

For the above comparator to function properly, its clock needs to be timed accurately. For
this purpose, a separate circuit has been designed to generate the comparator clock using the
main clock and DAC calibration control signals. The required circuit is shown in Fig. 5.43.

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 Fig. 5.43 Schematic of Comparator Control Circuit

Fig. 5.44 Layout of Comparator Control Circuit

As discussed earlier, this comparator needs offset calibration before it begins its actual
operation. The required circuit, as shown in Fig. 5.45, uses the comparator output voltages to
determine how much adjustment is essential. In order to control this calibration process, another
circuit, as shown in Fig. 5.47, has been designed. This block generates 2 non-overlapping clocks
using the comparator outputs to be used for comparator calibration.

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Fig. 5.45 Schematic of Comparator Calibration Circuit

Fig. 5.46 Layout of Comparator Calibration Circuit

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Fig. 5.47 Schematic of Comparator Calibration Control Circuit

Fig. 5.48 Layout of Comparator Calibration Control Circuit

Fig. 5.49 Schematic of Comparator with Calibration

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 Fig. 5.50 Layout of Comparator with Calibration

Fig. 5.51 Waveform of Comparator with Calibration

5.7.4 Architecture of DAC Control Logic

Fig. 5.52 shows a circuit diagram and Fig. 5.52 a timing diagram of the DAC control
logic. At the rising edge of clock, static flip-flop samples the comparator output. If the output

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is high, the relevant capacitor is switched from VDD to ground. If the output is low, the
relevant capacitor is kept connected to VDD. At the falling edge of clock, all capacitors are
reconnected to zero. The delay buffer guarantees that the AND gate is triggered after the output
of the static flip-flop. This timing arrangement avoids unnecessary transitions. This operation
uses an inverter as a switch buffer. The conventional architecture samples both the input signal
and reference voltages on the bottom plates. If the input swing is nearly rail-to-rail, transmission
gates are needed to sample input signal. Bootstrapped switches are used to sample input signal
onto the top plates of the capacitors and inverter buffers are used to switch between positive and
negative voltages. Hence, compared to the conventional architecture, no transmission gates are
used, which enables high-speed and low-power operation.

Fig. 5.52 Circuit diagram of 1-bit DAC Control

Fig. 5.53 Timing diagram of 1-bit DAC Control

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 Fig. 5.54 Circuit diagram of DAC Control with Switch to control Capacitor

Fig. 5.55 Circuit diagram of DAC Control with SAR Logic

As shown in Fig. 5.54, DAC control logic includes a DFF, an AND gate and a delay
buffer to make sure that the CLK triggers AND gate only when the output of DFF is generated;
and the last DAC control part is only a DFF that will generate last bit. As per Fig. 6.51, at the
rising edge of CLK1 and CLK2, DFF samples the comparator output . As is low,
the DAC control signals DAC CON P1 and DAC CON P2 are high, thus switching the relevant
capacitor switches. Again at rising edge of CLK3, comparator output is high, which
results in DAC CON N3 being high to control the corresponding capacitor switch.

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Fig. 5.56 Schematic of 1-bit DAC Control

Fig. 5.57 Layout of 1-bit DAC Control

Fig. 5.58 Schematic of 14-bit DAC Control

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 Fig. 5.59 Layout of 14-bit DAC Control

Fig. 5.60 Waveform of pre-layout s i m u l a t i o n of 14-bit DAC Control

Fig. 5.61 Waveform of post-layout s i m u l a t i o n of 14-bit DAC Control

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 Fig. 5.62 Comparison of pre-layout and post-layout simulations of 14-bit DAC Control

5.7.5 Architecture of Delay Buffer

Delay buffers have been used for two reasons – firstly to match the propagation delay

between analog and digital blocks and secondly, in layout, to maintain the signal integrity between
the two blocks sitting far apart from each other.

Fig. 5.63 Schematic of Delay Buffer

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 Fig. 5.64 Layout of Delay Buffer

5.8 Architecture of Clock Network

For complex clock signals, it is difficult to design the clock network where input

variable is only an external clock. Moreover, the circuit complexity increases, and a number
of loop increases. So, it might happen that after layout, these dependencies might not work as
the set up and hold time might get violated. It might also happen that the requirement of clock
changes after some issues. Then, it is difficult to redesign the clock using FSM. So, the clock
circuit has been programmed to a ROM. This architecture is like the procedure control in
microprocessors i.e. Stored Procedure Control (SPC). The architecture contains a counter, a
decoder, and a ROM. All the FF‘s in the counter are set at power on using few delay buffers so
that, after the first clock pulse, these components are reset to 0. As diode is not present in the
SCL pdk, the ROM was designed using NMOS only because NMOS consumes lesser area than
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PMOS and for homogeneity in the layout. However, the challenge was to design the ROM for a
strong logic ‗1‘ made of NMOS transistors. So, an output buffer was provided to convert the weak
‗1‘‘s produced by NMOS transistors into strong ‗1‘‘s. To pull down the crossbar line to Logic
‗0‘, the NMOS is sufficient as NMOS produces strong Logic ‗0‘. The crossbar architecture
helps to reprogram the clock network as many times as possible.

Fig. 5.65 Block diagram of the clock network

Fig. 5.66 Schematic of Counter reset to ‗48‘

Fig. 5.67 Layout of Counter reset to ‗48‘

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Fig. 5.68 Waveform of pre-layout simulation of Counter reset to ‗48‘

Fig. 5.69 Schematic of 6:64 Decoder

Fig. 5.70 Layout of 6:64 Decoder

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Fig. 5.71 Waveform of pre-layout simulation of 6:64 Decoder

Fig. 5.72 Schematic of Crossbar architecture using NMOS

Fig. 5.73 Layout of Crossbar architecture using NMOS

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 Fig. 5.74 Layout of Clock Control Unit developed using SPC

Fig. 5.75 Waveform of pre-layout simulation of Clock Control Unit developed using SPC

Fig. 5.76 Waveform of post-layout simulation of Clock Control Unit developed using SPC

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 Fig. 5.77 Comparison of pre-layout and post-layout simulations of Clock Control Unit developed using SPC

5.9 Architecture of Register Control

The register control is provided after the clock control unit to select the register to store

the 14-bit output to the dedicated registers. The register must hold the data until the next data
comes from the same channel and the data must not b e written to any other registers. This
also reduces the dynamic power consumption because no node switches at that time. The Register
Control must be generated from the output register enable signal and C0, C1 generated by SPC.

Fig. 5.78 Schematic of Register Control

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Fig. 5.79 Layout of Register Control

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 Fig. 5.80 Waveform of pre-layout simulation of Register Control

Fig. 5.81 Waveform of post-layout simulation of Register Control

Fig. 5.82 Comparison of pre-layout and post-layout simulations of Register Control

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5.10 Architecture of 14-bit Demultiplexer
The Demultiplexer is used for writing the 14-bit output data to the specified registers.

After 14 cycles of the clock, when the data is ready to be written, the Enable signal is high and
based on C0 and C1 the Demultiplexer performs the write operation to the specified registers.

Fig. 5.83 Schematic of 1-bit Demultiplexer

Fig. 5.84 Schematic of 14-bit Demultiplexer

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 Fig. 5.85 Layout of 1-bit Demultiplexer

Fig. 5.86 Waveform of pre-layout simulation of 1-bit Demultiplexer

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Fig. 5.87 Layout of 14-bit Demultiplexer

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 Fig. 5.88 Waveform of post-layout simulation of 1-bit Demultiplexer

Fig. 5.89 Comparison of pre-layout and post-layout simulations of 1-bit Demultiplexer

5.11 Architecture of 14-bit Multiplexer

The Multiplexer is used for the user end. The user can see any of the three channel

outputs at any time. So, based on the user input S0 and S1, any of the three channels will
appear at the output.

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Fig. 5.90 Schematic of 1-bit Multiplexer

Fig. 5.91 Schematic of 14-bit Multiplexer

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 Fig. 5.92 Layout of 1-bit Multiplexer

Fig. 5.93 Layout of 14-bit Multiplexer

Fig. 5.94 Waveform of pre-layout of 1-bit Multiplexer

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 Fig. 5.95 Waveform of post-layout of 1-bit Multiplexer

Fig. 5.96 Comparison of pre-layout and post-layout simulations of 1-bit Multiplexer

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5.12 Architecture of 14-bit Output Register

The final digital code after conversion and De-Muxing of a sample must be stored

somewhere for the user to read. So, a 14-bit register is designed as shown in Fig. 6.89 to store
the value and pass it when needed. It is a 14-bit parallel input parallel output register designed
using edge triggered DFFs. The conversion time of a given signal is very less as compared to
sample rate. So, to reduce the power consumption, the ADC core should remain ideal for
the time there is no new sample available, after the conversion of the given sample.

Fig. 5.97 Schematic of 14-bit Output Register

Fig. 5.98 Waveform of pre-layout simulation of 14-bit Output Register

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Fig. 5.99 Layout of 14-bit Output Register

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 Fig. 5.100 Waveform of post-layout simulation of 14-bit Output Register

Fig. 5.101 Comparison of pre-layout and post-layout simulations of 14-bit Output Register

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CHAPTER 6

6.1 Validation of Multi-Channel Fully Differential SAR ADC

All the individual components of the ADC are integrated using proper placement, floor
planning and routing. This is followed by insertion of I/O pads. Then, dummy insertion is
performed, where the empty spaces of the integrated layout are filled with dummies.
Subsequently, the final DRC and antenna DRC has been performed to rectify any those antenna
issues. The complete layout is shown in Fig. 6.1. Finally, the GDS II file is generated, which is a
binary file, sent along with all DCR reports to the fab lab (SCL in this case) for fabrication.

Fig. 6.1 Complete layout of the 14-bit Multi Channel Fully Differential SAR ADC
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 The ADC core, after completion of integration, has been simulated with different input
voltages, input frequency and sampling frequency. The waveforms are as follows.

Fig. 6.2 Output waveform of 14-bit ADC with Vip=0.825 mV and Vin=0.975 mV

Fig. 6.3 Output waveform of 14-bit ADC with Vip=0. 900062V and Vin=0. 899938V

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Fig. 6.4 Reconstructed analog signal after an ideal DAC for input frequency 500Hz and sampling frequency 31.3 KHz

Specifications for quantifying ADC dynamic performance are SINAD (Signal to

Noise and Distortion Ratio), ENOB (Effective Number Of Bits), SNR (Signal to Noise Ratio),
THD (Total Harmonic Distortion), THD + N (Total Harmonic Distortion plus Noise), and SFDR
(Spurious Free Dynamic Range). There are a number of ways to quantify the distortion and
noise of an ADC. All of them are based on an FFT analysis using a generalized test setup such
as shown in Fig. 6.5. The spectral output of the FFT is a series of M/2 points in the frequency
domain (M is the size of the FFT—the number of samples stored in the buffer memory). The
spacing between the points is fs /M, and the total frequency range covered is dc to fs /2, where
f width of each frequency "bin" (sometimes called the resolution of the FFT) is fs is the
sampling rate.
Harmonic distortion is normally specified in dBc (decibels below carrier), although
in audio applications it may be specified as a percentage. It is the ratio of the RMS signal to the
RMS value of the harmonic in question. Harmonic distortion is generally specified with an
input signal near full-scale (generally 0.5 to 1 dB below full-scale to prevent clipping), but it can
be specified at any level. For signals much lower than full-scale, other distortion products due
to the differential nonlinearity (DNL) of the converter—not direct harmonics—may limit
performance.
Total harmonic distortion (THD) is the ratio of the RMS value of the fundamental

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signal to the mean value of the root-sum-square of its harmonics (generally, only the first 5
harmonics are significant). THD of an ADC is also generally specified with the input signal
close to full-scale, although it can be specified at any level.
Total harmonic distortion plus noise (THD + N) is the ratio of the RMS value of the
fundamental signal to the mean value of the root-sum-square of its harmonics plus all noise
components (excluding dc). The bandwidth over which the noise is measured must be specified.
In the case of an FFT, the bandwidth is dc to fs/2. (If the bandwidth of the measurement is dc to
f/2 (the Nyquist bandwidth), THD + N is equal to SINAD—see below). Be warned,
however, that in audio applications the measurement bandwidth may not necessarily be the
Nyquist bandwidth.
Spurious-free dynamic range (SFDR) is the ratio of the RMS value of the signal to the
RMS value of the worst spurious signal regardless of where it falls in the frequency spectrum.
The worst spur may or may not be a harmonic of the original signal. SFDR is an important
specification in communications systems because it represents the smallest value of the signal
that can be distinguished from a large interfering signal (blocker). SFDR can be specified with
respect to full- scale (dBFS) or with respect to the actual signal amplitude (dBc). The definition of
SFDR is shown graphically in Fig. 6.5.

Fig. 6.5 FFT of a reconstructed signal of ADC

Signal-to-Noise-and-Distortion (SINAD or S/(N + D)) is the ratio of the RMS

signal amplitude to the mean value of the root-sum-square (RSS) of all other spectral
components, including harmonics, but excluding dc. SINAD is a good indication of the

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overall dynamic performance of an ADC because it includes all components which make up
noise and distortion. SINAD is often plotted for various input amplitudes and frequencies. For a
given input frequency and amplitude, SINAD is equal to THD + N, provided the bandwidth for
the noise measurement is the same for both (the Nyquist bandwidth).
SINAD plots such as these are very useful in evaluating the dynamic performance of
ADCs. SINAD is often converted to effective number-of-bits (ENOB) using the relationship for
the theoretical SNR of an ideal N-bit ADC: SNR= 6.02N + 1.76 dB. The equation is solved for N,
and the value of SINAD is substituted for SNR:

Signal-to-noise ratio (SNR, or sometimes called SNR-without-harmonics) is calculated

from the FFT data the same as SINAD, except that the signal harmonics are excluded from the
calculation, leaving only the noise terms. In practice, it is only necessary to exclude the first 5
harmonics, since they dominate. The SNR plot will degrade at high input frequencies, but
generally not as rapidly as SINAD because of the exclusion of the harmonic terms.

6.2 Mathematical relationships between SINAD, SNR and THD

There is a mathematical relationship between SINAD, SNR, and THD (assuming all are
measured with the same input signal amplitude and frequency). In the following equations,
SNR, THD, and SINAD are expressed in dB, and are derived from the actual numerical
ratios S/N, S/D, and S/(N+D) as shown below:

The above three equations can be solved for the numerical ratios N/S, D/S, and (N+D)/S as
follows:

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As in the above three equations all the denominators all equal to S, the root sum square of N/S and
D/S is equal to (N+D)/S as follows:

Therefore, S/(N+D) must equal:

and hence,

6.3 Results

The core of ADC is simulated with different sampling frequency and all the quantities
have been measured in MATLAB. Variation of different quantities with the variation of input
frequency has also been measured.

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Fig. 6.6 FFT diagram of ADC with input frequency 50Hz and sampling frequency 25KSPS

Fig. 6.7 FFT diagram of ADC with input frequency 100Hz and sampling frequency 2 5KSPS

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Fig. 6.8 Comparison of performance parameter with Sampling Frequency

Fig. 6.9 Comparison of performance parameter with Input Frequency

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The following ADC parameters were measured both for schematic and layout formats:

Table 6.1 Comparison of performance parameters with the 100Hz as Input frequency with 25KSPS Sampling Rate
Characteristics Pre-layout (dB) Post-layout (dB)

SINAD 72.5 71.75

SFDR 74.65 74.18

SNDR 71.38 69.33

ENOB 11.75 11.62

-THD 72.5 71.75

The specifications of the final chip as achieved has been compared to that of the required
specifications in Table 6.2

Table 6.2 Comparison of specifications for the 14-bit ADC

Size of the Chip 2x2 mm2

Targeted Achieved

Topology Multi-Channel SAR 3 Channel Fully Differential SAR

Supply voltage 1.8 V 1.8 V

Input voltage < 1.8 V 1 V (0.5 V to -0.5V)

ENOB 12 bit 11.81 bit

SINAD 80 dB 72.91 dB (10 Hz, 1 KSPS)

SFDR 90 dB 75.05 dB (10 Hz, 1 KSPS)

SNR 74 dB 71.59 dB (10 Hz, 1 KSPS)

Input signal frequency 10 Hz – 500 Hz 0.1 Hz – 100 Hz

Sample rate 100 Hz –50 KHz 25 KSPS

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CHAPTER 7

7.1 Conclusion

With the requirement of an analog to digital converter for low frequency applications,
the above design was considered after extensive literature survey. The choice of SAR
architecture for ADC was mainly because of its low power consumption, sufficient resolution,
simple principle and it popularity in data acquisition systems. Each and every component of the
Multi-Channel Fully Differential SAR ADC has been designed as mentioned in the previous
chapter. The circuit architecture of all individual components have been fixed only after
achieving the required waveforms through repeated trials on schematic view. After finalizing the
schematic structures, their corresponding layouts were drawn followed by DRC and LVS checks.
Upon passing these checks, PEX of these layouts were simulated to generate the calibre view for
post layout simulations. Both pre-layout and post-layout simulation results were compared. If the
waveforms showed undesirable deviations from each other, then schematic designs had to be
rechecked.
After successfully passing all checks, the guard rings were attached to the individual
blocks. They were then integrated one by one and again checked for proper working. Final
integration of the complete circuit was performed accompanied by I/O pads insertion, dummy
insertion and generation of GDS II file. ADC parameters such as ENOB, SINAD, SNDR and
SFDR were measured. After the chip arrives from fabrication, it needs to be tested. So, test
equipment has to be designed for validation of the ADC.

7.2 Future Work

In the near future, the following work has to be performed:
 Testing and Validation of the ADC - On fabrication, the chip has to be tested to check
the proper operation of the ADC. For this reason, a test equipment needs to be designed
to validate the ADC.
 Integration with application – The tested and validated ADC will be further
incorporated as an integrated part of a seismic sensing/ low frequency application finally.
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