CHAPTER 1

INTRODUCTION
Oil exploration, earthquake detection, and acoustic monitoring of drilling operations are all
applications that use seismic sensing capabilities. In this chapter, a concise background about
seismic system is given. Then motivation is presented.

1.1 BACKGROUND

Seismic applications require signal conditioning of the input of a geophone, hydrophone, or other
acoustic sensor, demanding effective amplification, filtering, and digitization of the target
acoustic signal. An ideal seismic sensing system has the characteristics of good signal-to-noise
ratio, low power consumption (to allow for remote operation), programmable signal filtering to
accommodate several applications, a variable sampling rate, and cost-effectiveness. The system
input is an acoustic sensor that drives a signal conditioning circuit which in turn drives an A/D
converter.

FIG: 1. BASIC BLOCK DIAGRAM OF SEISMOLOGY STATION

1.2 SEISMIC SENSORS

OVERVIEW
Seismic sensors are devices used to measure seismic vibrations by converting ground motion into
a measurable electronic signal. As the signal is analogue in nature, sensors must be linked to a
data acquisition unit to convert its output into a digital format that can be read by computers.
Some sensors contain Smart electronics to provide the sensor type, serial number and orientation
(dip and roll) in inclined boreholes.
 FIG 1.2 Seismic sensor [www.imseismology.org]

SENSOR TYPES

Seismic sensors are classified according to what form of ground motion it measures, namely
ground velocity (geophone) or ground acceleration (accelerometer and FBA); the number of
sense axes the sensor has and whether the sensor is deployed in a borehole or against a rock
surface. Each sensor type has different advantages in terms of amplitude range, frequency range,
reliability and cost.

A seismic network can be based on any combination of geophone, accelerometer and force
balance accelerometers, in uni - and tri-axial combinations. The tri-axial configuration affords
the most accurate estimates of source parameters.

GEOPHONES

Geophones are usually the sensor of choice in most mining applications, because of the low cost,
large bandwidth and excellent reliability. We have different kinds of geophones available in the
market like some with natural frequencies of 4.5 Hz and other with 14 Hz. The 4.5 Hz geophone
has a usable frequency bandwidth of between 3 Hz and 2000 Hz but must be installed to within
two degrees of its pre-set orientation with respect to the vertical. The 14 Hz geophone is omni-
directional and can be installed at any angle, with a usable frequency bandwidth of between 8 Hz
(-3dB point) and 2000 Hz.

FIG 1.3 Geophone [www.imseismology.org]

ACCELEROMETERS

Accelerometers are usually used where precision records of smaller (high-frequency) seismic
events are required. Some companies like IMS routinely manufactures two kinds of
accelerometers: a 2.3 kHz low-noise version with useful bandwidth between 0.7 and 2,300 Hz,
and a 25 kHz high-frequency version with useful bandwidth between 2 and 25,000 Hz.

1.2 BASIC PARAMETERS OF DATA CONVERTERS

1.2.1 INPUT VOLTAGE RANGE:

The input voltage range of an ADC is determined by the reference voltage (VREF) applied to the
ADC. A reference voltage can be either internal voltage or external voltage by applying a voltage
on an external pin of the microcontroller. Generally reference voltage can be selected by
configuring the corresponding register’s bit field of the microcontroller. ADC will saturate with a
analog voltage higher than the reference voltage, so the designer must make sure that the analog
input voltage does not exceed the reference voltage[6]. The input voltage range is also called as
conversion range.

1.2.2 RESOLUTION:
The entire input voltage range (from 0V to VREF) is divided into a number of sub-ranges. Each
sub range is assigned a single output digital code. A sub range is also called LSB (least
significant bits) and the number of sub ranges is usually in powers of two. The total number of
sub ranges is called the resolution of the ADC. For an example, an ADC with eight LSBs has the
resolution of three bits (2 = 8). If an ADC’s resolution is three bits then it also means that the
code width of the output is three bits.

= (1.1)

(n = number of bits)
1.2.3 QUANTIZATION:

The LSB is determined if input analog voltage lies in the lowest sub-range of the input voltage
range. For example, consider an ADC with VREF as 2V and resolution as three bits. Now the 2V
is divided into eight sub-ranges, so the LSB voltage is within 250mV. Now an input voltage of
0V as well as 250mV is assigned to the same output digital code 000. This process is called as
quantization.

1.2.4 SIGNAL TO NOISE RATIO (SNR):

SNR is defined as the ratio of the output signal voltage level to the output noise level. It is
usually represented in decibels (dBs) and calculated with the following formula.

()*+ ,-. /0#

!"# = 20log # (1.2)
()*+ 1-,2#

1.2.5 TOTAL HARMONIC DISTORTION (THD) :

Whenever an input signal of a particular frequency passes through a non-linear device, additional
content is added at the harmonics of the original frequency. For example, assume an input signal
having frequency f. Then the harmonic frequencies are 2f, 3f, 4f, etc. So non-linearity in the
converter will produce harmonics that were not present in the original signal. These harmonic
frequencies usually distort the output which degrades the performance of the system. This effect
can be measured using the term called total harmonic distortion (THD). THD is defined as the
ratio of the sum of powers of the harmonic frequency components to the power of the
fundamental/original frequency component. In terms of RMS voltage, the THD is given by,

6(77 8(97 8…8( 7

345 = (1.3)
(;

1.2.6 EFFECTIVE NUMBER OF BITS (ENOB):

Effective number of bits (ENOB) is the number of bits with which the ADC behaves like a
perfect ADC. It is another way of representing the signal to noise ratio and distortion (SINAD)
and is given below:

>[email protected]
< =" = (1.4)
G.H

1.2.7 SAMPLE AND HOLD TIME:

Usually after giving a trigger to an ADC to start a conversion, it take some time (in clock cycles)
to charge the internal capacitor to a stable value so that the conversion result is accurate. This
time is called as sample time. This time must be considered carefully especially when multiple
channels are used during conversion. In such case there is a minimum time (in clock cycles)
needed to guarantee the best converted value between two ADC channel switching. After the
sampling time, the number of clock cycles it takes to convert the charge or the voltage across the
internal sampling capacitor into corresponding digital code is called the hold time.

1.2.8 SETTLING TIME:

When using multiple channels, there may be cases in which each channel may have different
gain and offset configurations. Switching between these channels requires some amount of time,
before beginning the sample and hold phase, in order to have good results. Especially care should
be taken when switching between differential channels. Once a differential channel is selected,
the ADC should wait for some amount of time for some of the analog circuits (for example the
automatic offset cancellation circuitry) to stabilize to the new value. This time is called as
settling time. So ADC conversion should not be started before this time. Doing so will produce
an erroneous output. The same settling time should be observed for the first differential
conversion after changing the ADC reference.

1.2.9 CONVERSION TIME:

Conversion time is the combination of the sampling time and the hold time, usually represented
in number of clock cycles. The conversion time is the main parameter in deciding the speed of
the ADC. Also the startup time, sample and hold time and the settling time are all software
configurable in ADC’s of some high end microcontrollers.
1.3 ERRORS ASSOSIATED WITH ADC

1.3.1. OFFSET ERROR:

The offset error is defined as the deviation of the actual ADC’s transfer function from the perfect
ADC’s transfer function at the point of zero to the transition measured in the LSB bit.

When the transition from output value 0 to 1 does not occur at an input value of 0.5LSB, then we
say that there is an offset error. With positive offset errors, the output value is larger than 0 when
the input voltage is less than 0.5LSB from below. With negative offset errors, the input value is
larger than 0.5LSB when the first output value transition occurs. In other words, if the actual
transfer function lies below the ideal line, there is a negative offset and vice versa.

The figure shows the transfer function of an ADC with positive offset error .

FIG. 1.4 OFFSET ERROR

1.3.2. GAIN ERROR:

The gain error is defined as the deviation of the last step’s midpoint of the actual ADC from the
last step’s midpoint of the ideal ADC, after compensated for offset error.

After compensating for offset errors, applying an input voltage of 0 always give an output value
of 0. However, gain errors cause the actual transfer function slope to deviate from the ideal slope.
This gain error can be measured and compensated for by scaling the output values.
1.3.3. FULL SCALE ERROR:

Full scale error is the deviation of the last transition (full scale transition) of the actual ADC from
the last transition of the perfect ADC, measured in LSB or volts. Full scale error is due to both
gain and offset errors.

FIG: 1.5. FULL SCALE ERROR

1.3.4 DIFFERENTIAL NON LINEARITY:

Differential non-linearity (DNL) is defined as the maximum and minimum difference in the step
width between actual transfer function and the perfect transfer function.

Non-linearity produces quantization steps with varying widths, some narrower and some wider.
 FIG: 1.6. DIFFERENTIAL NON-LINEARITY (DNL).

1.3.5. MISSING CODE

In the example below, the first code transition (from 000 to 001) is caused by an input change of
250mV. This is exactly as it should be. The second transition, from 001 to 010, has an input
change that is 1.25LSB, so is too large by 0.25LSB. The input change for the third transition is
exactly the right size. The digital output remains constant when the input voltage changes from
1000mV to 1500mV and the code 100 can never appear at the output. It is missing. the higher the
resolution of the ADC is, the less severity the missing code is.
1.4 MOTIVATION
The seismic sensor collects a lot of data in very short duration and these data are analog in
nature. This work goes on continuously. So we need an efficient A/D converter for our system.
Here we choose SAR ADC as A/D converter as SAR ADCs are low power consumption, high
resolution and accuracy, and a small form factor. Because of these benefits, SAR ADCs can
often be integrated with other larger functions.

1.5 SUMMARY
In Chapter 2 Specifications, the specifications of the 14-bit ADC are elaborated, taking into
account neighboring blocks. Chapter 3 ADC Architectures lists and briefly explains all ADC
architectures proposed to date and shows that the Switched-Capacitor SAR-type ADC best meets
the specifications. Chapters 4 Comparator, Chapters 5 DAC using Split capacitor array, Chapters
6 SAR logic, Chapters 7 Edge trigger clock design and output register design Chapters 8
Timing and Control design describe in detail the generation of different signals used in ADC
core. In Chapter 9 Validation of the ADC core transient simulation results of the entire ADC
core, validating its correct operation, are presented; which allow to determine the SFDR, SNDR
and ENOB of the ADC core. Chapter 10 Conclusion summarizes the achievements of the
presented work, explains future work and gives various ideas to further improve the presented
design
 CHAPTER 2

SPECIFICATIONS
2. ELABORATION OF SPECIFICATIONS
For accurate, high-quality signal conversion, we require a resolution of 14 bits. The 14-bit must
convert 3 electrodes or channel. Each electrode or channel needs to be converted at a
rate of 12KSPS . The spectrum of electrophysiological signal is limited to B=100Hz. The
corresponding Nyquist frequency is f Nyquist = 2B = 200Hz. By choosing 1kHz as
sampling rate for 3 channels oversampling with an oversampling factor of 1.67 is
performed. . Choosing 1kHz rather than the minimum o f 6 0 0 Hz brings the following
advantages:
- The requirements for the anti-aliasing filter are relaxed, easing its design
- Performing oversampling reduces noise
The analog input range of the 14-bit ADC is [109uV, 1V]. Assuming an Comparator gain of
86dB full analog input range is used.
The ADC will work on voltage signals, and neither on current, nor on charge signals. The length
and width of the ADC is not specified. As most implantable chips are battery-powered , Low
Power ADC is required.
The ADC must have a Differential Non-Linearity smaller than 1 ( DNL < 1 ) and an Integral
Non- Linearity smaller than 1.5 ( INL < 1.5 ).
Table 2-1 Summarizes the elaborated specifications for the 14-bit ADC.

ADC Specifications

Topology SAR

Technology 180nm SCL

Supply voltage: 1.8 V

Resolution: 14 bit

ENOB: 12 bit

Permissible Noise: <109 µV p-p

SAR clock 200 KHz

Vin 0 - 1.0 V

LSB: 109 µV

Sample rate: ~500 Hz

Dynamic Range: 86 dB
 CHAPTER 3

ADC ARCHITECTURES
3.1. ADC ARCHITECTURES IN COMPARISON
A large variety of ADC architectures have been proposed to this day. They can be classified as
follows [Kester2005-1]. (Architectures shown in gray cannot be implemented as CMOS
integrated circuits; they are here to complete the list.)
• Comparator (1-bit ADC)
• High Speed ADC Architectures
- Flash Converters (sometimes called parallel ADCs)
- Successive Approximation ADCs
- Subranging, Error Corrected, and Pipelined ADCs
- Serial Bit-Per-Stage Binary and Gray Coded (Folding) ADCs
• Counting and Integrating ADC Architectures
- Charge Run-Down ADC
- Ramp Run-Up ADC
- Tracking ADC
- Voltage-to-Frequency Converters (VFCs) combined with Frequency Counter
- Dual Slope/ Multislope ADCs
- Optical Converters
• Sigma-Delta ADC
Figure 3-1 compares integrated circuit ADC architectures in terms of resolution and bandwidth.
The attentive reader will see which resolution and frequency range are attainable with each of
the architectures.

FIG: 3.1 ADC architectures in comparison [Pelgrom2007]

The following paragraphs discuss briefly the various ADC architectures and their
compatibility with the specifications elaborated in Chapter 2.
Flash ADC
Flash ADCs (sometimes called parallel ADCs) are the fastest type of ADC, but have limited
resolution, high power dissipation and relatively large chip size.

Successive Approximation ADC

“The successive approximation ADC is by far the most popular architecture for data-
acquisition applications, especially when multiple channels require input multiplexing. […]
The overall accuracy and linearity of the SAR ADC are determined primarily by the internal
DAC’s characteristics. […] Switched-capacitor (or charge-redistribution) DACs have become
popular in newer CMOS-based SAR ADCs, as their accuracy and linearity are primarily
determined by high-accuracy photolithography.” [Kester2005-2].
As SAR ADCs do not have latency, they outperform Pipelined and Sigma-Delta ADCs in the
case of single-shot measurements or repeated ADC power-up and -down cycles. Remember the
14-bit ADC is powered up for high-accuracy data conversion as soon as activities are observed
in a specific area, then powered down again.
The challenge is to build a capacitor array that is at least 14-bit accurate, which should be
possible in SCL 0.18µm CMOS technology, as a 12-bit accurate capacitor array has already
been realized in a 0.6µm CMOS process, using a special common centroid layout technique
[Promitzer2001]. If a 14-bit accuracy is not achieved, calibration in the digital or analog domain
can be performed. However, the aim is to build a non-calibrating ADC, as calibration would
add a lot of extra circuitry, including a memory. Consequently, the ADC would consume much
more area. Calibration would also introduce a delay at each ADC start-up.

Subranging ADC

Subranging ADCs split the A/D conversion in several steps. For example, an N-bit conversion
could be split into a coarse N1-bit conversion and a fine N2-bit conversion, where N1+N2=N.
Each sub- conversion is carried out in a separate stage. Each stage will work on the residue
signal (error signal) of the previous stage. Residue signals are amplified to match the input
range of the next stage. Subranging ADCs always include operational amplifiers.

Subranging ADCs can be pipelined. In a pipelined subranging ADC, all stages work
simultaneously on different samples.

A stage can be repeated in time instead of space. In a cyclic/algorithmic/recirculating ADC, the

residue signal is amplified and fed back to the same stage several times.

Pipelined ADC

Pipelined ADCs are used for high-frequency applications. The critical delay time of each
stage diminishes, as it performs only a part of the conversion, which allows increasing the
frequency. However, to convert a sample, its residue signal needs to propagate through the
whole line of stages, which introduces the famous pipeline delay or latency. Due to latency, the
pipelined ADC architecture is not appropriate for single-shot operation or repeated ADC start-
up and shut-down cycles. However, a pipelined ADC is well suited for continuous data
conversion.

Cyclic/Algorithmic /Recirculating ADC

Different authors use different terminology to refer to the same idea: the residue signal is
recirculated several times through a single stage. Rudy van de Plassche refers to it as Cyclic or
Algorithmic [Plassche2003], while Walt Kester refers to it as Recirculating [Kester2005-1].
This architecture can be adopted to achieve small area in applications where speed is not
critical. Cyclic ADCs necessitate an operational amplifier.

Folding ADC

Folding ADCs have limited resolution, in general lower than 10 bits

[Pelgrom2007].

Sigma-Delta ADC

The Sigma-Delta ADC architecture is one of the most popular high-resolution medium-to-low-
speed ADC architectures in use today. The Sigma-Delta ADC architecture is typically used in
applications requiring resolutions from 12 to 24 bits [Kester2005-2]. A Sigma-Delta ADC
contains very simple analog electronics (a comparator, voltage reference, a switch and one or
more integrators and analog summing circuits), and quite complex digital computational
circuitry [Kester2005-1]. Thus, requirements placed on the analog circuitry are relaxed at the
expense of more complicated digital circuitry, which becomes a more desirable trade-off for
modern submicron technologies [Johns1997].

High resolution, together with on-chip programmable-gain amplifiers (PGAs) allows

direct digitization of small output voltages of sensors, requiring no instrumentation amplifier.
Sigma-Delta ADCs offer therefore an attractive alternative to traditional approaches using
an instrumentation amplifier and a SAR ADC [Kester2005-2].

Sigma-Delta ADCs contain as building blocks a digital filter and decimator. The digital filter
does introduce inherent pipeline delay. Consequently, the Sigma-Delta ADC cannot be operated
in a single- shot or burst mode [Kester2005-2].

Conclusion

In conclusion, any of Counting, Successive Approximation, Pipelined 1 or Sigma-

Delta ADC architectures could be used for converting 3 channels with 14-bit resolution. The
Folding and Flash ADC architectures are not taken into consideration because they hardly
reach 14-bit resolution. The Counting ADC architecture can be excluded also because it
would require large no. of ADCs operating in parallel, which means an excessively big silicon
area.

From the remaining Successive Approximation, Pipeline and Sigma-Delta ADC

architectures, none has an obvious advantage at first sight. However, the Successive
Approximation ADC architecture has been used extensively in multiplexed data acquisition
systems which is our application. Due to its popularity, the Pipelined ADC is taken as
representative of all Subranging ADCs.

Sigma-Delta ADC architecture is typical for precision industrial measurement as well as

voiceband and audio applications. Finally, the pipelined ADC architecture is most convenient
for high-speed applications like instrumentation, video, radar, communications and
consumer electronics [Kester2005-2]. Resolution versus sampling rate is displayed in Figure
3-2 for the three remaining ADC architectures, along with their typical applications. Section
3.2 lists further arguments in favor of the Successive Approximation ADC architecture.

FIG: 3.2 ADC architectures, applications, resolution and sampling rates. The dashed line was
the state of the art in 2005 [Kester2005-2]

3.2. Advantages of the SAR ADC

- Very simple principle. SAR ADCs implement the binary search algorithm.

- Low power consumption. A SAR ADC does not contain an operational amplifier;
operational amplifiers are generally power-hungry. The SAR ADC contains solely a
comparator; comparators consume much less power than operational amplifiers. Pipelined
and Sigma- Delta ADCs contain power-hungry operational amplifiers. From SAR, Pipelined
and Sigma- Delta ADCs, the SAR ADC is most likely low-power.
- No pipeline delay (latency). In a pipelined ADC, the pipeline delay is a multiple of
the sampling clock period. For low sampling frequencies, there will be a considerable
latency. The SAR ADC can use an internal clock that is independent of (and – if desired – much
faster than) the sampling clock; output codes can thus be delivered with a delay negligible with
respect to sampling clock period. Closing the loop requires that ADC and DAC has no latency,
a further argument in favor of the SAR ADC.

3.3. Switched-Capacitor or Charge-Redistribution SAR ADC

A SAR ADC has the following building blocks:

- Sample-and-Hold Stage (S/H)
- Digital-to-Analog Converter (DAC)
- Comparator
- Successive Approximation Register (SAR)

Figure 3-3 shows the basic SAR ADC.

 FIG: 3.3 Basic SAR ADC with S/H stage, DAC, Comparator and SAR
[Kester2005-1]

SAR ADCs can be classified according to the DAC they use. The Charge-Redistribution or
Switched- Capacitor (SC) SAR ADC is by far the most popular one. It combines the S/H stage
and the DAC in a single building block, a switched-capacitor array. Figure 3-4 shows a 3-bit
SC SAR ADC with its binary-weighted parallel capacitor array.

FIG: 3.4 3-bit SC SAR ADC with single-ended analog path [Kester2005-1]. The
capacitor array serves as DAC and S/H stage at the same time. The SAR control logic, which
is not shown here, controls the switches and takes the comparator’s response as input.
SAR ADC DESIGN

CHAPTER 4

COMPARATOR
4. COMPARATOR
Each A/D Converter contains at least one comparator. A comparator itself can be considered a
1-bit A/D Converter. In the presented ADC design, the comparator plays a key role; it must
be able to discriminate voltages as small as 109µV.

The heart of every A/D converter is its comparator. In a successive approximation A/D converter
the comparator is used to make every decision to keep or reject a bit. As a result, every salient dc
and ac accuracy specification hinges on the performance of the comparator[1]. In some sorts of
ADCs such as flash ADC, the comparator has a great impact on the performance of the whole
ADC. However, in some cases the error produced by the comparator can be compensated in the
followed digital processing block. A comparator generates a logic output high or low based on
the comparison of the analog input with a reference voltage. In an ideal comparator, with infinite
gain, for input voltages higher than the reference voltage, the comparator outputs logical one and
for the input voltages lower than the reference voltage it produces zero at the output.
However, in reality due to finite gain, comparator results in one when Vin > Vref + VIH , and is
set to zero when Vin < Vref + VIL .
Speed, accuracy, low power consumption and wide input common mode range are some design
considerations for comparators, which define performance metrics of a comparator.

4.1. SPECIFICATIONS

Where comparators are incorporated into IC ADCs, their design must consider:
- Offset voltage
- Resolution
- Speed
- Bias current
- Power dissipation
- Area
- Metastability [Kester2005-1]

A critical specification is the offset voltage. In fact differential amplifiers, as used here have an
offset voltage of 1mV to 10mV if they are realized in CMOS technology [Makinwa2002].
Differential amplifiers realized in bipolar technology have an offset voltage of approximately
0.1 mV [Makinwa2002]. In practice offset voltage after performing dynamic offset cancellation
comes down to 10uV [Makinwa2002].

As discussed the response time of the comparator must be smaller than 1us. The power
dissipation is proportional to the bias current. Neither power dissipation, nor bias current is
rigorously specified. Nevertheless, efforts will be made to minimize both quantities. Of

16
SAR ADC DESIGN

course, also the area will be kept as small as possible.

Metastability is the ability of a comparator to balance right at its threshold for a short period of
time or in other words its occasional inability to resolve a small differential input into a
valid output logic level [Kester2005-1]. Anyhow, metastability is an important design issue
for high speed ADCs like the Flash type, but not for this kind of low-speed SAR-type ADC.

Table 4.1 summarizes the main specifications of the comparator.

Specification Value
Offset voltage VOS < 0.5VLSB = 55µV
Resolution (∆VIN ) < 0.5VLSB = 55µV
Response time < 1us

Table 4.1 Main specifications of comparator

4.2. Architecture
The comparator consists of a differential pair and a common source stage, as shown in Figure
4.1. The amplifier, which has an optimized noise performance, senses the minimum input voltage
of 109uV. It has got pre-layout gain of 84dB. That is what we need to sense the minimum
voltage specified.

17
SAR ADC DESIGN

IMPLEMENTATION OF COMPARATOR

FIG.4.1: COMPARATOR SCHEMATIC

4.2.1. Design approach

The topologies which a designer chooses are very much dependent upon the type of application
he or she is looking for. However it may also depend on some particular advantages and
disadvantages of a particular topology. Here we have chosen simple differential pair amplifier
(high noise immune) for input amplifier A1, common source amplifier (high gain) for output
amplifier A2, a current mirror circuit (free from voltage sources; utilizing single current
reference source) as a biasing circuit.
For best performance, keep all transistors in saturation. M4 is the only transistor that cannot be
forced into saturation by internal connections or external voltages. Therefore, we develop
conditions to force M0 to be in saturation.

18
SAR ADC DESIGN

Table 4.2: Aspect Ratio of transistors

M0, M1, M2 10
M3, M6 15
M5, M7 2
M4 1

Common Centroid method is followed while making the layout of the above schematic. It helps
in routing between different nodes and makes the layout compact hence decreasing the chip area.
The layout design of the comparator is shown in figure 4.2.

FIG: 4.2 Layout of Comparator designed using common centroid methodology.

4.2.2. Pre-layout simulation results

The comparator was simulated with VDD= 1.8 V, clock frequency= 100 kHz, input frequency =
5 kHz with full swing, and temperature = 27ºC. The comparator operation is shown in Figure
4.3.

19
SAR ADC DESIGN

FIG: 4.3 Comparator is simulated with a sin wave of 5kHz frequency.

FIG: 4.4 COMPARATOR’S GAIN BANDWIDTH PLOT

4.2.3. Post-layout simulation results

After layout the gain of the comparator is increased due to parasitic capacitance and the
bandwidth is reduced but the gain bandwidth product remains almost same. So for a given
bandwidth we still get the same gain. Comparator post-layout gain bandwidth plot is shown in
figure 4.4.

FIG: 4.5 POST LAYOUT COMPARATOR’S GAIN BANDWIDTH PLOT

20
SAR ADC DESIGN

Table 4.3 Summarizes Pre-layout, all process corner Gain and Bandwidth of the comparator.

Process Corner Gain (dB) Bandwidth (kHz)

tt 84.31 131.86
sf 82.34 154.17
fs 84.91 98.17
ss 84.75 136.77
ff 81.19 161.00

Table 4.4 Summarizes Post-layout, all process corner Gain and Bandwidth of the comparator.

Process Corner Gain (dB) Bandwidth (kHz)

tt 102.85 20.32
sf 97.48 33.97
fs 102.35 20.00
ss 102.56 22.90
ff 94.01 38.49

21
SAR ADC DESIGN

CHAPTER 5

DIGITAL TO ANALOG CONVERTER

5.1. DIGITAL TO ANALOG CONVERTERS

This section examines the digital-to-analog conversion aspect. The input to the DAC is a digital
word consisting of parallel binary signals that are generated from Successive Approximation
Register.
The factors that determine the speed of the DAC are the parasitic capacitors and the gain
bandwidth and slew rate of opamp, if they are used.
Different DAC architectures are:-
1. Nyquist DAC architectures:
For example:
a) Binary-weighted DAC
b) Unit-element (or thermometer-coded) DAC
c) Segmented DAC
d) Resistor-string, current-steering, charge-redistribution DACs
2. Oversampling DAC:
a) Oversampling performed in digital domain (zero stuffing)
b) Digital noise shaping (Σ∆ modulator)
c) 1-bit DAC can be used
d) Analog reconstruction/smoothing filter
We are not going to use Resistor string DAC as it takes a lot area. So we are going to use binary
weighted DAC in its modified form in two split capacitor form and if required then Thermometer
coded DAC[4][8].
Basic structure of Binary weighted DAC and 14-bit DAC with unit value bridge capacitor are
shown in figure 5.1 and 5.2.

22
SAR ADC DESIGN

FIG: 5.1 BINARY WEIGHTED CAPACITIVE ARRAY DAC[4]

BINARY-WEIGHTED CAPACITOR ARRAY VS SERIES CAPACITANCE SPLIT

ARRAY METHOD:

The linearity of ADC is restricted by the linearity of the DAC which is caused by the capacitor
mismatch. Therefore, choosing an appropriate value for the unit capacitance is vital. Reducing
the unit capacitance value improves the linearity but deteriorates the noise performance at the
same time due to thermal noise. The minimum value of the unit capacitor is limited by several
factors including thermal noise, capacitor matching and the value of the parasitic capacitances.

By conventional method the area required is also very large. The series capacitance split array
method employed as it reduced the total area of the capacitors required for high resolution
DACs. A 14-bit regular binary array structure requires 8192 unit capacitors (Cs) while the split
array needs 128 unit Cs. These results in the reduction of the total capacitance and power
consumption of the series split array architectures as to regular binary-weighted structures.

5.2 SPLIT CAPACITOR ARRAY

A common implementation of SC SAR ADCs uses a binary-weighted capacitor array. For

binary- weighted capacitor arrays, however, area and power increase exponentially with
resolution. In fact, n- bit resolution requires 2 unit capacitors.

Split capacitor arrays as well as C-2C ladders reduce the total capacitance, thereby reducing
area and power. However, the parasitic bottom-plate capacitance of series capacitors affects the
linearity of the ADC. If the ratio of bottom-plate capacitance over nominal capacitance is
precisely known, this non- linearity problem can be dealt with during the design phase by
scaling some of the unit capacitors [Cong2001, Cong2000]. Another approach consists in

23
SAR ADC DESIGN

shielding the series capacitors.

SCL 0.18µm CMOS technology comes with a Metal Insulator Metal Capacitor (MIM Cap)
module. For a lower bottom-plate parasitic capacitance, the MIM module can be inserted
between the second- last and last (top) metal layers. A MIM capacitor is then built as parallel
plate capacitor with M4 and the MIM layer. A SCL MIM capacitor characterization report
gives following MIM capacitance values.

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SAR ADC DESIGN

FIG: 5.2 Binary weighted Split Array Capacitor DAC structure

After many considerations like kT/C noise, capacitor matching and timing a unit Capacitor of
capacitance I = 300KL is chosen. SCL MIM Capacitor module calculates capacitance of 17.76fF for
L=W= 4. Capacitor per square micron = 1fF. Maximum length of the capacitor module is 30 while the
maximum width is 10F . Maximum capacitance that can be designed in SCL MIM Capacitor module is
302.2nF.

14 parallel capacitors are switched from ground to the reference voltage and eventually back to ground
during a conversion. However, an additional parallel capacitor C equal to the unit capacitor needs to be
inserted to divide the reference voltage by exactly two at each successive bit cycling step [Martin1997].
Also a split capacitor of value 1.007874 times the unit capacitor needs to be inserted in between so that
the maximum value of capacitance required reduces to 2F rather than 2D earlier. A purely binary-
weighted capacitor array without a series capacitor can clearly not be used, due to excessively large
area, power consumption and cost. Splitting the purely binary-weighted capacitor array in two parts of
approximately equal total capacitance leads to the arrangement show in Figure 5.2. Going on splitting up
binary-weighted capacitor arrays results in the so-called C-2C ladder as shown in the following figures.

Figure 5.3 Two sub binary-weighted capacitor arrays, one series capacitor
(2bw1Cs)

Figure 5.4 Three sub binary-weighted capacitor arrays, two series capacitors
(3bw2Cs)

Figure 5.5 Four sub binary-weighted capacitor arrays, three series capacitors
(4bw3Cs)

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SAR ADC DESIGN

Figure 5.6 C-2C ladder

As primary design criterion to choose one out of the many possible capacitor arrangements, we
look at how capacitor mismatch affects the DACs accuracy. Area is considered the second most
important decision criterion. Here we choose binary weighted split array capacitor for our
design. The calculation for Split capacitor value is done for 4bit and is shown in figure 5.7.

If only MSB bit is high and rest all bits are low then equivalent capacitance for 4 bit as shown in
NO∗O,Q0-R
figure 5.7 will be + I = 2I.
NO8O,Q0-R

N
Calculating we get I = I . If we generalize it then the value of split capacitor can be
T
7
written as I = T I.
7 CD

FIG: 5.7. 4bit Split Capacitor array

At the first step of a D/A conversion, all the capacitors except the MSB capacitor C1 are
connected to ground, while C1 is connected to the positive reference voltage U V = 1.8U .
The same situation occurs in the ADC core if a zero input signal is converted. Ideally, if there was
no capacitor mismatch then UW = U V /2 = 900ZU . Due to capacitor mismatch the node voltage will
change with some variation. In fact it is assumed that all the capacitors are built from unit
capacitors, which follow a Gaussian distribution. Of course, the MSB capacitor is the biggest
capacitor built from the highest number of unit capacitors and can consequently have the
highest absolute uncertainty. Having the highest absolute uncertainty, it affects the capacitance
voltage division the most. ]: “The maximum error voltage occurs at the switch combination
1000…0, i.e. MSB equal to 1 and all other bits equal to 0.” A similar statement is mad in
[Bechen2006]: “The MSB capacitor has the most deleterious effect on the signal-to-noise and
distortion ratio (SNDR).”
The unit capacitors deviate from their nominal value due to mismatch. It is assumed that they
follow a Gaussian distribution characterized by a mean value and standard deviation.

26
SAR ADC DESIGN

5.2.1. Unit capacitor sizing

The unit capacitor sizing must consider [3/I noise, 14-bit accurate matching, timing and
power consumption. Of course, to decrease power consumption and increase speed, the unit
capacitor should be as small as possible. On the other hand, to improve MIM capacitor
matching, noise immunity and consequently the ADC’s accuracy, the unit capacitor must be as
big as possible. The design approach chosen here gives priority to accuracy. Indeed, the
minimum unit capacitor size, dictated by either [3/I noise or capacitor matching, is
determined first. It is then shown that timing requirements are met with the found unit
capacitance value and that the power consumption is reasonably small. For our design the unit
capacitor is equal to capacitance of 300fF.

5.2.2. Switch design

Switch is used to change the value from reference voltage to ground on capacitor plates. Here
two inverters back to back is used as switch with proper sizing of the PMOS and NMOS. The
schematic design of the switch is shown in figure 5.8.

FIG: 5.8. Schematic design of switch

5.2.3 Layout of capacitor array

The binary-weighted capacitor array is built from unit capacitors. To reach good capacitor
matching properties, a common-centroid layout technique is used. A sophisticated wiring
scheme leads to binary-weighted parasitic capacitances. Not only are binary weighted the
nominal capacitors, but so are their parasitic interconnection capacitances.
Layout of Capacitor array without switch, switch and full DAC layout is shown in figure 5.9,
5.10 and 5.11.

FIG: 5.9. Layout design of 14bit Capacitor array

FIG: 5.10 Layout design of switch array

FIG: 5.11 Layout design of complete DAC

5.2.4. Simulation Results for DAC

The DAC is simulated with input digital code 10 0000 0000 0000 and reference voltage of 1.8V.

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SAR ADC DESIGN

The analog output obtained is equal to 900.08mV. So it has got error of 80uV right now which is
less than the LSB=109uV. Hence it produces the desired output. The simulated graph is shown in
figure 5.12.

FIG: 5.12 DAC simulated with digital code 10 0000 0000 0000.

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SAR ADC DESIGN

CHAPTER 6

SAR CONTROL LOGIC

6. SAR control logic

The Successive Approximation Register (SAR) sets the switches – as a function of the current
state of the conversion and the comparator’s response – and stores the digital output code to
be issued at the end of the conversion. The main building blocks of the SAR control logic are:
- 14-counter
- Combinational network
- Output registers

6.1. OPERATING PRINCIPLE OF SAR ADC

SAR ADC employs a successive approximation algorithm to convert analog input to a digital
code successively. In other words, one bit is determined in each clock cycle using binary search
algorithm.

In order to investigate the operation of the SAR ADC, consider a 4 bit ADC. As shown in
Figure, in the first clock cycle DAC voltage is set to half of Vref by setting the code to 1000,
then the input voltage is compared to Vref /2 and based on the comparison result, MSB is
defined. If Vin >Vref /2 the MSB will not be changed and will remain at one, otherwise the
MSB is reset to zero. So here MSB (D3) remains at one. In the next clock cycle the DAC input is
set to 1100 and again Vin is compared to 3/4Vref . D2 retains its value since Vin>3/4Vref .
For the next bit the DAC input is set to 1110. Based on comparison, D1 is reset to zero since
Vin< 7/8 Vref and finally for defining LSB, the DAC input is set to 1101. D0 is one because
Vin> 13/16 Vref .Thus the analog input is converted to the digital code 1101 in four clock
cycles[5].

Successive Approximation Register (SAR) control logic determines each bit successively. The
SA register contains N bit for an N-bit ADC. There are 3 possibilities for each bit, it can be set to
‘1’, reset to ‘0’ or keeps its value.

In the first step, MSB is set to ‘1’ and other bits are reset to ‘0’, the digital word is converted to
the analog value through DAC. The analog signal at the output of the DAC is inserted to the
input of the comparator and is compared to the sampled input. Based on the comparator result,
the SAR controller defines the MSB value. If the input is higher than the output of the DAC, the
MSB remains at ‘1’, otherwise it is reset to ‘0’. The rest of bits are determined in the same
manner. In the last cycle, the converted digital word is stored. Therefore, an N-bit SAR ADC
takes N+2 clock cycles to perform a conversion.

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SAR ADC DESIGN

6.1.1 SAR LOGIC

SAR architecture shown in Figure 7.1 is presented in and is commonly used in SAR ADCs due
to its straightforward design technique. This control logic encompasses a ring counter and a code
register. The ring counter is in fact a shift register.

For each conversion, in clock cycle 0, the EOC signal is high and all Flip Flops outputs are reset
to zero, and for the rest of cycles EOC is low. In the next clock cycle, the most significant Flip
Flop is set to one which corresponds to MSB of the digital word to the DAC. Then the counter
shifts ‘1’ through the Flip Flops from MSB to LSB.

In each clock cycle, one of the outputs in the ring counter sets a Flip Flop in the code register.
The output of this Flip Flop which is set by the ring counter is used as the clock signal for the
previous Flip Flop. At rising edge of the clock, this Flip Flop loads the result from the
comparator. Figure shows the transient response. At the end of each conversion, EOC signal
turns to high. This type of SAR logic, converts each sample in 16 clock cycles.

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SAR ADC DESIGN

FIG: 6.1. SAR BLOCK DIAGRAM WITH FLIP FLOPS

The Flip Flops which are employed in this structure are set-reset D-FFs. For low power purpose,
transmission gate based Flip Flops are used [7]. Minimum size transistors with double length are

31
SAR ADC DESIGN

chosen for improving the power performance. The layout of SAR block is optimized with respect
to area and is designed as shown in figure 6.2.

FIG: 6.2. Layout design of SAR block

TABLE: 6.1 SAR LOGIC IMPLEMENTATION

Cycl Sample D D D D D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Comp

e 13 12 11 10
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 a13
2 0 a13 1 0 0 0 0 0 0 0 0 0 0 0 0 a12
3 0 a13 a12 1 0 0 0 0 0 0 0 0 0 0 0 a11
4 0 a13 a12 a11 1 0 0 0 0 0 0 0 0 0 0 a10
5 0 a13 a12 a11 a10 1 0 0 0 0 0 0 0 0 0 a9
6 0 a13 a12 a11 a10 a9 1 0 0 0 0 0 0 0 0 a8
7 0 a13 a12 a11 a10 a9 a8 1 0 0 0 0 0 0 0 a7
8 0 a13 a12 a11 a10 a9 a8 a7 1 0 0 0 0 0 0 a6
9 0 a13 a12 a11 a10 a9 a8 a7 a6 1 0 0 0 0 0 a5
10 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 1 0 0 0 0 a4
11 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 1 0 0 0 a3
12 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 1 0 0 a2

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SAR ADC DESIGN

13 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 1 0 a1

14 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 1 a0
15 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 -----

6.1.2. NAND GATE

The NAND gates used for making different circuit components are designed according to the
value of load it is driving. We have done DC analysis of an inverter to find the ratio of widths of
\Q
PMOS and NMOS. The results give us the value of = 3…….(6.1) For example we want to
\
design a NAND gate with load of 6 micron unit. So first we will resize an inverter and then
taking that inverter as a reference we will resize NAND gate. We have ] + ] = 6 …….(6.2)

Solving both the equations we get 4] = 6.

This implies that ] = 1.5 and hence ] = 4.5 . Now considering 4 Fan-out for any circuit the
sizes reduces to 4 times i.e. ] = 0.375 and ] = 1.125.

These are the sizes for an inverter. For NAND since two NMOS are in series so the width of
NMOS will be multiplied with a factor of 2. Finally the width of PMOS for the above NAND
gate is 1.125 micron and the width of NMOS for the same NAND gate is 0.75 micron for two
input NAND gate.

The layout for standard gates used in design have been done in SCL library using Caliber from
Mentor Graphics.

The layout diagram of a NAND gate is shown in figure 6.3.

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SAR ADC DESIGN

FIG: 6.3. OPTIMIZED LAYOUT OF A NAND GATE WITH THREE INPUTS

34
SAR ADC DESIGN

6.1.3. D Flip Flop

The Flip Flops which are employed in this structure are set-reset D-FFs. For holding the value
and edge triggered clock supply, NAND gate based Flip Flops are used. Minimum size
transistors with double length are chosen for improving the power performance. The designs of
different nand gates are according to size calculation done in section 6.1.2. The schematic and
the layout diagram of DFF are shown in following figures.

35
SAR ADC DESIGN

FIG: 6.4. D FLIP FLOP SCHEMATIC WITH SET AND RESET PINS

FIG: 6.5. Layout design of DFF

6.2. Pre and Post layout simulation results of SAR block

SAR block is simulated and the
simulation results are shown in
figures 6.6 and 6.7.

FIG: 6.6. Pre-Layout simulation of

SAR block

FIG: 6.7. Post-Layout simulation of

SAR block

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SAR ADC DESIGN

CHAPTER 7

EDGE TRIGGER CLOCK AND OUTPUT REGISTER

7.1. Clock Edges

A clock also has "edges". These are the times that the clock transitions from 0 to 1 (this is called
a positive edge) or from 1 to 0 (this is called a negative edge). In the original clock diagram at
the top, the edges are shown to go instantaneously from 0 to 1. In reality, that does not happen.

The clock looks more like:

FIG: 7.1. Clock output showing transition from low to high.

In other words, there's a small amount of time to transition from 0 to 1 (call the rise time) and a
small amount of time to transition from 1 to 0 (called the fall time). The timing diagram has been
exaggerated to make the rise and fall time more obvious. In general, those times are very short
compared to the time the clock stays at 1 or 0.
On the diagram, you see the label "positive". This indicates a 0 to 1 transition. That transition is
considered a positive edge (since it has a positive slope). The 1 to 0 transition is called a negative
edge (since it has a negative slope).

Why Are Clock Edges Important?

Flip flops (and registers, which are built from flip flops) are timed devices. They use a clock.
A flip flop can store 1 bit of information. In a positive edge-triggered flip flop, the value stored
in the flip flop can only change when a positive edge occurs. Thus, it can only change at the
circled portion (shown in the previous figure) that says "positive".

37
SAR ADC DESIGN

At all other times (i.e., when the clock is steady at 1, or steady at 0, or transitioning from 1 to 0
on a negative edge), the flip flop holds its value. That is, its value cannot change. Thus, edge
triggered flip flops can only change its values at the edge of a clock.

You might wonder why flip flops are designed this way, when combinational logic circuits (i.e.,
AND gates, OR gates, etc) do not use any clocks. It turns out that it’s easier to design digital
circuits which can only change values at an edge.

Design of positive edge triggered clock and Output Register:

Positive edge clock is designed with the help of some combinational logic and a capacitor as
shown in figure. As the outermost inverter has to drive a lot of load since it is being fed to all the
14 flipflops simultaneously so the transistor sizing has to be modified. The calculation for sizing
is done in same manner as done earlier in the case of SAR logic design.

The capacitor used in the design can be as small as possible for fast charge and discharge time
but smaller the capacitance lesser is the charge holding capacity. Here 1pF of capacitor is used.
The schematic and the layout of the positive edge trigger circuit is shown in figures 7.2 and 7.3.

FIG: 7.2. Schematic of positive edge trigger generation

FIG: 7.3. Layout diagram of positive edge trigger generation

Pre and post layout simulation results are shown here:

38
SAR ADC DESIGN

FIG: 7.4. Pre-Layout Simulation results of positive edge trigger generation \

FIG: 7.5. Post-Layout Simulation results of positive edge trigger generation

Output Register

The final digital code after conversion of a sample has to be stored somewhere for user to read it.
So a 14bit register is designed as shown in figure to store the value and pass it when needed. It is
14bit parallel input parallel output register designed using edge triggered D FlipFlops. And the
conversion time of a given signal is very less as compared to sample rate. So to reduce the power
consumption we want our ADC core to remain ideal for the time there is no new sample
available after the conversion of the given sample.

The Schematic and Layout design of output register is shown in figure 7.6 and 7.7.

FIG: 7.6. Schematic design for Output Register

FIG: 7.7. Layout design for Output Register

CHAPTER 8

TIMING AND CONTROL SYSTEM

39
SAR ADC DESIGN

8.1. Timing and Control system design

Different blocks used in this design requires clock at different instances of time. Apart from this
the Start of Conversion, End of Conversion and clock for output register to trigger has to be
generated from the global clock and user defined Sample and Hold signal. To meet the above
requirements, following circuit as shown in figures are designed and used.

8.1.2. EoC and SoC signal generation

End of conversion is needed as soon as the second sample arrives at the sample and hold input
and then we have start of conversion signal. The circuit used to generate these signals from the
global clock(CLK) and sample and hold control signal(S/H). The circuit is shown in the figure
8.1. The circuit is designed with the help of D flipflops and some combinational logics as shown
in figure.

FIG: 8.1. EoC and SoC generation circuit

40
SAR ADC DESIGN

8.1.3. Final clock and Output register clock signal generation

Since the frequency of seismic waves is very low so the sampling rate is low. Also we have
analog multiplexer which multiplexes three signals and feed to the ADC core. And the
conversion time of a given signal is very less as compared to sample rate. So to reduce the power
consumption we want our ADC core to remain ideal for the time there is no new sample
available after the conversion of the given sample. So at every 16th clock cycle after a sample
arrives the ADC is disabled. The timing diagram is shown in figure 8.4.

For user to read the value of a given sample, the output digital code after the conversion has to be
stored somewhere. So we designed parallel input parallel output 14bit register as mentioned in
chapter 7. The clock to enable this register has to trigger it at every 16th clock cycle after the
sample arrived.

The circuit used to generate these signals is shown in figure 8.2. It consist of 16-counter and
some combinational logics. The final timing and control circuit is shown in figure 8.3.

FIG: 8.2. Final clock and Register clock generation circuit

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SAR ADC DESIGN

FIG: 8.3. Schematic for generation of all the four signals i.e. EoC, SoC, Final clock and Register
clock

8.1.4. Timing diagram for complete operation of ADC

The timing diagram after simulation of all the four signals are shown in figure 8.4.

FIG: 8.4. Timing diagram for complete operation of ADC.

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SAR ADC DESIGN

CHAPTER 9

VALIDATION OF ADC CORE

9.1. Transient simulations

To test the ADC core, the A/D conversions listed in Table 9.1. have been simulated.
Table 9.1.Showing simulated results for different samples

Sample Expected Digital Code Simulated Digital Simulated Value

Code
1.8 V 11 1111 1111 1111 11 1111 1111 1111 1.8 V
900 mV 10 0000 0000 0000 01 1111 1111 1111 899.890 mV
450 mV 01 0000 0000 0000 00 1111 1111 1111 449.890 mV
225 mV 00 1000 0000 0000 00 0111 1111 1111 224.890 mV
112.5 mV 00 0100 0000 0000 00 0011 1111 1111 112.390 mV
56.250 mV 00 0010 0000 0000 00 0001 1111 1111 56.140 mV
28.125 mV 00 0001 0000 0000 00 0000 1111 1111 28.015 mV
14.0625 mV 00 0000 1000 0000 00 0000 0111 1111 13.952 mV
219 uV 00 0000 0000 0010 00 0000 0000 0001 109.86 uV
109 uV 00 0000 0000 0001 00 0000 0000 0000 0V

43
SAR ADC DESIGN

All the ten tests have been successful with ENOB=13. The figures given below shows simulation
results for some of the sample value mentioned in the table.

FIG: 9.1. ADC’s output digital code for input sample of 219uV.

44
SAR ADC DESIGN

FIG: 9.2. ADC’s output digital code for input sample of 450mV.

FIG: 9.3. ADC’s output digital code for input sample of 900mV.

45
SAR ADC DESIGN

46
SAR ADC DESIGN

CHAPTER 10

DISCUSSION
In this semester I have designed different blocks involved in to my project “DESIGN OF SAR
ADC FOR SEISMIC SENSOR BASED APPLICATIONS”.
Major issues:
1. Design of high resolution comparator with low power consumption.
2. Large area of R-2R DAC design.
3. Timing synchronization.
4. Complex layout design.
Steps taken to overcome these issues:
1. Proper aspect ratio and length and width of the transistors are adjusted to obtain a high
gain comparator. It also require proper biasing circuit.
2. R-2R DAC is replaced with Split array weighted capacitor DAC. Capacitors occupy less
area and also since we are using Split array capacitive method , the maximum
capacitance used in design is of lower value. This gives advantage over normal weighted
capacitor DAC.
3. Since our SAR logic takes 16 clock cycles to convert one sample to its digital value, so
the next sample is made available only after 16 *clock period. The clock period is such
that we overcome the delays produced by comparator to compare one value.
4. A lot of issues generate once we start the layout. Placement and Routing are very vital.
So I started making all standard cells of equal heights and followed 18 track design
methodology so that I can have enough space in between available for routing.

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SAR ADC DESIGN

CHAPTER 11

FUTURE WORK
Remaining Layout design.
Complete analysis of ADC and its components to optimize its performance. For example
Noise analysis , power consumption , slew rate , CMRR etc.
Integrating all blocks to make the final tapeout .
Optimizing comparator design to increase gain ,resolution and reduce power
consumption.
Improve the design according to feedback given by Fab lab.

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SAR ADC DESIGN

CHAPTER 12

REFERENCES

[1] Chung-Yi Li, Hao-Tsun Chao, and Chin Hsia, “A 10-Bit Area-Efficient SAR ADC with Re-
usable Capacitive Array,” in Anti Counterfeiting ,Security and Identification on 24-26 Aug, 2012
at Taipei. IEEE Conference Publication in Aug, 2012. pp. 1-5.

[2] Prakruthi T.G, and Siva Yellampalli, “Design and Implementation of Sample and Hold
Circuit in 180nm CMOS Technology”, in Advances in Computing, Communications, and
Informatics (ICACCI) , 2015 International Conference on 10-13 Aug, 2015 at Kochi. IEEE
Conference Publication in Aug, 2012. pp. 1148-1151.

[3] Silvia Dondi, DavideVecchi, Andrea Boni, and Marco Bigi , “A 6-bit, 1.2 GHz Interleaved
SAR ADC in 9Onm CMOS”, 2006 Ph.D. Research in Microelectronics and Electronics. IEEE
International conference at Otranto in 2006. pp. 301-304.

[4] Wee Leong Son, Hasmayadi Abdul Majid, and Rohana Musa, “High-Resolution 12-Bit
Segmented Capacitor DAC in Successive Approximation ADC”, World Academy of Science,
Engineering and Technology. International Journal of Electrical, Computer, Energetic,
Electronic and Communication Engineering Vol:6, No:12, 2012. pp. 1383-1386.

[5] H.KhurramabadiADC Converters (Lecture 13).UC Berkeley Course, Analog-Digital

Interfaces in VLSI Technology EE247.2006

[6] B. Razavi, Principles of Data Conversion System Design, Wiley-Interscience, IEEE Press,
1995.

[7] RahelehHedyati “A Study of Successive Approximation Registersand Implementation ofan

Ultra-Low Power 10-bit SAR ADCin 65nm CMOS Technology”, Master thesis, Linkoping
University, 2011.

[8] M. Saberi, R. Lotfi, K. Mafinezhad, W. A. Serdijn, “Analysis of Power Consumption and

Lineary in Capacitive Digital-to-Analog Converters Used in Successive Approximation
ADCs,”IEEE Transactions on Circuits and Systems, vol. 58, no. 8, August 2011. 73

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SAR ADC DESIGN

[9] Hur A. Hassan, Izhal Abdul Halin, Ishak Bin Aris , and MohdKhair Bin Hassan, “Design of
A Low Power 8-bit SAR-ADC CMOS”,Proceedings of 2009 Student Conference on Research
and Development (SCOReD 2009),16-18 Nov. 2009,
UPM Serdang, Malaysia

[10] Young-Deuk Jeon1, Young-Kyun Cho1, Jae-Won Nam1, Kwi-Dong Kim1,Woo-Yol Lee2,
Kuk-Tae Hong2, and Jong-Kee Kwon1 , “A 9.15mW 0.22mm2 10b 204MS/s Pipelined SAR
ADC in 65nm CMOS”,inCustom Integrated Circuits Conference (CICC),2010.IEEE conference
publication 19-22 sept 2010 in San Jose CA. pp.1-4.

[11] Bonnie C. Baker, Senior Applications Engineer ,”Designing an anti-aliasing filter for ADCs
inthe frequency domain”, in Analog Applications JournalTexas Instruments in 2015. AAJ 2Q
2015.

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