Logic Gates

Digital Logic Design

Timing Diagram

A graphical
representation
time
Of the truth table!

time

time

time

time
 Digital Logic Design

Boolean Algebra

Algebra Boolean Algebra

Numbers
Integers 1 (True, High)
Values Real numbers 0 (False, Low)
Complex Numbers

Operators +, -, x, /, … etc AND ( . )

OR (+)
NOT ( ‘, )

Variables may be given any name such as A, B, X etc..

 Digital Logic Design

Basic Definitions

 Binary Operators
● AND
z=x•y=xy (x * y) * z = x * (y * z)
● OR
z=x+y (x+y)+z = x+(y+z)
● NOT
z = x = x’

 Boolean Algebra
● Binary Variables: only ‘0’ and ‘1’ values

●Algebraic Manipulation
 Digital Logic Design

Boolean Algebra Postulates

 Commutative Law
x•y=y•x x+y=y+x
 Identity Element
x•1=x x+0=x
 Complement
x • x’ = 0 x + x’ = 1

x．x'=0 → 0．0'=0．1=0; x+x'=1 → 0+0'=0+1=1;

1．1'=1．0=0 1+1'=1+0=1
 Digital Logic Design

Duality

 It says that if an expression is valid in Boolean

algebra, the dual of that expression is also valid.

To form the dual of an expression,

replace all + operators with . operators,
all . operators with + operators,
all ones with zeros,

all zeros with ones.

 Digital Logic Design

Form the dual expression

 Example: F = (A + C) · B + 0
dual F = (A · C + B) · 1 = A · C + B

 Example: G = X · Y + (W + Z)
dual G = (X+Y) · (W · Z) = (X+Y) · (W+Z)

 Example: H = A · B + A · C + B · C
dual H = (A+B) · (A+C) · (B+C)
Digital Logic Design
 Digital Logic Design

Theorem 1 Applied to a valid

equation
● x•x=x x+x=x
produces a valid
Theorem 2 equation

● x•0=0 x+1=1
Postulates of Two-Valued Boolean Algebra
Digital Logic Design

x•(y+z)=(x•y)+(x•z)
x y z y+z x．(y+z) x．y x．z (x．y)+(x．z)
0 0 0 0 0 0 0 0

0 0 1 1 0 0 0 0

0 1 0 1 0 0 0 0

0 1 1 1 0 0 0 0

1 0 0 0 0 0 0 0

1 0 1 1 1 0 1 1

1 1 0 1 1 1 0 1

1 1 1 1 1 1 1 1
 Digital Logic Design

x + y.z = (x + y) . (x + z)
x y z y.z x + yz x+y x+z (x + y).(x + z)

0 0 0 0 0 0 0 0

0 0 1 0 0 0 1 0

0 1 0 0 0 1 0 0

0 1 1 1 1 1 1 1

1 0 0 0 1 1 1 1

1 0 1 0 1 1 1 1

1 1 0 0 1 1 1 1

1 1 1 1 1 1 1 1
 Digital Logic Design

Distributive Law
Digital Logic Design
Digital Logic Design
 Digital Logic Design

Null Law
 Digital Logic Design

Absorption Law
 Digital Logic Design

Consenus Theorem
Digital Logic Design
 Digital Logic Design

Transposition Theorem
 Digital Logic Design

De Morgan’s Law
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
 Digital Logic Design

x
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
 Digital Logic Design

Standard Form :

F  BC  AB  AC

F  (A  C)(A  B)(B  C)
 Digital Logic Design

Canonical Form
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
 Digital Logic Design

Steps :
1. Find Missing terms
2. Take Compliment
3. Put Value of Minterm
Digital Logic Design
 Digital Logic Design

Steps :
1. Find Missing terms
2. Multiply with remaining terms
 Digital Logic Design

Steps :
1. Find Missing terms
2. Add with remaining terms
 Digital Logic Design

Karnaugh Map / K Map

Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
Digital Logic Design
5 Variable K-Map
Digital Logic Design
Digital Logic Design
Variable Entered Map (VEM)
Digital Logic Design
VEM – 1 MEV
Digital Logic Design
Digital Logic Design
Digital Logic Design
VEM – 2 MEV
Simplification of Boolean Function Part II
Digital Logic Design

• Other Gate Types

• NAND
• NOR

• More Gates Types

• XOR
• XNOR
 More Gates – NAND, NOR
Digital Logic Design

X Y Z=(XY)’

X 0 0 1

NAND Z F = (XY)’ 0 1 1
Y 1 0 1
1 1 0

X Y Z=(X+Y)’
X
NOR Z F = (X+Y)’
0 0 1

Y 0 1 0
1 0 0
1 1 0

 Sometimes it is desirable to build circuits using

NAND gates only or NOR gates only
 NAND Gate is Universal
Digital Logic Design

NOT X X’ X
X’
X

X X XY
AND XY
Y Y

X X X+Y
OR X+Y
Y Y

• Therefore, we can build all functions we learned so far using NAND gates
ONLY (Exercise: Prove that NOT can be built with NAND)
• NAND is a UNIVERSAL gate
 Graphic Symbols for NAND Gate
Digital Logic Design

 Two equivalent X

graphic symbols or
AND-NOT Y (XYZ)’
Z
shapes for the
SAME function

X
NOT-OR X’+Y’+Z’ = (XYZ)’
Y
Z

AND-NOT (NAND) = NOT-OR (Bubbled OR)

 Implementation using NANDs
Digital Logic Design

 Example: Consider F = AB + CD
NAND
A A
B B
F F
C C
D D

NAND

Proof:
A
F = ((AB)’.(CD)’)’
= ((AB)’)’ + ((CD)’)’ B F
= AB + CD C
D
 Rules for 2-Level NAND
Digital Logic Design Implementations

1. Simplify the function and express it in sum-of-products

form
2. Draw a NAND gate for each product term (with 2 literals
or more)
3. Draw a single NAND gate at the 2nd level (in place of the
OR gate)
4. A term with single literal requires a NOT

What about multi-level circuits?

 NOR Gate is Universal
Digital Logic Design

X X’ X X’
NOT
X

X X (X’+Y’)’ = XY
AND XY
Y Y

X X (X+Y)’’ = X+Y
OR X+Y
Y Y

• Therefore, we can build all functions we learned so far using NOR gates
ONLY (Exercise: Prove that NOT can be built with NOR)
• NOR is a UNIVERSAL gate
 Graphic Symbols for NOR Gate
Digital Logic Design

 Two equivalent
graphic symbols or X
Y
(X+Y+Z)’
shapes for the OR-NOT
Z
SAME function
X (X’Y’Z’)=(X+Y+Z)’
NOT-AND Y
Z

OR-NOT (NOR) = NOT-AND (Bubbled AND)

 Implementation using NOR gates
Digital Logic Design

 Consider F = (A+B)(C+D)E
NOR

NOR
A A
B B
F F
C C
D D

E E’
 Implementation using NOR gates
Digital Logic Design

 Consider F =Σm(1,2,3,5,7) – Implement using NOR

gates

X’
Y=1 Z F
YZ
Y
X 00 01 11 10
Z
0 1 1 1
X=1 1 1 1
X’
Z=1 Z F
Y
F’(X,Y) = Y’Z’+XZ’ Z
OR
F(X,Y) = (Y+Z)(X’+Z)
 Rules for 2-Level
Digital LogicNOR
Design Implementations

1. Simplify the function and express it in product of sums

form
2. Draw a NOR gate (using OR-NOT symbol) for each sum
term (with 2 literals or more)
3. Draw a single NOR gate (using NOT-AND symbol) the
2nd level (in place of the AND gate)
4. A term with single literal requires a NOT

What about multi-level circuits?

 More Digital
Gates: XOR - XNOR
Logic Design

X Y Z=XY
Exclusive OR X F = X’Y + XY’ 0 0 0
Z
(XOR) Y =XY 0 1 1
1 0 1
1 1 0

Exclusive NOR X F = XY + X’Y’ X Y Z=(XY)’

Z
(XNOR) Y = (X  Y)’ 0 0 1
=XY 0 1 0
=X Y 1 0 0
1 1 1

Different symbols for XNOR

 XOR/XNOR Properties
Digital Logic Design

• X 0=X
X  0 = X’
• X  1 = X’
X1=X
• X X=0
XX=1
• X  X’ = 1
X  X’ = 0
• X  Y’ = X’  Y = (X  Y)’ = X  Y
• X  Y = X’  Y’ (same with XNOR)
• X  Y = Y  X (commutative, same with XNOR)
• X  (Y  Z) = (X  Y)  Z (associative, same with XNOR)
 Odd Parity Function
Digital Logic Design

 The XOR of an n-input function: F = XY Z is equal to 1

if and only if an odd number of variables of the function
have a value of 1

X Y Z F
The Exclusive OR of a function
acts as an ODD detector. It is 1 0 0 0 0
only if the number of 1’s in the 0 0 1 1
input is odd. 0 1 0 1

X 0 1 1 0
1 0 0 1
Y
1 0 1 0
1 1 0 0
Z
1 1 1 1
 Odd Parity Function
Digital Logic Design

4-Input XOR = 4-input odd parity checker

 Even Parity function
Digital Logic Design

 Function is equal to 1 if and only if the total number of 1’s

in the input is an even number
 Obtained by placing an inverter in front of the odd
function
X Y Z F
X
0 0 0 1
Y 0 0 1 0
0 1 0 0
Z 0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
 Summary
Digital Logic Design

• The universal gates NAND and NOR can

implement any Boolean expression
• NAND gates (2-level SOP)
• NOR gates (2-level POS)

• XOR and XNOR gates