Department of ECE

23EC1202
DIGITAL DESIGN & COMPUTER ARCHITECTURE
Session – 24

Instruction Sets, Machine Cycle

 AIM OF THE SESSION

To familiarize students with the basic concept of instruction set and machine cycle in the context of computer architecture.

INSTRUCTIONAL OBJECTIVES

This Session is designed to:

1. Demonstrate to decode and understand simple instructions sets.
2. Describe instructions related to data movement, such as load and store operations, and understand their role in transferring
data between memory and registers.
3. List out the Steps in machine cycle.

LEARNING OUTCOMES

At the end of this session, you should be able to:

1. Define the concept of an instruction set.
2. Describe how instructions are fetched, decoded, and executed within a processor.
3. Summarize the machine cycle process.
 Instruction Set

• An instruction set is a list of all the instructions that a processor can execute.
• Types of Operations:

1. Data Transfer
2. Arithmetic
3. Logical
4. Input Output [ I/O ]
5. System Control
6. Transfer Control
 Data Transfer - Instruction Set

• Move (Transfer) :Transfer word or block from source

• Exchange: Swap contents of source and
to destination.
destination.
Example: MOV AX, 1234H
Example: XCHG AH, AL
MOV [2345H], AX
XCHG AX, BX
• Store: Transfer word from processor to memory.
• Clear (reset): Transfer word of 0s to destination.
Example: STORE T
Example: CLR AX
STORE [R1], R3
CLR A
• Load (fetch): Transfer word from memory to processor.
• Set: Transfer word of 1s to destination
Example: LOAD A, [R1]
Example: SET A
LOAD C
 Arithmetic - Instruction Set

• Add: Compute sum of two operands. • Divide: Compute quotient of two operands.
Example: ADD AL, 07H Example: MOV AX,8003H
ADD AX,BX MOV CX,100H
• Subtract: Compute difference of two operands. DIV CX
Example: SUB AH, 05H • Negate: Change sign of operand.
SUB AH, AL Example: NEG AL
• Multiply: Compute product of two operands. • Increment : Add 1 to operand.
Example: MOV AX,1234H Example: INC A
MOV BX,100H • Decrement: Subtract 1 from operand.
MUL BX Example: DEC A
 Logical - Instruction Set

• AND: Performs the bitwise logical AND operation. • Exclusive OR: Performs the bitwise Exclusive-OR operation.
Example: AND AL, 0Fh Example: XOR AL,03H
AND AL, 01h AL (Operand1): 0101, Operand2: 0011
• OR: Performs the bitwise logical OR operation. After XOR -> Operand1: 0110
Example: OR AH, 0Bh • Shift: Left (right) shift operand, introducing constant at end.
OR AH, 05h Example: SHR AX, 2 (Shift Right by 2 times)
• NOT: Performs the bitwise logical NOT operation. SHL AX, 2 (Shift Left by 2 times)
Example: NOT AL • Rotate: Left (right) shift operation, with wraparound end
AL: 0101 0011 Example: ROR AH, 4 (Rotate Right by 2 times)
After NOT -> Operand1: 1010 1100 ROL AH, 4 (Rotate Left by 2 times)
 Input / Output - Instruction Set

• Input (Read): Transfer data from specified I/O port or device to destination (e.g., main memory or processor register)
• EX: IN AX, 20H (Transfer data from I/O port address of 20H to Register AX.)
INS [2000H],20H (Transfer data from I/O port address of 20H to memory location of [2000H].)
• Output (Write): Transfer data from specified source to I/O port or device.
• EX: OUT 30H, AX (Transfer data from Register AX to I/O port address of 30H.)
OUTS 30H, [2000H] (Transfer data from memory location of [2000H] to I/O port address of 30H.)
• Start I/O (SIO): This instruction triggers an input/output procedure on a designated device. When you need to carry out
I/O tasks, you utilize Start I/O (SIO) to commence the operation.
• Test I/O (TIO): Test I/O (TIO) is employed for monitoring the progress of an active I/O operation on a designated device. It
enables you to ascertain whether the I/O process has been finalized or is still in progress.
 System Control - Instruction Set

• System control instructions are those which are used for system setting and it can be used only

in privileged state.

• Typically, these instructions are reserved for the use of operating systems.
 Transfer of Control - Instruction Set

• The control transfer instructions redirect the program's execution flow to a specified address
indicated directly or indirectly within the instruction.
• The most common transfer-of-control operations found in instruction set are:
1. Branch (Jump)
2. Skip
3. Procedure call (CALL XXXX)
BRP X: Branch to location X if result is positive
BRN X: Branch to location X if result is negative
BRZ X: Branch to location X is result is zero
BRO X: Branch to location X if overflow occurs
 Machine Cycle
➢ A computer's memory unit contains a program, which is comprised of a sequence of instructions.
➢ CPU executes each single instruction through a simple procedure called a machine cycle, which is also referred to as an
instruction cycle.
➢ The CPU follows a series of stages in order to retrieve, decode, and carry out a command. There are multiple phases to a
typical machine cycle:
• Fetch Phase: The address of the instruction to be fetched is determined by the program counter. Then the CPU retrieves the
instruction from memory.
• Decode Phase: The fetched instruction is decoded to determine the operation to be performed and the operands involved.
• Execute Phase: The actual operation specified by the instruction is carried out. This could involve arithmetic or logical
operations, data manipulation, or control transfer.
 Machine Cycle (Cont.)

• The CPU is prepared to get the subsequent instruction

and resume the cycle after these stages are finished.

• The whole performance of a computer is greatly influe

nced by the speed and effectiveness of these cycles.
 Fetch Phase

• During the fetch cycle, an instruction is read from

memory. The following Figure shows the flow of data
during this cycle.

• The PC contains the address of the next instruction to

be fetched. This address is moved to the MAR and
placed on the address bus.

• The control unit requests a memory read, and the result

is placed on the data bus and copied into the MBR and
then moved to the IR.

• Meanwhile, the PC is incremented by 1, preparatory for

the next fetch.
 Fetch Phase (Cont.)

• The illustrated fetch cycle above can be summarized by the following points:
PC => MAR
MAR => memory => MBR
MBR => IR
PC=PC+1
 Decode Phase

➢ After the CPU has finished fetching an instruction, the Control Unit (CU) checks the contents of
the Instruction Register (IR) and determines which type of execution is to be carried out next. This
process is known as the decoding phase.
➢ The fetched instruction is interpreted or decoded to identify the operation to be carried out and
the operands involved.
• Instruction Decoding
• Operand Extraction
• Control Signal Generation
• Address Calculation (if applicable)
➢ The instruction is now ready for the execution cycle.
 Execution Phase

➢ After the instruction has been fetched and placed into the Instruction Register (IR), and subsequent
examination and decoding by the Control Unit (CU) to determine the necessary action, the execution
cycle can begin.
➢ The actions within the execution cycle can be categorized into the following four groups:
• CPU - Memory: Data may be transferred from memory to the CPU or from the CPU to memory.
• CPU - I/O: Data may be transferred from an I/O module to the CPU or from the CPU to an I/O
module.
• Data Processing: The CPU may perform some arithmetic or logic operation on data via the
arithmetic-logic unit (ALU).
• Control: An instruction may specify that the sequence of operation may be altered.
 SELF-ASSESSMENT QUESTIONS
1.Which type of instruction involves transferring data between memory and registers?

A. Control transfer instructions

B. Arithmetic instructions
C. Data movement instructions
D. Logic instructions

2. What is a common trade-off when designing an instruction set?

A. Execution speed vs. code size

B. Memory size vs. processor speed
C. Number of registers vs. cache size
D. Pipelining vs. parallel processing
 SELF-ASSESSMENT QUESTIONS
3. Which of the following is not a general operation of machine cycle in a CPU ?

A. Fetch
B. Decode
C. Return
D. Store

4. A unit that decodes, interprets each instruction and generates the required enable signal for
ALU and other units is called _____________.

A. Arithmetic Unit
B. CPU
C. Logical Unit
D. Control Unit
 REFERENCES FOR FURTHER LEARNING OF THE SESSION

Reference Books:
1. Computer Organization by Carl Hamacher, Zvonko Vranesic and Saftwat Zaky.
2. Computer System Architecture by M. Morris Mano
3. Computer Organization and Architecture by William Stallings

Sites and Web links:

1. https://www.javatpoint.com/instruction-cycle
2. https://www.tutorialspoint.com/what-is-an-instruction-set-in-a-computer
 THANK YOU

Team – Digital Design & Computer Architecture