20/02/2024, 10:22 Data Flow Modeling - javatpoint

Data Flow Modeling

Dataflow modeling makes use of the functions that define the working of the circuit instead
of its gate structure.

Dataflow modeling has become a popular design approach, as logic synthesis tools became
sophisticated. This approach allows the designer to focus on optimizing the circuit in terms
of the flow of data.

Dataflow modeling uses several operators that act on operands to produce the desired
results. Verilog provides about 30 operator types. Dataflow modeling describes hardware in
terms of the flow of data from input to output.

The dataflow modeling style is mainly used to describe combinational circuits. The primary
mechanism used is a continuous assignment.

Continuous Assignments

A value is assigned to a data type called net, which is used to represent a physical connection
between circuit elements in a continuous assignment. The value assigned to the net is
specified by an expression that uses operands and operators.

A continuous assignment replaces gates in the circuit's description and describes the circuit
at a higher level of abstraction. A continuous assignment statement starts with the keyword
assign.

Syntax

The syntax of a continuous assignment is

assign [delay] LHS_net = RHS_expression;

LHS_net is a destination net of one or more bit, and RHS_expression is an expression of

various operators.

The statement is evaluated at any time any of the source operand value changes, and the
result is assigned to the destination net after the delay unit.

The LHS of the assign statement must always be a scalar or vector net or a
concatenation. It cannot be a register.

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Continuous statements are always active statements, which means that if any value on
the RHS changes, LHS changes automatically.

Registers or nets or function calls can come in the RHS of the assignment.

The RHS expression is evaluated whenever one of its operands changes. Then the
result is assigned to the LHS.

Delays can be specified in the assign statement.

Example

assign out1 = in1 & in2; // perform and function on in1 and in2 and assign the result to out1
assign out2 = not in1;
assign #2 z[0] = ~
(ABAR & BBAR & EN); // perform the desired function and assign the result after 2 units

The target in the continuous assignment expression can be one of the following:

1. A scalar net

2. Vector net

3. Constant bit-select of a vector

4. Constant part-select of a vector

5. Concatenation of any of the above

Let us take another set of examples in which a scalar and vector nets are declared and used

wire COUNT, CIN; // scalar net declaration

wire [3:0] SUM, A, B; // vector nets declaration
assign {COUT,SUM} = A + B + CIN; // A and B vectors are added with CIN

NOTE: Multiple continuous assignment statements are not allowed on the same destination
net.

Continuous Assignment on Vectors

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As described in the characteristics, the continuous assignment can be performed on vector

nets.

module adder(a,b,sum);
input [2:0] a,b;
output [3:0] sum;

assign sum = a + b;
$display("a = %b, b = %b, sum=%b", a,b,sum);
endmodule

The above code describes a 3-bit adder. The MSB of the sum is dedicated to carry in the
above module. It generates the following output:

a = 100, b = 111, sum = 1011 // (a = 4, b = 7, sum = 011, carry = 1)

The concatenation of vector and scalar nets is also possible. The same example for 3-bit
adder is shown by using concatenation:

module adder(a,b,sum);
input [2:0] a,b;
output [2:0] sum; //sum is a vector
output carry; // carry is a scalar

assign {carry,sum} = a + b; //assigning result to a concatenation of scalar and vector

$display("a = %b, b = %b, sum=%b, carry = %b", a,b,sum,carry);
endmodule

The output is:

a = 100, b = 111, sum = 011, carry = 1

1. Regular Continuous Assignment

It follows the following steps, such as:

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Step 1: Declare net.

Step 2: Write a continuous assignment on the net.

The below code follows Regular continuous assignment:

wire out; // net 'out' is declared

assign out = a&b; //continuous assignment on declared net

2. Implicit Continuous Assignment

We can also place a continuous assignment on a net when it is declared. The format will look
like the below:

wire out = a & b; // net declaration and assignment together

3. Implicit Net Declaration

In Verilog, during an implicit assignment, if LHS is declared, it will assign the RHS to the
declared net, but if the LHS is not defined, it will automatically create a net for the signal
name.

Wire in0, in1;

Assign out = in0 ^ in1;

In the above example, out is undeclared, but Verilog makes an implicit net declaration for
out.

Delays

In real-world hardware, there is a time gap between change in inputs and the corresponding
output.

For example, a delay of 2 ns in an AND gate implies that the output will change after 2 ns
from the time input has changed.

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Delay values control the time between the change in an RHS operand and when the new
value is assigned to LHS. It is similar to specifying delays for gates. Adding delays helps in
modeling the timing behavior in simple circuits.

It is getting us closer to simulating the practical reality of a functioning circuit. There are
different ways to specify a delay in continuous assignment statements, such as:

1. Regular Assignment Delay

We assign a delay value in the continuous assignment statement. The delay value is specified
after the assign keyword.

This delay is applicable when the signal in LHS is already defined, and this delay represents
the delay in changing the value of the already declared net. For example,

Assign #10 out = in0 | in1;

If there is any change in the RHS operands, then RHS expression will be evaluated after 10
units of time and the evaluated expression will be assigned to LHS.

At time t, if there is a change in one of the operands in the above example, then the
expression is calculated at t+10 units of time.

It means that if in0 or in1 changes value before 10-time units, then the values of in1 and in2
at the time of re-computation (t+10) are considered.

2. Implicit Continuous Assignment Delay

Here, we use an implicit continuous assignment to specify both a delay and an assignment on
the net.

wire #10 out = in0 ^ in1; //implicit Continuous Assignment Delay.

Is same as

wire out
assign #10 out = in0 ^ in1;

3. Net Declaration Delay

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In this case, the delay is associated with the net instead of the assignment.

Here, a delay is added when the net is declared without putting continuous assignment.

wire #10 out;

assign out = in;

This code has the same effect as the following:

wire out
assign #10 out = in;

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