VIETNAM NATIONAL UNIVERSITY HANOI (VNU)

INFORMATION TECHNOLOGY INSTITUTE

Microblaze

Duy-Hieu Bui and Xuan-Tu Tran

VNU Information Technology Institute
Laboratory for Smart Integrated System (SISLAB)
Email: [email protected]
https://duyhieubui.github.io

Objectives

• After completing this module, you will be able to:

– List the MicroBlaze features
– Describe the differences between the interface and bus
– List the various buses and interfaces available in the MicroBlaze
processor system

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• MicroBlaze Features

• MicroBlaze System Busses and Interfaces

– Advanced Extensible Interface (AXI)

– Processor Local Bus (PLB)

– Local Memory Bus (LMB)

– Fast Simplex Links (FSL)

– Xilinx Cache Links (XCL)

• Summary

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• MicroBlaze Features

• MicroBlaze System Busses and Interfaces

– Advanced Extensible Interface (AXI)

– Processor Local Bus (PLB)

– Local Memory Bus (LMB)

– Fast Simplex Links (FSL)

– Xilinx Cache Links (XCL)

• Summary

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 MicroBlaze Block Diagram

Optional MMU for

AXI interface for
Linux2.6 and MPU block
caches
for ease of software use

AXI based system

AXI-Streams for
CPU to hw/sw
accelerators

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MicroBlaze Processor

• Scalable 32-bit Core

– Single-Issue pipeline
• Supports either 3-stage (resource focused) or 5-stage pipeline (performance
focused)
– Configurable Instruction and Data Caches over either AXI or XCL
interfaces
• Direct mapped (1-way associative)
– Optional Memory Mgt or Memory Protection Unit
• Required for Linux OS (Linux 2.6 is currently supported)
– Floating-point unit (FPU)
• Based upon IEEE 754 format
– Barrel Shifter
– Hardware multiplier
• 32x32 multiplication to generate a 64-bit result
– Hardware divider
– AXI4 Stream channels for easy, direct access to fabric and hardware
acceleration
– Hardware Debug and Trace module
– Configurable endianess
• Little endian for AXI system
• Big endian for PLB system
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 MicroBlaze Processor Features

• Features and improvements

– High-performance AXI4 interface and AXI4 peripherals
– Memory Management Unit (MMU) implements virtual memory
management
• PPC405 processor MMU compatible
• Virtual memory management provides greater control over memory
protection, which is especially useful with applications that can use an
RTOS
– Processing improvements
• New float-integer conversion and float-square root instructions
• Speeds up
– FP → Int conversion
– Int → FP conversion
– FP square root
– Enhanced XMD support
– AXI4 streaming interface
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MicroBlaze Processor Features

AXI Streaming Interface

• Unidirectional, point-to-point FIFO-based communication

• Built-in programmable depth FIFO
• Simplex connection—processor to/from FIFO
• Direct connection to CPU core
– Native to MicroBlaze processor hardware
• Enable up to 16 in/out pairs (channels)
• Dedicated register to/from FIFO assembler instructions (same as for FSL)

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 AXI4 System

BRAM LMB

AXI4 AXI4 AXI Memory External

Controller Memory

AXI
Interconnect
AXI4
MicroBlaze AXI Video DMA

AXI4
TEMAC

Hardware AXI4-Stream AXI4

Accelerator Custom IP

AXI Interconnect
AXI4-Lite AXI4-Lite AXI4-Lite AXI4-Lite

AXI to IPIF IPIF

Timer SRAM UART Custom IP
Bridge

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Multi-processor Capability

• Two fundamental MP cores

– Mailbox: allows for message passing between 2 CPUs or CPU and
accelerator
• Supports AXI4-Lite, AXI4-Stream and FSL
– Mutex core: allows 2 or more CPUs to synchronize
• Supports AXI4-Lite and PLBV46
• Processor Version Register (PVR) support
– Contains: Processor ID, configuration/user/processor info (e.g. cache
size etc), version number and other internal information
• PVR options:
– None (C_PVR=0). No PVR implemented at all
– Basic (C_PVR=1). Only first PVR register implemented
• Allow designers to assign unique ID for a particular MicroBlaze core
• Important for multi-core application or debug
– Full (C_PVR=2). All PVR registers (twelve) implemented
• Allow designers access to all PVR registers for individual MicroBlaze
configuration information per core

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 MailBox Core

• Two processors can communicate with each other either using

PLB, AXI4-Lite, AXI4-Stream, or FSL interface
– In AXI system, AXI4-Lite, and AXI4-Stream are available
• Configurable parameters
– Depth
• 16 to 8192 words
– Interrupt thresholds and maskable interrupts
• Separate thresholds for receive and send
• Maskable interrupts for error, receive, and send
– Synchronous or asynchronous operations

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Mutex Core

• The core provides mechanism for mutual exclusion to enable

one process to gain exclusive access to a particular resource
• Contains a configurable number of mutexes (up to 32)
– Each of these can be associated with a 32-bit User configuration register
to store arbitrary data
• Configurable parameters
– Priority based PLB/AXI4-Lite interfaces from 0 to 7 (0 is highest priority)
– Asynchronous or synchronous interface operation
– USER register
– Number of mutexes
– CPUID width
– Enhanced security through hardware identification support

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• MicroBlaze Features

• MicroBlaze System Busses and Interfaces

– Advanced Extensible Interface (AXI)

– Processor Local Bus (PLB)

– Local Memory Bus (LMB)

– Fast Simplex Links (FSL)

– Xilinx Cache Links (XCL)

• Summary

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AXI is Part of ARM’s AMBA

AMBA

APB AHB AXI

Older Performance Newer

AMBA: Advanced Microcontroller Bus Architecture

AXI: Advanced Extensible Interface

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 AXI is Part of AMBA:
Advanced Microcontroller Bus Architecture

AMBA
Enhancements for FPGAs

APB AHB AXI ATB AMBA 3.0

(2003)

Same Spec
AXI-4 AXI-4 AXI-4 AMBA 4.0
(2010)
Memory Map Stream Lite
Interface Features Similar to
Memory Map / Full Traditional Address/Data Burst PLBv46, PCI
(AXI4) (single address, multiple data)
Streaming Data-Only, Burst Local Link / DSP Interfaces / FIFO /
(AXI4-Stream) FSL

Lite Traditional Address/Data—No Burst PLBv46-single

(AXI4-Lite) (single address, single data) OPB

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What is AXI?

• Is . . .
– An interface and protocol definition for pieces of
IP
– A symmetrical, point-to-point, master/slave
interface (symmetrical means all signals that exist
on a master also exist on a slave) Arrows indicate Master/Slave Relationship not direction of
data flow
• Isn’t . . .
Master Slave
– A bus
• Sure, some signals like, say, the data bus, are
buses, but AXI itself is not a bus specification

The AXI specification describes an interface on a piece of IP.

It does not specify how systems of IP are to be connected except for the fact that a single master
interface always connects to a single slave interface.

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 Basic AXI Signaling – 5 Channels

1. Read Address Channel

2. Read Data Channel

3. Write Address Channel

4. Write Data Channel
5. Write Response Channel

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The AXI Interface—AXI4

• Sometimes called “Full AXI” or “AXI Memory Mapped”

– Not ARM-sanctioned names

• Single address multiple data

– Burst up to 256 data beats

• Data Width parameterizable

– 1024 bits

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 The AXI Interface—AXI4-Stream

• No address channel, no
read and write, always
just master to slave
– Effectively an AXI4 “write AXI4-Stream Transfer
data” channel
• Unlimited burst length
– AXI4 max 256
– AXI4-Lite does not burst
• Virtually same signaling
as AXI Data Channels
– Protocol allows merging,
packing, width conversion
– Supports sparse,
continuous, aligned,
unaligned streams

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Streaming Applications

• May not have packets

– E.g. Digital up converter
• No concept of address
• Free-running data (in this case)
• In this situation, AXI4-Stream would optimize to a very simple interface
• May have packets
– E.g. PCIe
• Their packets may contain different information
• Typically bridge logic of some sort is needed

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 Processor Local Bus (PLB)

• Connection infrastructure in PLB System

• Fully synchronous to one clock
• Centralized bus arbitration—PLB arbiter
• 32 or 64-bit address (upper 32-bit are connected to GND by
default)
• 32, 64, or 128-bit data bus
• Selectable shared bus or point-to-point interconnect topology
– Point-to-point optimization available for 1 master, 1 slave configuration
– Point-to-point topology supports 0 cycle latency via arbitration removal
• Selectable address pipelining support (2-level only)
• Dynamic master request priority based arbitration
• Vectored resets and address/qualifier registers

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PLB Bridge

• The PLB-to-PLB is required when two PLB segments are

connected
– Different bus speed
– Different bus width
• The bridge translates PLB transactions on one side into the
PLB transactions of the other side
• The bridge functions as a slave on one PLB side and a master
on
the other PLB side
• For a typical system with two PLB segments, one bridge is
necessary for transactions originating from processor
– A second bridge is required if a peripheral on the other side is master
capable and wants to address a peripheral on the processor side

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 AXI Bridges

• AXI_to_PLBv46 and PLBv46_to_AXI Bridges

– Used in system having two standards (Core-Connect and AMBA)
– Supports multi-master/multi-slave connections
– Designed to support existing customer PLBv46-based cores in an AXI
system
• AXI_to_APB Bridge
– Designed to support 3rd party slave IP talking to an AXI4-Lite master
– The bridge is slave on the AXI4Lite side and master on the APB
peripheral side
– APB3/APB4 peripherals are supported

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Local Memory Bus (LMB)

• The Local Memory Bus (LMB) provides single-cycle access to

on-chip dual-port block RAM for MicroBlaze processors
• The LMB provides simple synchronous protocol for efficient
block RAM transfers
– DLMB: Data interface, local memory bus (block RAM only)
– ILMB: Instruction interface, local memory bus (block RAM only)

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 Fast Simplex Links ( FSL)

• Unidirectional point-to-point FIFO-based communication

• Dedicated (unshared) and nonarbitrated architecture
• Dedicated MicroBlaze™ C and ASM instructions for easy access
• High speed access in as little as two clocks on processor side
• Available in Xilinx Platform Studio (XPS) as a bus interface
library core from Hardware → Create or Import Peripheral
Wizard

FSL_M_Clk FSL_S_Clk
FSL_M_Data [0:31] FSL_S_Data [0:31]
FSL_M_Control FIFO FSL_S_Control

32-bit data
FSL_M_Write FSL_S_Read
FSL_M_Full FSL_S_Exists

FIFO Depth

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FSL Features

• 32-bit wide interface

• Configurable FIFO depths – 1 to 8192 using SRL16 or block
RAM
• Synchronous or asynchronous FIFO clocking with respect to
the MicroBlaze™ system clock
• Selectable use of control bit
• Simple software interface using predefined C instructions;
Automatically generated C drivers
• Blocking and non-blocking software instructions for
– Blocking data (get and put) and control (cget and cput)
– Non-blocking data (nget and nput) and control (ncget and ncput)
• Exception from FSL can be generated
• Disable interrupt while FSL executing
• Addition of dynamic assignment of FSL channel (getd and putd)
– Channel number from register rather than immediate

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 Xilinx Cache Link

• High performance solution for memory accesses in PLB system

• The MicroBlaze CacheLink interface is designed to connect
directly to a memory controller with integrated FSL Buffers
– i.e. MicroBlaze can connect directly to data ports of EDK supported
multi-port memory controllers
• The CacheLink Interface is only available on MicroBlaze when
caches are enabled and should only be used when external
memory is present in the system
• The CacheLink cache controllers handle 4 or 8-word cache
lines
• All individual CacheLink accesses follow the FSL FIFO based
transaction protocol

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Caches in AXI System

• With XCL, Instruction and Data port widths are 32 bits only
• MicroBlaze AXI Cache Interfaces allows different port widths
– 32-bit (legacy)
– 128-bit (4 word cache line)
– 256-bits (8-word cache line)
• Interconnect handles bridging between MicroBlaze and Memory
Controller

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 MicroBlaze Cache to External Memory Datapath
Default ,Configuration, same as pre-AXI

C_ICACHE_DATA_WIDTH = 0

Instruction Cache
AXI4
32-bits

AXI
MicroBlaze Interconnect AXI4 to External
C_DCACHE_DATA_WIDTH = 0
External Memory Memory
64-bits
Data Cache
AXI4
32-bits

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MicroBlaze Cache to External Memory Datapath

Highest Performance, MicroBlaze port widths match AXI cache line width

C_ICACHE_DATA_WIDTH = 1

C_xCACHE_DATA_WIDTH = 1 and C_xCACHE_LINE_LEN = 4 => 128 bits

Instruction Cache C_xCACHE_DATA_WIDTH = 1 and C_xCACHE_LINE_LEN = 8 => 256 bits
AXI4 C_xCACHE_DATA_WIDTH = 2 => 512 bits
128 / 256 bits

AXI AXI4 to
MicroBlaze Interconnect External External
C_DCACHE_DATA_WIDTH = 1 Memory Memory
64-bits
Data Cache
AXI4
128 / 256 bits

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• MicroBlaze Features

• MicroBlaze System Busses and Interfaces

– Advanced Extensible Interface (AXI)

– Processor Local Bus (PLB)

– Local Memory Bus (LMB)

– Fast Simplex Links (FSL)

– Xilinx Cache Links (XCL)

• Summary

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Summary

• Current version of MicroBlaze supports AXI and PLB interfaces

– Either PLB bus or AXI interface can be present on the processor
– FSL channels are available for PLB system and AXI4 Stream interfaces
are available for AXI system
• AXI is an interface providing high performance through point-
to-point connection
• PLB is a shared bus connection infrastructure for high-
bandwidth master and slave devices
• LMB provides local memory where data, stack, interrupt service
routines can reside. It provides fixed and deterministic latency
• Caching can be done either on AXI interface or XCL provided
caches are enabled
• Caching may be enabled only when external memory is present

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