VIETNAM NATIONAL UNIVERSITY HANOI (VNU)

INFORMATION TECHNOLOGY INSTITUTE

Sequential logic and FSM design with

VHDL

Xuan-Tu Tran
Vietnam National University, Hanoi
Email: [email protected]

Outlines

• VHDL modeling examples

• Finite State Machine

• Finite State Machine in VHDL

9/11/2022 Duy-Hieu Bui & Xuan-Tu Tran 2

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 VHDL examples

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Comparator Example

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY comp_4bit IS PORT (

in1, in2 : IN std_logic_vector (3 DOWNTO 0);
eq : OUT std_logic );
END comp_4bit;

ARCHITECTURE functional OF comp_4bit IS

SIGNAL im : std_logic_vector (3 DOWNTO 0);
FUNCTION nor_reduce
(in1: IN std_logic_vector (3 DOWNTO 0))
RETURN std_logic
IS
VARIABLE result : std_logic ;
BEGIN
result:= NOT (in1(3) OR in1(2) OR in1(1) OR in1(0)) ;
RETURN result;
END;
BEGIN
im <= in1 XOR in2;
eq <= nor_reduce(im);
END functional;
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 Multiplexer Example

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY multiplexer IS
PORT (a, b : IN std_logic_vector; s : IN std_logic;
w : OUT std_logic_vector);
END ENTITY;
ARCHITECTURE expression OF multiplexer IS
BEGIN
w <= a WHEN s = '0' ELSE b;
END ARCHITECTURE expression;

Note: An Unconstrained 2-to-1 Mux using Condition Operator

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Decoder Example

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dcd2to4 IS
PORT (sel: IN std_logic_vector (1 DOWNTO 0);
y: OUT std_logic_vector (3 DOWNTO 0) );
END dcd2to4;

ARCHITECTURE structural OF dcd2to4 IS

BEGIN
WITH sel SELECT
y <= "0001" WHEN "00",
"0010" WHEN "01",
"0100" WHEN "10",
"1000" WHEN "11",
"0000" WHEN OTHERS;
END ARCHITECTURE structural;

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 Adder Example

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY adder8 IS PORT (
a : IN std_logic_vector (7 DOWNTO 0);
b : IN std_logic_vector (7 DOWNTO 0);
ci : IN std_logic;
s : OUT std_logic_vector (7 DOWNTO 0);
co : OUT std_logic );
END ENTITY adder8;
--
ARCHITECTURE equation OF adder8 IS
SIGNAL mid : std_logic_vector (8 DOWNTO 0);
BEGIN
mid <= ('0'&a) + ('0'&b) + ci;
co <= mid (8);
s <= mid (7 DOWNTO 0);
END equation; Adder with Carry-in and Carry-out

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ALU Example

ENTITY alu8 IS PORT (

a, b : IN std_logic_vector (7 DOWNTO 0);
addsub : IN std_logic;
gt, zero, co : OUT std_logic;
r : OUT std_logic_vector (7 DOWNTO 0));
END ENTITY alu8;
ARCHITECTURE assigns OF alu8 IS
SIGNAL mid : std_logic_vector (8 DOWNTO 0);
BEGIN
mid <= ('0'& a) + ('0'& b) WHEN addsub = '1' ELSE ('0'& a) - ('0'& b);
co <= mid (8);
r <= mid (7 DOWNTO 0);
gt <= '1' WHEN a > b ELSE '0';
zero <='1' WHEN mid (7 DOWNTO 0) = "00000000" ELSE '0';
END assigns;

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 ALU Example Using Adder

ENTITY alu8add IS PORT (

a, b : IN std_logic_vector (7 DOWNTO 0);
gt, zero, co : OUT std_logic;
r : OUT std_logic_vector (7 DOWNTO 0));
END ENTITY alu8add;
ARCHITECTURE assigns OF alu8add IS
SIGNAL mid8 : std_logic_vector (7 DOWNTO 0);
SIGNAL mid1 : std_logic;
BEGIN
AD: ENTITY WORK.adder8 PORT MAP (a, b, '0', mid8, OPEN);
-- AD: ENTITY WORK.adder8 PORT MAP
-- (a => a, b => b, ci => '0', s => mid8, co => co);
r <= mid8;
gt <= '1' WHEN a > b ELSE '0';
zero <= '1' WHEN mid8 = "00000000" ELSE '0';
END assigns;

ALU VHDL Code Using Instantiating an Adder

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Bussing

ENTITY bussing IS
PORT ( Three-state Bussing
busin1: IN std_logic_vector (3 DOWNTO 0);
busin2: IN std_logic_vector (3 DOWNTO 0);
busin3: IN std_logic_vector (3 DOWNTO 0);
en1: IN std_logic;
en2: IN std_logic;
en3: IN std_logic;
busout: OUT std_logic_vector(3 DOWNTO 0) );
END bussing;
--
ARCHITECTURE structural OF bussing IS
BEGIN
busout <= busin1 WHEN en1 = '1' ELSE (OTHERS => 'Z');
busout <= busin2 WHEN en2 = '1' ELSE (OTHERS => 'Z');
busout <= busin3 WHEN en3 = '1' ELSE (OTHERS => 'Z');
END structural;

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 Basic Memory Elements at the Gate Level

Clocked D-latch

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Basic Memory Elements at the Gate Level

ENTITY latch IS
PORT (d, c: IN std_logic;
q, q_b : BUFFER std_logic);
END latch;
ARCHITECTURE structural OF latch IS
SIGNAL s, r : std_logic;
BEGIN
s <= c AND d AFTER 6 ns;
r <= c AND (NOT d) AFTER 6 ns;
q_b <= s NOR q AFTER 4 ns;
q <= r NOR q_b AFTER 4 ns;
END structural;

VHDL Code for a Clocked D-latch

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 Memory elements using Procedural Statements

ENTITY latch1 IS
PORT (d, c: IN std_logic; q: OUT std_logic);
END latch1;
ARCHITECTURE behavioral OF latch1 IS
BEGIN
PROCESS (d, c)
BEGIN
IF c = '1' THEN
q <= d;
END IF;
END PROCESS;
END ARCHITECTURE behavioral;

Procedural Latch

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A Positive-Edge D Flip-Flop

ENTITY DFF1 IS
PORT (d, clk: IN std_logic; q : OUT std_logic);
END DFF1;
--
ARCHITECTURE behavioral OF DFF1 IS
BEGIN
PROCESS (clk)
BEGIN
IF clk = '1' AND clk'EVENT THEN
q <= d;
END IF;
END PROCESS;
END ARCHITECTURE behavioral;

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 Synchronous Control

ENTITY DFF1sr IS
PORT (d, clk, s, r: IN std_logic; q : OUT std_logic);
END DFF1sr;
--
ARCHITECTURE behavioral OF DFF1sr IS
BEGIN
PROCESS (clk)
BEGIN
IF clk = '1' AND clk'EVENT THEN
IF s = '1' THEN
q <= '1';
ELSIF r = '1' THEN
q <= '0';
ELSE
q <= d;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE behavioral;

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Synchronous Control

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 Asynchronous Control

ARCHITECTURE asynchronous OF DFF1sr IS

BEGIN
PROCESS (clk, s, r) BEGIN
IF s = '1' THEN
q <= '1';
ELSIF r = '1' THEN
q <= '0';
ELSIF clk = '1' AND clk'EVENT THEN
q <= d;
END IF;
END PROCESS ;
END ARCHITECTURE asynchronous;

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Asynchronous Control

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 Registers

ENTITY register8 IS
PORT (
d : IN std_logic_vector (7 DOWNTO 0);
clk, s, r : IN std_logic;
q : OUT std_logic_vector ( 7 DOWNTO 0));
END register8;
--
ARCHITECTURE behavioral OF register8 IS
BEGIN
PROCESS (clk)
BEGIN
IF clk = '1' AND clk'event THEN
IF s= '1' THEN
q <= (OTHERS => '1');
ELSIF r = '1' THEN
q <= (OTHERS => '0');
ELSE
q <= d;
END IF;
END IF;
END PROCESS;
END behavioral;

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Shift-Registers

ENTITY shift_reg4 IS
PORT (
d : IN std_logic_vector (3 DOWNTO 0);
clk, ld, rst, l_r, s_in : IN std_logic;
q : OUT std_logic_vector (3 DOWNTO 0));
END shift_reg4;
ARCHITECTURE behavioral OF shift_reg4 IS
BEGIN
PROCESS (clk)
VARIABLE q_t: std_logic_vector (3 DOWNTO 0);
BEGIN
IF rising_edge (clk) THEN
IF rst= '1' THEN
q_t := (OTHERS => '0');
ELSIF ld = '1' THEN
q_t := d;
ELSIF l_r = '1' THEN
q_t := q_t (2 DOWNTO 0) & s_in ;
ELSE
q_t := s_in & q_t (3 DOWNTO 1);
END IF;
END IF;
q <= q_t;
END PROCESS;
END behavioral;
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 Counters

ENTITY counter4 IS
PORT (reset, clk : IN std_logic;
count : OUT std_logic_vector (3 DOWNTO 0));
END ENTITY;
--
ARCHITECTURE procedural OF counter4 IS
SIGNAL cnt_reg : std_logic_vector (3 DOWNTO 0);
BEGIN
PROCESS (clk)
BEGIN
IF (clk = '0' AND clk'EVENT) THEN
IF (reset='1') THEN
cnt_reg <="0000" AFTER 1.2 NS;
ELSE
cnt_reg <= cnt_reg + 1 AFTER 1.2 NS;
END IF;
END IF;
END PROCESS;
count <= cnt_reg;
END ARCHITECTURE procedural;

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Finite State Machines

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 FSMs in VHDL

• Finite State Machines Can Be Easily

Described With Processes

• Synthesis Tools Understand FSM Description

If Certain Rules Are Followed
• State transitions should be described in a process
sensitive to clock and asynchronous reset signals only

• Outputs described as concurrent statements outside

the process
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Finite State Machines (FSMs)

• Any Circuit with Memory Is a Finite State

Machine
– Even computers can be viewed as huge FSMs

• Design of FSMs Involves

– Defining states
– Defining transitions between states
– Optimization / minimization

• Above Approach Is Practical for Small FSMs

Only
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 Moore FSM

• Output Is a Function of a Present State Only

Inputs Next State

function
Next State Present State
clock Present State
reset Register

Output Outputs
function
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Mealy FSM

• Output Is a Function of a Present State and Inputs

Inputs Next State

function
Next State Present State
clock Present State
reset Register

Output Outputs
function
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 Moore Machine

transition
condition 1

state 1 / state 2 /
output 1 output 2
transition
condition 2

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Mealy Machine

transition condition 1 /
output 1

state 1 state 2
transition condition 2 /
output 2

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 Moore vs. Mealy FSM (1)

• Moore and Mealy FSMs Can Be Functionally

Equivalent
– Equivalent Mealy FSM can be derived from Moore
FSM and vice versa

• Mealy FSM Has Richer Description and

Usually Requires Smaller Number of States
– Smaller circuit area

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Moore vs. Mealy FSM (2)

• Mealy FSM Computes Outputs as soon as

Inputs Change
– Mealy FSM responds one clock cycle sooner than
equivalent Moore FSM

• Moore FSM Has No Combinational Path

Between Inputs and Outputs
– Moore FSM is more likely to have a shorter critical
path
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 Moore FSM - Example 1

• Moore FSM that Recognizes Sequence “10”

0 1
0
1
S0 / 0 S1 / 0 1 S2 / 1

reset
0
S0: No S1: “1” S2: “10”
Meaning elements observed observed
of states: of the
sequence
observed
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Mealy FSM - Example 1

• Mealy FSM that Recognizes Sequence “10”

0/0 1/0 1/0

S0 S1

reset 0/1
S0: No S1: “1”
Meaning elements observed
of states: of the
sequence
observed
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 Moore & Mealy FSMs – Example 1

clock
0 1 0 0 0
input

S0 S1 S2 S0 S0
Moore
S0 S1 S0 S0 S0
Mealy

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Finite State Machines

in VHDL

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 FSMs in VHDL

• Finite State Machines Can Be Easily

Described With Processes
• Synthesis Tools Understand FSM Description
If Certain Rules Are Followed
• State transitions should be described in a process
sensitive to clock and asynchronous reset signals only
• Outputs described as concurrent statements outside
the process

9/11/2022 Duy-Hieu Bui & Xuan-Tu Tran 35

Moore FSM

process(clock, reset)

Inputs Next State

function
Next State

clock Present State Present State

reset Register

concurrent Output Outputs

statements function
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 Mealy FSM

process(clock, reset)
Inputs Next State
function
Next State Present State
clock Present State
reset Register

Output Outputs
concurrent function
statements
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Moore FSM - Example 1

• Moore FSM that Recognizes Sequence “10”

0 1
0
1
S0 / 0 S1 / 0 1 S2 / 1

reset
0

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 Moore FSM in VHDL (1)

TYPE state IS (S0, S1, S2);

SIGNAL Moore_state: state;

U_Moore: PROCESS (clock, reset)

BEGIN
IF(reset = ‘1’) THEN
Moore_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Moore_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Moore_state <= S1;
ELSE
Moore_state <= S0;
END IF;

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Moore FSM in VHDL (2)

WHEN S1 =>
IF input = ‘0’ THEN
Moore_state <= S2;
ELSE
Moore_state <= S1;
END IF;
WHEN S2 =>
IF input = ‘0’ THEN
Moore_state <= S0;
ELSE
Moore_state <= S1;
END IF;
END CASE;
END IF;
END PROCESS;
Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;

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 Mealy FSM - Example 1

• Mealy FSM that Recognizes Sequence “10”

0/0 1/0 1/0

S0 S1

reset 0/1

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Mealy FSM in VHDL (1)

TYPE state IS (S0, S1);

SIGNAL Mealy_state: state;

U_Mealy: PROCESS(clock, reset)

BEGIN
IF(reset = ‘1’) THEN
Mealy_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THEN
CASE Mealy_state IS
WHEN S0 =>
IF input = ‘1’ THEN
Mealy_state <= S1;
ELSE
Mealy_state <= S0;
END IF;

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 Mealy FSM in VHDL (2)

WHEN S1 =>
IF input = ‘0’ THEN
Mealy_state <= S0;
ELSE
Mealy_state <= S1;
END IF;
END CASE;
END IF;
END PROCESS;

Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;

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State Machine Coding

A Moore Machine
Sequence Detector
The State in which
the 110 sequence is
States are named: detected.
0 s0 , s1 , s2 , s3 1
reset
1 1 0
S0 S1 S2 S3
0 0 0 0 1
1
Initia
l 0
State It Takes at least
3 clock periods to
get to the s3 state
▪ A Moore Sequence Detector

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 Moore Machine VHDL Code

ENTITY detector110 IS WHEN S1 =>

PORT (a, clk, reset : IN std_logic; w : IF a='1' THEN current <= S2;
OUT std_logic); ELSE current <= S0; END IF;
END ENTITY; WHEN S2 =>
-- IF a='1' THEN current <= S2;
ARCHITECTURE procedural OF ELSE current <= S3; END IF;
detector110 IS WHEN S3 =>
TYPE state IS (S0, S1, S2, S3); IF a='1' THEN current <= S1;
SIGNAL current : state := S0; ELSE current <= S0; END IF;
BEGIN WHEN OTHERS => current <=
PROCESS (clk) BEGIN S0;
IF (clk = '0' AND clk'EVENT) THEN END CASE;
IF reset = '1' THEN current <= S0; END IF;
ELSE END IF;
CASE current IS END PROCESS;
WHEN S0 => w <= '1' WHEN current = S3 ELSE '0';
IF a='1' THEN current <= S1; END ARCHITECTURE procedural;
ELSE current <= S0; END IF;

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State machine synthesis

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 Writing Testbenches

ENTITY detector110_tester IS END ENTITY;

--
ARCHITECTURE timed OF detector110_tester IS
SIGNAL aa, clock, rst, ww : std_logic := '0';
BEGIN
UUT1: ENTITY WORK.detector110 (procedural)
PORT MAP (aa, clock, rst, ww);
rst <= '1' AFTER 31 NS, '0' AFTER 54 NS;
clock <= NOT clock AFTER 7 NS WHEN NOW<=165 NS ELSE '0';
PROCESS BEGIN
WAIT FOR 23 NS; aa <= '1';
WAIT FOR 21 NS; aa <= '0';
WAIT FOR 19 NS; aa <= '1';
WAIT FOR 31 NS; aa <= '0';
WAIT;
END PROCESS;
PROCESS (ww) BEGIN
REPORT "Signal w changed to:"& std_logic'IMAGE(ww)&
" at " & TIME'IMAGE(NOW)
SEVERITY NOTE;
END PROCESS;
END ARCHITECTURE timed;

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Writing Testbenches

Testbench Waveform Results

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