UNIT-6

CPU Organization
All Questions are IMP
Explain about General register organization with proper diagram.
Generally CPU has seven general registers. Register organization show how registers are
selected and how data flow between register and ALU. A decoder is used to select a
particular register.The output of each register is connected to two multiplexers to form the
two buses A and B. The selection lines in each multiplexer select the input data for the
particular bus.
The A and B buses form the two inputs of an ALU.The operation select lines decide the
micro operation to be performed by ALU. The result of the micro operation is available at
the output bus. The output bus connected to the inputs of all registers, thus by selecting a
destination register it is possible to store the result in it.

A bus organization for seven CPU register

EXAMPLE:
•To perform the operation R3 = R1+R2 We have to provide following binary selection
variable to the select inputs.
1.SEL A : 001 -To place the contents of R1 into bus A.
2.SEL B : 010 - to place the contents of R2 into bus B
3.SEL OPR : 10010 – to perform the arithmetic addition A+B
4.SEL REG or SEL D : 011 – to place the result available on output bus in R3.
Register and multiplexer input selection code

SEL-D or
Binary code SELA SELB SEL-REG

000 Input Input ---

001 R1 R1 R1

010 R2 R2 R2

011 R3 R3 R3

100 R4 R4 R4

101 R5 R5 R5

110 R6 R6 R6

111 R7 R7 R7
Operation with symbol

Operation
selection code Operation symbol

0000 Transfer A TSFA

0001 Increment A INC A

0010 A+B ADD

0011 A-B SUB

0100 Decrement A DEC

0101 A AND B AND

 0110 A OR B OR

0111 A XOR B XOR

1000 Complement A COMA

1001 Shift right A SHR

1010 Shift left A SHL

What is stack? Give the organization of register stack with all necessary
elements and explain the working of push and pop operations.?
Stack: It is a useful feature that is included in the CPU which follows the LIFO principle(Last
In First Out).It is a storage device that stores info in such a manner that the item stored last
is the first item retrieved.
Register Stack: A stack register is a computer central processor register whose purpose is
to keep track of a call stack. It can be placed in a portion of a large memory or it can be
organized as a collection of a finite number of memory words or registers.

Stack Pointer: It is the register that holds the address for the stack,because it’s value
always points at the top of stack.

Operations of Stack:
1. Push: Operation of insertion in stack and increase the value of stack pointer by
Execution of Push Operation
SP<--SP+1 M[SP]<--DR if(SP==0) then FULL<--1 EMTY<--0
2. Pop: Operation of deletion in stack and it decreases the value of stack pointer by1.
Execution of Pop Operation
DR<--M[SP] SP<--SP-1 if(SP==0) then EMTY<--1 FULL<--0

What is a memory stack? Explain its role in managing subroutines

with the help of neat diagrams.
Memory Stack:
A stack can be implemented in a RAM attached to a CPU, the implementation of stack
is done by assigning a portion of memory to a stack operation, and using a processor
register as a stack pointer. Computer memory is partitioned into 3 parts namely:
1.Program
2.Data
3.Stack
What is Stack Organization? Explain Memory Stack Organization

Stack Organization
The Last In First Out (LIFO) list is another name for stack. It is the CPU's most
crucial feature. It saves information so that the last element saved is retrieved first. A
memory space with an address register is called a stack. This register, known as the
Stack Pointer, affects the stack's address (SP). The address of the element at the
top of the stack is continuously influenced by the stack pointer.
Memory Stack Organization
 A stack can exist as a stand-alone unit as in Fig. 3 or can be implemented in a random-access memory
attached to a CPU. The implementation of a stack in the CPU is done by assigning a portion of memory
to a stack operation and using a processor register as a stack pointer.
 Figure 4 shows a portion of computer memory partitioned into three segments: program, data, and stack.
The program counter PC points at the address of the next instruction in the program. The address register
AR points at an array of data.
 The stack pointer SP points at the top of the stack. The three registers are connected to a common
address bus, and either one can provide an address for memory.
 PC is used during the fetch phase to read an instruction. AR is used during the execute phase to read
an operand.
 SP is used to push or pop items into or the stack. As shown in Fig. 4, the initial value of SP is 4001
and the stack grows with decreasing addresses.
 Thus the first item stored in the stack is at address 4000, the second item is stored at address 3999,
and the last address that can be used for the stack Is 3000.
 No provisions are available for stack limjt checks.

 We assume that the items in the stack communicate with a data register DR . A new item is inserted
with the push operation as follows:

 SP ← SP - 1

 M[SP] ← DR

 The stack pointer is decremented so that it points at the address of the next word. A memory write
operation inserts the word from DR into the top of the stack. A new item is deleted with a pop operation
as follows:

 DR ← M[SP]

 SP ← SP + 1
  The top item is read from the stack into DR. The stack pointer is then incremented to point at the next
item in the stack.
 Most computers do not provide hardware to check for stack overflow (full stack) or underflow (empty
stack).
 The stack limits can be checked by using two processor registers: one to hold the upper limit (3000 in
this case), and the other to hold the lower limit (4001 in this case).
 After a push operation, SP is compared with the upper-limit register and after a pop operation, SP is
compared with the lower-limit register.
 The two microoperations needed for either the push or pop are (1) an access to memory through SP,
and (2) updating SP. Which of the two microoperations is done first and whether SP is updated by
incrementing or decrementing depends on the organization of the stack.
 In Fig. 4 the stack grows by decreasing the memory address. The stack may be constructed to grow by
increasing the memory address as in Fig. 3.
 In such a case, SP is incremented for the push operation and decremented for the pop operation. A
stack may be constructed so that SP points at the next empty location above the top of the stack.
 In this case the sequence of microoperations must be interchanged. A stack pointer is loaded with an
initial value. This initial value must be the bottom address of an assigned stack in memory. Henceforth,
SP is automatically decremented or incremented with every push or pop operation.
 The advantage of a memory stack is that the CPU can refer to it without having to specify an address,
since the address is always available and automatically updated in the stack pointer.

Compare Register stack and Memory Stack

Explain in detail the different instruction formats with examples
Computer perform task on the basis of instruction provided. A instruction in computer
comprises of groups called fields. These field contains different information as for
computers every thing is in 0 and 1 so each field has different significance on the basis of
which a CPU decide what so perform. The most common fields are:
 Operation field which specifies the operation to be performed like addition.
 Address field which contain the location of operand, i.e., register or memory location
 Mode field which specifies how operand is to be founded.
A instruction is of various length depending upon the number of addresses it contain.
Generally CPU organization are of three types on the basis of number of address fields:
1. Single Accumulator organization
2. General register organization
3. Stack organization
In first organization operation is done involving a special register called accumulator. In
second on multiple registers are used for the computation purpose. In third organization
the work on stack basis operation due to which it does not contain any address field. It is
not necessary that only a single organization is applied a blend of various organization is
mostly what we see generally.
On the basis of number of address instruction are classified as:
Note that we will use X = (A+B)*(C+D) expression to showcase the procedure

1. Zero Address Instructions –

A stack based computer do not use address field in instruction. To evaluate a expression first
it is converted to revere Polish Notation i.e. Post fix Notation.
2. One Address Instructions – This use a implied ACCUMULATOR register for data
manipulation.One operand is in accumulator and other is in register or memory
location.Implied means that the CPU already know that one operand is in accumulator
so there is no need to specify it
3. One Address Instructions – This use a implied ACCUMULATOR register for data
manipulation.One operand is in accumulator and other is in register or memory
location.Implied means that the CPU already know that one operand is in
accumulator so there is no need to specify it
4. Three Address Instructions – This has three address field to specify a register or
a memory location. Program created are much short in size but number of bits per
instruction increase. These instructions make creation of program much easier but it
does not mean that program will run much faster because now instruction only
contain more information but each micro operation (changing content of register,
loading address in address bus etc.) will be performed in one cycle only.
Explain an accumulator based central processing unit organization with block
diagram
Wright down the difference between RISC and CISC Computer

S.No. RISC CISC

It stands for Reduced Instruction It stands for Complex Instruction Set

1.
Set Computer. Computer.

It is a microprocessor architecture This offers hundreds of instructions of

2. that uses small instruction set of different sizes to the users.
uniform length.

These simple instructions are This architecture has a set of special

3. executed in one clock cycle. purpose circuits which help execute the
instructions at a high speed.

These chips are relatively simple to These chips are complex to design.
4.
design.

5. They are inexpensive. They are relatively expensive.

Examples of RISC chips include Examples of CISC include Intel

6.
SPARC, POWER PC. architecture, AMD.

7. It has less number of instructions. It has more number of instructions.

It has fixed-length encodings for It has variable-length encodings of

8.
instructions. instructions.

Simple addressing formats are The instructions interact with memory

9.
supported. using complex addressing modes.

It doesn't support arrays. It has a large number of instructions. It

10.
supports arrays.

11. It doesn't use condition codes. Condition codes are used.

Registers are used for procedure The stack is used for procedure
12.
arguments and return addresses. arguments and return addresses.
What is Interrupt in Computer? Explain various types of Interrupts?
An interrupt is a signal from a device attached to a computer or from a program
within the computer that requires the operating system to stop and figure out
what to do next.
Interrupt systems are nothing but while the CPU can process the programs if the
CPU needs any IO operation. Then, it is sent to the queue and it does the CPU
process. Later on Input/output (I/O) operation is ready.
The I/O devices interrupt the data which is available and does the remaining
process; like that interrupts are useful. If interrupts are not present, the CPU
needs to be in idle state for some time, until the IO operation needs to complete.
So, to avoid the CPU waiting time interrupts are coming into picture.
Types of interrupts
There are two types of interrupts which are as follows −
Hardware interrupts
The interrupt signal generated from external devices and i/o devices are made interrupt to
CPU when the instructions are ready.
For example − In a keyboard if we press a key to do some action this pressing of the keyboard
generates a signal that is given to the processor to do action, such interrupts are called
hardware interrupts.
Hardware interrupts are classified into two types which are as follows −
 Maskable Interrupt − The hardware interrupts that can be delayed when a
highest priority interrupt has occurred to the processor.
 Non Maskable Interrupt − The hardware that cannot be delayed and
immediately be serviced by the processor.
Software interrupts
The interrupt signal generated from internal devices and software programs need to access
any system call then software interrupts are present.
Software interrupt is divided into two types. They are as follows −
 Normal Interrupts − The interrupts that are caused by the so ware instructions
are called software instructions.
 Exception − Excep on is nothing but an unplanned interrup on while execu ng
a program. For example − while execu ng a program if we got a value that is
divided by zero is called an exception.
Explain Interrupt Cycle

 An instruction cycle (sometimes called fetch-and-execute cycle, fetch-decode-execute

cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a
computer retrieves a program instruction from its memory, determines what actions
the instruction requires, and carries out those actions. This cycle is repeated
continuously by the central processing unit (CPU), from bootupto when the computer
is shut down.

Block diagram of Interrupt Cycle

 After the execute cycle is completed, a test is made to determine if an interrupt was
enabled (e.g. so that another process can access the CPU)
 If not, instruction cycle returns to the fetch cycle
 If so, the interrupt cycle might performs the following tasks: (simplified...)
 move the current value of PC into MBR
 move the PC-save-address into MAR
 move the interrupt-routine-address into PC
 move the contents of the address in MBR into indicated memory cell
 continue the instruction cycle within the interrupt routine
 after the interrupt routine finishes, the PC-save-address is used to reset the value of
PC and program execution can continue
 Numerical
Consider a processor with 64 registers and an instruction set of size twelve. Each
instruction has five distinct fields, namely, opcode, two source register
identifiers, one destination register identifier, and a twelve-bit immediate
value. Each instruction must be stored in memory in a byte-aligned fashion. If a
program has 100 instructions, the amount of memory (in bytes) consumed by
the program text is ____________.
(A) 100
(B) 200
(C) 400
(D) 500

Solution: It can be approached as:

The instruction consists of opcode and operands. Given the instruction set of size 12, 4 bits
are required for opcode (2^4 = 16).
As there are total 64 registers, 6 bits are required for identifying a register.
As the instruction contains 3 registers (2 source + 1 designation), 3 * 6 = 18 bit are required
for register identifiers.
12 bits are required for immediate value as given.
Total bits for an instruction = 4 + 18 + 12 = 34 bits
The instructions are required to be stored in a byte-aligned fashion. The nearest byte
boundary after 34 bits is at 40 bits (5 bytes).
Hence, for 100 instructions, the memory required is 5 * 100 = 500 bytes, and the correct
option is (D).
A machine has a 32-bit architecture, with 1-word long instructions. It has 64
registers, each of which is 32 bits long. It needs to support 45 instructions, which
have an immediate operand in addition to two register operands. Assuming
that the immediate operand is an unsigned integer, the maximum value of the
immediate operand is ___________.
Solution: It can be approached as:
As machine has 32-bit architecture, therefore, 1 word = 32 bits = instruction size
As the processor has 64 register, number of bits for one register = 6 (2^6 = 64)
As the processor has 45 instructions, number of bits for opcode = 6 (2^6 = 64)
Total bits occupied by 2 registers and opcode = 6 + 6 + 6 =18.
As instruction size given is 32 bits, remaining bit left for immediate operand = 32-18 = 14 bits.
Maximum unsigned value using 14 bits = 2^14 – 1 = 16383 which is the answer.