System Synthesis - Introduction

System Synthesis of Digital Systems

Petru Eles, Zebo Peng

System Synthesis - Introduction

Literature: P. Eles, K. Kuchcinski and Z. Peng "System Synthesis with VHDL" Kluwer Academic Publisher, December 1997.

Introduction

1. Digital System Synthesis 2. Lecture Topics 3. Specification Domains and the Abstraction Hierarchy 4. The Y-Chart 5. Synthesis Steps

Examination: Term paper Seminar presentation

6. High Level Synthesis

Petru Eles, IDA, LiTH

March 2000

Petru Eles, IDA, LiTH

March 2000

System Synthesis - Introduction

System Synthesis - Introduction

Whats About?

Why Is This an Issue?

 Its about (automatic) synthesis of digital systems.  A digital system (for this course) Consists of programmable processors and dedicated hardware (application specic integrated circuits - ASICs). Performs a well-dened task.  In this course there will be more emphasis on the specication and synthesis of the hardware part (the ASIC).

Complexity: new computer aided methodologies are needed in the context of increasing complexity (SoC).

Verication: starting from a (formal) system specication which is validated, and performing well dened design steps (transformations) with veriable outputs.

Time to market: only efcient tools and reuse can bring design productivity up to the expected level.

Petru Eles, IDA, LiTH

March 2000

Petru Eles, IDA, LiTH

March 2000

System Synthesis - Introduction

System Synthesis (contd)

System specication Arch. Selection & Partitioning Partitioned model Scheduling Part. model& Schedule Communication Synthesis Software model Hardw./Softw. Cosimulation Hardware model Hardw./Softw. Cosimulation Hardw./Softw. Cosimulation Simulation

System Synthesis - Introduction

System Synthesis
Input: an implementation independent specication of the system; this includes: functionality and constraints. The synthesis tasks: To select the architecture; To partition functionality over the components of the architecture; To schedule activities To generate behavioral modules corresponding to the hardware and software domain of the implementation, including interface modules.

- The behavioral modules resulted from the previous steps are further synthesised into the actual hardware and/or software implementation.

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March 2000

Software Generation Software blocks Hardw./Softw. Cosimulation Emulation& Prototyping Product Fabrication
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Hardware Synthesis Hardware blocks

March 2000

System Synthesis - Introduction

Lecture Topics and Schedule

1. Introduction and Course Overview. System Synthesis and High-Level Synthesis. - Thursday March 23, 10-12. 2. VHDL - Basics and Simulation Mechanism. - Thursday April 6, 10-12. 3. High-Level Synthesis. - Thursday April 13, 10-12. 4. Basics of Transformational Approach. - Thursday April 20, 10-12. 5. Optimization Heuristics for Synthesis. - Thursday April 27, 10-12. 6. System-Level Synthesis and HardwareSoftware Partitioning - I. - Thursday May 11, 10-12. 7. System-Level Synthesis and HardwareSoftware Partitioning - II. - Thursday May 18, 10-12. 8. Synthesis of Advanced Features. - Wednesday May 31, 10-12. 9. High-Level Synthesis for Testability. - Thursday June 8, 10-12. 10.Presentation of Term Papers. - Thursday June 15, 10-??.
Petru Eles, IDA, LiTH March 2000

System Synthesis - Introduction

System Synthesis (contd)

System specification Compilation Partitioning Simulation Verification Internal design representation Communic. synthesis Behavioral modules Hardware synthesis Software synthesis Architecture selection Estimation Scheduling Architecture model Component library (IP, COTS)

IMPLEMENTATION

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March 2000

System Synthesis - Introduction

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Digital Systems - The Abstraction Hierarchy

System Synthesis - Introduction

System level: The specication is given as a set of subsystems (modules/processes) which are loosely interacting (e.g. by exchanging messages). The basic structural elements are processors, communication channels, ASICs, memories.

Digital Systems - Specication Domains

Functional Domain: emphasis is on behavior (input - output functionality), without any reference to the particular way in which this behavior is implemented. Structural Domain: the specication is in terms of hierarchy of interconnected functional components. Physical/Geometrical Domain: the specication is in terms of physical placement in space and physical characteristics without any elements to functionality.

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Algorithmic level (behavioral level): The specication is given as an algorithm describing the functionality. repeat xl = x + dx; ul = u - (3 * x * u * dx) - (3 * y * dx); yl = y + u * dx; c = xl < a; x = xl; u = ul; y = yl; until (c); The basic structural elements are controller and net-list.

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The Abstraction Hierarchy (contd) Register-transfer level: Operations described as transfer of values between registers and functional units.
System Synthesis - Introduction 12

a 3 dx x y u r1 r2

The Abstraction Hierarchy (contd) Logic level: Operations are described as boolean equations. The basic structural elements are gates and their interconnections.

validate

control multiplex. control ALU c

Circuit level: Differential equations dene relations between signal voltage, current response, etc. The system is described in terms of transistors, resistors, capacitors.

ALU

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March 2000

The basic structural elements are registers, ALUs, multiplexers and controller.

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March 2000

System Synthesis - Introduction

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Y-Chart

System Synthesis - Introduction

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Behavioral Domain
System Spec. Algorithm Reg.-Transf. Spec.

System level Algorithmic level RT level Logic level

Structural Domain
CPU,Memory Controller, Net-list ALU, Reg., MUX

Y-Chart

 A representation proposed by Gajski, in order to capture specication domains, abstraction levels and their inter-relation. Specication domains are represented as the three axes; In each domain, the specication can be at different abstraction levels. These levels are represented as points on the respective axes.  The Y-chart also tries to capture the relation between different design activities (synthesis, analysis, renement, etc.)

Gate, Flip-flop Circuit Transistor functions level Transistor

Boolean Equ.

Transistor layouts Standard-Cell Macro-Cell Block/Chip

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March 2000

Chip, Board, MCM

Physical/Geometrical Domain

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March 2000

System Synthesis - Introduction

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System Synthesis - Introduction

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Y-Chart and Design Activities

Top-Down Synthesis in the Y_Chart

Behavioral Domain

Synthesis Analysis

Structural Domain

Behavioral Domain
System Spec. Algorithm

1 2

Structural Domain
CPU,Memory

3 4

Controller, Net-list ALU, Reg., MUX Gate, Flip-flop Transistor

Renement

Optimization

Reg.-Transf. Spec. Boolean Equ.

Abstraction Generation

Transistor functions

5
Extraction

1: System level synthesis 2: High level synthesis 3: RT level synthesis 4: Logic synthesis 5: Physical design

Transistor layouts Standard-Cell Macro-Cell Block/Chip Chip, Board, MCM

Physical/Geometrical Domain

Physical/Geometrical Domain

Petru Eles, IDA, LiTH

March 2000

Petru Eles, IDA, LiTH

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System Synthesis - Introduction

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System Synthesis - Introduction

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Synthesis Steps
Synthesis: Transformation of a representation in the behavioral domain to a representation of the same design in the structural domain (at the same abstraction level). The structural description which results after a synthesis step is formulated as an interconnection of abstract components. Each such component is functionally specied at the following, lower abstraction level. These functional specications are the input for the following synthesis step.

Synthesis Steps (contd) System synthesis Input: System level specication (interacting processes) + design constraints Output: Behavioral elements to be synthesised to hardware and software + System architecture + Process schedule and mapping

High level (behavioral) synthesis Input: Algorithmic description Output: RT level description of the controller (FSM) + net-list (data path)

Petru Eles, IDA, LiTH

March 2000

Petru Eles, IDA, LiTH

March 2000

System Synthesis - Introduction

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System Synthesis - Introduction

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Synthesis Steps (contd) RT level synthesis Input: RT level description of the controller (FSM) + net-list Output: Blocks of combinational and memory elements Logic synthesis Input: Blocks of combinational and memory elements (as boolean functions) Output: gate-level net-list Physical design Input: gate-level netlist Output: geometrical layout for a given technology

High Level Synthesis

Behavioural description Compilation Design representation Scheduling Allocation Binding RT level implementation

Petru Eles, IDA, LiTH

March 2000

Petru Eles, IDA, LiTH

March 2000

System Synthesis - Introduction

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System Synthesis - Introduction

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From Algorithm to Design Representation

Allocation and Binding

Allocate: 4 multipliers and two ALUs. Bind as follows:

u = u - (3 * x * u * dx) - (3 * y * dx); x = x + dx; y = y + u * dx; c = x < a;

0
NOP

0
NOP

3*x

u*dx y*dx 1 2 6 * * * 3 4 5 7

u*dx 8 * 9

x+dx 10 + 11

* 3

* 7

10

* 4 -

<

11

<

5 n

NOP NOP

Petru Eles, IDA, LiTH

March 2000

Petru Eles, IDA, LiTH

March 2000

System Synthesis - Introduction

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System Synthesis - Introduction

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Scheduling
Schedule the operations into clock cycles.
0
NOP

Scheduling (contd) A schedule of the same graph, considering one multiplier and one ALU.
0
NOP

TIME 1 TIME 1 * 1 * 3 4 5 TIME 4 TIME 5

NOP

10

* 7

10 TIME 2 * 2 < 11

TIME 2 TIME 3

<

11 TIME 3 * 3

TIME 4

6 7

n TIME 6

5 9

We considered each operation to take one clock cycle.

TIME 7
NOP

+ n

Petru Eles, IDA, LiTH

March 2000

Petru Eles, IDA, LiTH

March 2000

System Synthesis - Introduction

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System Synthesis - Introduction

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The Netlist
repeat xl = x + dx; ul = u - (3 * x * u * dx) - (3 * y * dx); yl = y + u * dx; c = xl < a; x = xl; u = ul; y = yl; until (c);
a 3 dx x y u r1 r2

The Controller
Suppose the following schedule (1 multiplier, 1 ALU):

0
NOP

v1 : 3*x -> r2 v10 : x+dx -> r1,x v2 : u*dx -> r1 v11 : r1<a -> c validate v3 : r2*r1 -> r2

10

<

11

control multiplex. control ALU c

v6 : 3*dx -> r2 v4 : u-r2 -> r1 v7 : r2*y -> r2 v8 : u*dx -> r2 v5 : r1-r2 -> u v9 : y+r2 -> y

6 7

ALU

5 9

+
NOP

n
March 2000

Petru Eles, IDA, LiTH

March 2000

Petru Eles, IDA, LiTH

System Synthesis - Introduction

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The Controller (contd) One state for each clock cycle In each state the signals are generated which are needed in order to execute the operations scheduled for that cycle (see schedule).

1,10 lk c s1

s2

2,11

clk
s3

clk, c

clk

clk

Petru Eles, IDA, LiTH

clk

clk

,c

s7

s4

6,4

clk

s6

5,8

7 s5

March 2000