HAMMING CODE:
ENCODER AND DECODER
By:
Marut Patel [22BEC088]
Department of Electronics and Communication Engineering
Semester – IV
2EC202 – FPGA based System Design
Special Assignment FPGA
INDEX
1. Objective
• Abstract
• Keywords
2. Literature Survey
• Hamming code
• Limitations
3. Methodology
4. Schematic diagram
5. Algorithm
• Flow of code
• Flowcharts
6. Result and Simulation
• RTL view
• TTL view
• Waveform
7. Conclusion
8. Appendix
• Verilog code
• FPGA implementation
❖ Objective:
The objective of this report is to understand and implement a Hamming code encoder and
decoder module in Verilog. The report aims to explore the principles of error detection and
correction using Hamming codes, focusing on a specific implementation. Through this,
readers will learn how to encode a 4-bit data input into a 7-bit codeword with added parity
bits, and then decode the received 7-bit message to detect and potentially correct errors. This
includes algorithmic details of the encoder and the decoder. By the end of this report, readers
will gain a practical understanding of Hamming codes and their application in error detection
and correction.
❖ Abstract:
This report presents a comprehensive analysis and implementation of Hamming Code
Encoder and Decoder using Verilog HDL. Hamming code is used for error detection and the
encoding decoding. The Verilog implementation discussed here is aims to provide a detailed
understanding of the encoding and decoding process, highlighting its significance in ensuring
data integrity. The emergence of Hamming code decoding greatly reduces the cost of forward
error correction, reduces the bit error rate of transmission, improves the ability of error
correction, and improves the reliability and stability of the system.
❖ Keywords:
Hamming Code, FPGA, Error Detection-Correction, Verilog, Encoder, Decoder, RTL, TTL,
Waveforms.
❖ Literature Survey:
Hamming codes, introduced by Richard W. Hamming in 1950, have been extensively
researched and implemented in various digital communication systems. Error-correcting
codes play a crucial role in various communication systems to ensure reliable data
transmission. Among these, Hamming codes are well-established and widely used due to
their simplicity and efficiency in error detection and correction.[1]
Existing literature on Hamming codes mainly focuses on their theoretical aspects,
implementation in hardware and software, and applications in communication systems. In
terms of implementation, there are various methodologies available, including hardware-
based solutions using digital logic design, software-based implementations, and combinations
of both. Verilog, a hardware description language (HDL), is commonly used for designing
digital systems, making it a suitable choice for implementing Hamming Code Encoder and
Decoder.
❖ Limitations:
While Hamming codes offer efficient error detection and correction capabilities, they have
certain limitations. One significant drawback is their inability to correct multiple errors
within the same code word. Additionally, the redundancy introduced by Hamming codes
increases with the length of the data word, leading to higher overhead in terms of bandwidth
and storage. Moreover, existing implementations of Hamming codes may suffer from
complexity, especially in hardware designs, which can impact performance and scalability.
Therefore, there is a need for efficient and scalable implementations of Hamming codes to
address these limitations.
❖ Methodology:
The proposed solution involves designing a Hamming Code Encoder and Decoder using
Verilog. The methodology includes developing modules for encoding and decoding
processes, adhering to the principles of Hamming codes.
The Encoder module takes an input data word, adds parity bits according to the Hamming
code algorithm, and generates the encoded output. On the other hand, the Decoder module
receives the encoded data word, detects and corrects errors using the parity bits, and produces
the decoded output. The design focuses on optimizing resource utilization and ensuring
scalability for different data word lengths.
Hamming(7,4) is a linear error-correcting code that encodes four bits of data into seven bits
by adding three parity bits.
Table 1: Construction of (7,4) binary Hamming code
As mentioned in table 1 (7, 4) Hamming code be represented by [D7,D6,D5,P4,D3,P2,P1],
where D represents information bits and P represents parity bits at respective bit positions.
The subscripts indicate the left to right position taken by the data and the parity bits. We note
that the parity bits are located at position that are powers of two.[2]
❖ Schematic diagrams:[3]
Figure 1: Hamming code encoding
Figure 2: Hamming code decoding
❖ Flow of code:
1. Encoding:
- The input data (4 bits) is used to calculate three parity bits (p1, p2, p3).
- Parity bit p1 is the XOR of data_in[0], data_in[1], and data_in[3].
- Parity bit p2 is the XOR of data_in[0], data_in[2], and data_in[3].
- Parity bit p3 is the XOR of data_in[1], data_in[2], and data_in[3].
- The encoded_data is formed by concatenating the parity bits and the input data in a
specific order: {p1, p2, data_in[0], p3, data_in[1], data_in[2], data_in[3]}.
2. Decoding:
- The received encoded_data is used to calculate three syndrome bits (x[0], x[1], x[2]).
- x[0] = encoded_data[0] ^ encoded_data[2] ^ encoded_data[4] ^ encoded_data[6]
- x[1] = encoded_data[1] ^ encoded_data[2] ^ encoded_data[5] ^ encoded_data[6]
- x[2] = encoded_data[3] ^ encoded_data[4] ^ encoded_data[5] ^ encoded_data[6]
- If any of these syndrome bits are non-zero, it indicates an error.
3. Error Detection:
- The error_detected output is set based on whether any of the syndrome bits are non-zero.
- If error_detected is 1, it means an error was detected in the received data.
❖ Hamming code encoding flow chart:
start
Input 4-bit data to be encoded
Calculate parity bits
Construct 7-bit encoded data
Output encoded data
end
❖ Hamming code decoding flow chart:
Input 7-bit received data
Calculate syndromes
If syndrome is
zero
Output decoded data
❖ RTL:
❖ TTL:
❖ Waveform:
❖ Conclusion:
In conclusion, the design and implementation of a Hamming Code Encoder and Decoder
using Verilog offer an efficient and scalable solution for error detection and correction in
digital communication systems. Hamming codes find applications in fields such as
computing, telecommunication services, like satellite communication, modems, embedded
processors, etc. By leveraging the principles of Hamming codes and the capabilities of
Verilog, the proposed methodology addresses the limitations of existing technologies and
provides a reliable mechanism for data integrity.
1) Advantages:
• Highly efficient for single-bit error correction.
• Easy encoding and decoding offer simplicity in error detection and correction.
2) Disadvantages:
• It is not suitable for correcting multiple error bits.
• The requirement of transmission bandwidth is high.
❖ References:
[1] "History of Hamming Codes"(Wikipedia)
[2] Hamming Code : construction, encoding & decoding. May 23,
2008 by Mathuranathan.
[3] Design of encoding and decoding of Hamming code based on VHDL Jing-jie Shan;
Jian Zhou
https://www.youtube.com/watch?v=8VXA021mHcM
❖ Appendix:
• Main code:
module hammingcode (
input [3:0] data_in,
output [6:0] encoded_data,
output [3:0] decoded_data,
output error_detected
);
// Parity bits
wire p1, p2, p3;
// Encoder
assign p1 = data_in[0] ^ data_in[1] ^ data_in[3];
assign p2 = data_in[0] ^ data_in[2] ^ data_in[3];
assign p3 = data_in[1] ^ data_in[2] ^ data_in[3];
assign encoded_data = {p1, p2, data_in[0], p3, data_in[1], data_in[2], data_in[3]};
// Decoder
wire [6:0] x;
wire error;
wire [3:0] corrected_data;
assign x[0] = encoded_data[0] ^ encoded_data[2] ^ encoded_data[4] ^ encoded_data[6];
assign x[1] = encoded_data[1] ^ encoded_data[2] ^ encoded_data[5] ^ encoded_data[6];
assign x[2] = encoded_data[3] ^ encoded_data[4] ^ encoded_data[5] ^ encoded_data[6];
assign error = x;
assign decoded_data = encoded_data[2:0];
assign error_detected = error;
endmodule
❖ FPGA implementation result:
