Faculty of Computing and Informatics

Top-level view of Computer function and interconnections

Faculty of Computing and Informatics

Objectives of the Lecture

:-

▪ Computer components
▪ Computer function
▪ Interconnection structures
▪ Bus interconnection
▪ Point-to-point interconnection
▪ PCI Express
Lecture Objectives
At the end of this lecture, we should be able to:-

➢ Describe the concept of interconnection within a computer

system.

➢ Explain the need for multiple buses arranged in hierarchy.

➢ Assess the relative advantages of point-to-point

interconnection compared to bus interconnection.

➢ Present an overview of PCIe.

+ Computer Components

• Contemporary computer designs are based on concepts

developed by John von Neumann at the Institute for
Advanced Studies(IAS), Princeton in 1945

• Referred to as the von Neumann architecture and is based

on three key concepts:
– Data and instructions are stored in a single read-write memory
– The contents of this memory are addressable by location,
without regard to the type of data contained there
– Execution occurs in a sequential fashion (unless explicitly
modified) from one instruction to the next

– Hardwired program
– The result of the process of connecting the various components
in the desired configuration

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The Von Neumann Architecture
 Faculty of Computing and Informatics

Group Discussion (pair up in groups of 2 and carry out this task )

Based on the Video Clip you just watched, take 2 minutes to answer the
following questions:-

1. List the five components of the Von-Neumann architecture.

2. From the user input to the computer, how is data handled?
3. What is the function of the ALU?
4. What is the relationship between the Control unit and other
computer components.
5. Data transfer between the processor and memory is controlled by?
6. The Von Neumann architecture, uses stored program concept.
What is stored program concept?
Software
• A sequence of codes or instructions
• Part of the hardware interprets each instruction and Software
generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware

Major components:
• CPU I/O
• Instruction interpreter Components
• Module of general-purpose arithmetic and logic
functions
• I/O Components
➢Input module
➢Contains basic components for accepting data and
instructions and converting them into an internal
form of signals usable by the system
➢Output module
➢Means of reporting results
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 Action Categories
• Data transferred • Data transferred
from processor to to or from a
memory or from peripheral device
memory to by transferring
processor between the
processor and an
I/O module
Processor- Processor-
memory I/O

Data
Control
processing
• An instruction • The processor
may specify that may perform
the sequence of some arithmetic
execution be or logic operation
altered on data
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+
I/O Function
• I/O module can exchange data directly
with the processor

• Processor can read data from or write

data to an I/O module

• In some cases it is desirable to allow I/O

exchanges to occur directly with memory

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NJ. All rights reserved.
The interconnection structure must support the following
types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory
An I/O
module is
allowed to
exchange
Processor data directly
Processor
reads an Processor Processor with
reads data
instruction writes a unit sends data memory
from an I/O
or a unit of of data to to the I/O without
device via an
data from memory device going
I/O module
memory through the
processor
using direct
memory
access

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 A communication Signals transmitted by any one
device are available for reception
pathway connecting two by all other devices attached to
or more devices the bus
• Key characteristic is that it is a
shared transmission medium
• If two devices transmit during the same
time period their signals will overlap and
become garbled
I n
n n
Typically consists of
multiple communication
lines
Computer systems contain a
number of different buses that
provide pathways between
B t e
• Each line is capable of components at various levels of
transmitting signals
representing binary 1 and
binary 0
the computer system hierarchy
u e c
s r t
The most common
System bus computer
• A bus that connects interconnection c i
major computer structures are based on
components (processor, the use of one or more
memory, I/O) system buses o o
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 Data Bus
• Data lines that provide a path for moving data among
system modules

• May consist of 32, 64, 128, or more separate lines

• The number of lines is referred to as the width of the

data bus

• The number of lines determines how many bits can

be transferred at a time

• The width of the data bus is a key factor in

determining overall system performance

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NJ. All rights reserved.
 Address Bus Control Bus

• Used to designate the source or • Used to control the access and the
destination of the data on the use of the data and address lines
data bus
– If the processor wishes to read a
word of data from memory it puts • Because the data and address lines
the address of the desired word are shared by all components there
on the address lines must be a means of controlling their
use
• Width determines the
maximum possible memory • Control signals transmit both
capacity of the system command and timing information
among system modules
• Also used to address I/O ports
• Timing signals indicate the validity of
– The higher order bits are used to data and address information
select a particular module on the
bus and the lower order bits
select a memory location or I/O • Command signals specify operations
port within the module to be performed
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 Bus Interconnection Scheme

CPU Memory Memory I/O I/O

Control lines

Address lines Bus

Data lines

Figure 3.16 Bus Interconnection Scheme

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NJ. All rights reserved.
+ Peripheral Component Interconnect
(PCI)
• A popular high bandwidth, processor independent bus that
can function as a mezzanine or peripheral bus

• Delivers better system performance for high speed I/O

subsystems

• PCI Special Interest Group (SIG)

– Created to develop further and maintain the compatibility of the
PCI specifications
– PCI Express (PCIe)
– Point-to-point interconnect scheme intended to replace bus-based schemes such as PCI
– Key requirement is high capacity to support the needs of higher data rate I/O devices, such as Gigabit
Ethernet
– Another requirement deals with the need to support time dependent data streams

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NJ. All rights reserved.
+ Point to Point Interconnect
❑ Quick Path Interconnect (QPI)
❑ PCIe
• The Intel QPI is a point-to point processor interconnect developed
by Intel which replaced the front-side bus (FSB) in Xeon, Itanium,
and certain desktop platforms starting in 2008

• PCIe is a point-to-point interconnect intended to replace both PCI

(a general-purpose system bus) and AGP (a bus used for graphics
cards). It is based on the concept of lanes, which work by analogy
to lanes on a highway. A single physical slot that you plug a card
into may have between 1 and 32 lanes
+
Point-to-Point Interconnect
At higher and higher data
Principal reason for change
rates it becomes increasingly
was the electrical constraints
difficult to perform the
encountered with increasing
synchronization and
the frequency of wide
arbitration functions in a
synchronous buses
timely fashion

A conventional shared bus

on the same chip magnified
Has lower latency, higher
the difficulties of increasing
data rate, and better
bus data rate and reducing
scalability
bus latency to keep up with
the processors

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NJ. All rights reserved.
 I/O device

I/O device
I/O Hub

DRAM

DRAM
Core Core
A B

DRAM

DRAM
Core Core
C D
I/O device

I/O device
I/O Hub

QPI PCI Express Memory bus

Figure 3.17 Multicore Configuration Using QPI

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NJ. All rights reserved.
 Core Core

Gigabit PCIe
Memory
Ethernet
Chipset
PCIe–PCI PCIe
Memory
Bridge

PCIe

PCIe PCIe
Switch

PCIe PCIe

Legacy PCIe PCIe PCIe

endpoint endpoint endpoint endpoint

Figure 3.21 Typical Configuration Using PCIe

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NJ. All rights reserved.
Summary
▪ Bus Interconnection structures
• Van Neuman
▪ Peripheral System Interconnect
✓ General purpose Vs
Hardwired ✓ Shared bus
✓ Point to Point
✓ PCIe
✓ QPI

✓ Engage Discussion
Forum
✓ Complete Lab1 week

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NJ. All rights reserved.
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Faculty of Computing and Informatics

Thank You.