10/9/2023

EE 3007 SoC Design

Datapath Components

Datapath Components

 N-bit muxes
 Multifunction Register
 Shifters
 Counters
 Timers
 Register files

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Datapath Components
N-bit Mux
 Example: Two 4-bit inputs, A (a3 a2 a1 a0), and B (b3 b2 b1 b0)
 4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can select between A or B

2x1
a3 i0 Simplifying
d
b3 i1 notation:
s0
4-bit 4
2x1 4 C
a2 i0 2x1
d A I0 4
b2 i1 D C is short
s0 4
B I1 for
2x1
a1 i0 s0
d
b1 i1 c3
s0
s0 c2
i0 2x1
a0
d c1
b0 i1
s0
s0 c0

Datapath Components
N-bit Mux Example

From the car's central 8-bit a

computer 8
T I0 4x1

A 8
I1 8 D To the
I 8 D above-mirror
I2
display
M 8
I3
s1 s0
x y
We will design
this later

button

 Four possible display items

 Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles
remaining (M) – each is 8-bits wide
 Choose which to display on D using two inputs x and y
 Pushing button sequences to the next item
 Use 8-bit 4x1 mux

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Datapath Components
Registers

 N-bit register: Stores N bits, N is the width b x

Combinational n1
 Can store data, very common in datapaths logic
n0
 Common widths: 8, 16, 32 s1 s0
 Storing data into register: Loading clk State register
 Opposite of storing: Reading (does not alter contents)

 Basic register: Loaded every cycle

a
 Useful for implementing FSM -- stores encoded state
 For other uses, may want to load only on certain cycles

I3 I2 I1 I0

4-bit register
load I3 I2 I1 I0
D D D D reg(4)
Q Q Q Q
Q3 Q2 Q1 Q0
clk

Q3 Q2 Q1 Q0

Basic register loads on every clock cycle

How to extend to only load on certain cycles? 5

Datapath Components
Register with Parallel Load

 Add 2x1 mux to front of each flip-flop

 Register’s load input selects mux input to pass
 Either existing flip-flop value, or new value to load
I3 I2 I1 I0

1 0 1 0 1 0 1 0
load 2x1
2mux
1 I3 I2 I1 I0
load
D D D D
Q3 Q2 Q1 Q0
Q Q Q Q

Q3 Q2 Q1 Q0
(a) (c)

I3 I2 I1 I0 I3 I2 I1 I0
load = 0

load = 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

D D D D D D D D
Q Q Q Q Q Q Q Q
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
(
(b)
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Datapath Components
Shift Registers

 Shift right
Register contents
 Move each bit one position right 1 1 0 1
before shift right
 Shift in 0 to leftmost bit 0

Register contents
0 1 1 0
after shift right

 Shift Register
 Connect register’s flip-flop’s outputs to
next flip-flop’s input
 This design would always shift on every
clock cycle shr_in
 How can we control it?

Datapath Components
Shift Registers

 What is the result after shifting 10011 four times to

the right?

1. 10011
2. 00010
3. 10000
4. 00001

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Datapath Components
Shift Register

 To allow register to either shift or retain, use 2x1 muxes

 shr: 0 means retain, 1 shift
 shr_in: value to shift in
 May be 0, or 1
 Note: Can easily design shift register that shifts left instead

shr_in

shr=1
shr 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
2 1
2 1
D D D D
D D D D
Q Q Q Q
Q Q Q Q Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0 (b)
(a)

shr_in
shr

Q3 Q2 Q1 Q0

(c)
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Datapath Components
Rotate Register

 Rotate right Register contents

1 1 0 1
 Like shift right, but leftmost bit comes before shift right
from rightmost bit
Register contents
1 1 1 0
after shift right

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Datapath Components
Buses

 N-bit bus: N wires to carry N-bit data

item
 Circuit drawings can become cluttered
ld
 Convention for drawing buses
 Single bold line and/or small angled line 8
across
a

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Datapath Components
Register Example: Above-Mirror Display

 Instead of connecting car’s

computer to display using 32
wires, can we use fewer
wires?
 To reduce wires: Car’s
computer can write 1 value at 0001010
C Loaded on clock edge
a time, loads into one of four 8
registers with display d0 load reg0 T

2-4 decoder i0
8
0 8-bit
d1 load reg1 A
a0 4× 1 Mux
i0
i1
1 i1 8
a1 1 d D
d2 loadreg2 I 8
0001010
i2
8
d3 load reg3
e M
1 i3 s1 s0
load 8
x y
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Datapath Components
Shift Register Example: Above-Mirror Display

 Earlier example: 8 +2+1 = 11 wires from car’s computer to

above-mirror display’s four registers
 Better than 32 wires, but 11 still a lot -- want fewer for smaller
wire bundles

Note: this line is 1 bit, rather than 8 bits like before

 Use shift registers
x y
c
 Wires: 1+2+1=4 shr_in
d0 shr
 Computer sends one value reg0 T
s1 s0
at a time, one bit per clock 
2 4 i0
cycle 8
shr_in 4×1
 Serial communication d1 shr reg1 A
a0 i0
i1
a1 i1 8
shr_in d D
d2 shr reg2 I 8
i2
8
shr_in
shr reg3
e d3 M
shift i3
8
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Datapath Components
Multifunction Registers

 Many registers have multiple functions Functions:

 Load, shift, clear (load all 0s)
s1 s0 Operation
 And retain present value, of course
0 0 Maintain present value
 Easily designed using muxes 0 1 Parallel load
 Just connect each mux input to achieve desired 1 0 Shift right
function 1 1 (unused - let's load 0s)

shr_in I3 I2 I1 I0
0 0 0 0
s1 3 2 1 0 3210 3210 3210
s0 4 1 shr_in I3 I2 I1 I0
s1
D D D D s0
Q3 Q2 Q1 Q0
Q Q Q Q

(b)
Q3 Q2 Q1 Q0
(a)

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Datapath Components
Multifunction Registers

s1 s0 Operation
0 0 Maintain present value
0 1 Parallel load
1 0 Shift right
1 1 Shift left

I3 I2 I1 I0

shr_in
shl_in

3210 3210 3210 3210

shl_in I3 I2 I1 I0
shr_in
D D D D s1
s0

Q Q Q Q Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0
(a) (b)

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Datapath Components
Multifunction Registers with Separate Control Inputs

ld shr shl Operation I3 I2 I1 I0

0 0 0 Maintain present value shr_in
0 0 1 Shift left ld shr_in I3 I2 I1 I0

?
0 1 0 Shift right combi- s1 shl_in
s0 shl_in
0 1 1 Shift right – shr has priority over shl shr national
1 0 0 Parallel load circuit Q3 Q2 Q1 Q0
1 0 1 Parallel load – ld has priority shl
1 1 0 Parallel load – ld has priority Q3 Q2 Q1 Q0
1 1 1 Parallel load – ld has priority

Truth table for combinational circuit

Inputs Outputs Note
ld shr shl s1 s0 Operation
0 0 0 0 0 Maintain value
s1 = ld’shr’shl + ld’shrshl’ + ld’shrshl
0 0 1 1 1 Shift left
0 1 0 1 0 Shift right = ld’shr + ld’shl
0 1 1 1 0 Shift right
1 0 0 0 1 Parallel load s0 = ld’shr’shl + ld = shr’shl + ld
1 0 1 0 1 Parallel load
1 1 0 0 1 Parallel load
1 1 1 0 1 Parallel load

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Datapath Components
Register Operation Table

 Register operations typically shown using compact version of table

 X means same operation whether value is 0 or 1
 One X expands to two rows
 Two Xs expand to four rows
 Put highest priority control input on left to make reduced table simple

Inputs Outputs Note

ld shr shl s1 s0 Operation ld shr shl Operation
0 0 0 0 0 Maintain value 0 0 0 Maintain value
0 0 1 1 1 Shift left 0 0 1 Shift left
0 1 0 1 0 Shift right 0 1 X Shift right
0 1 1 1 0 Shift right 1 X X Parallel load
1 0 0 0 1 Parallel load
1 0 1 0 1 Parallel load
1 1 0 0 1 Parallel load
1 1 1 0 1 Parallel load

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