10/13/2023

EE 3007 SoC Design

Datapath Components

Datapath Components

 N-bit muxes
 Multifunction Register
 Shifters
 Counters
 Timers
 Register files

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Datapath Components
Register Design Process

 Can design register with desired operations using simple four-step process

Datapath Components
Register Design Example

Inputs
clr set ld shl Operation
0 0 0 0 Maintain present value
0 0 0 1 Shift left
0 0 1 X Parallel load
0 1 X X Set to all 1s
1 X X X Clear to all 0s

I3 I2 I1 I0

shl I3 I2 I1 I0
s2
s1 shl_in
ld combi- s0 shl_in
national
set
circuit Q3 Q2 Q1 Q0
clr
Q3 Q2 Q1 Q0

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Datapath Components
Register Design Example
s2 s1 s0 Operation
 Desired register operations 0 0 0 Maintain present value
 Synchronous clear, synchronous set, load, shift 0 0 1 Parallel load
left (with this priority) 0 1 0 Shift left
0 1 1 Synchronous clear
1 0 0 Synchronous set
Step 1: Determine mux size 1 0 1 Maintain present value
1 1 0 Maintain present value
5 operations: above, plus maintain 1 1 1 Maintain present value
a
present value (don’t forget this one!) - In
1 0
-> Use 8x1 mux from
Qn-1
s2
s1 7 6 5 4 3 2 1 0
s0
Step 2: Create mux operation table
D

Step 3: Connect mux inputs Q

Qn
Step 4: Map control lines
Inputs Outputs
s2 = clr’set clr set ld shl s2 s1 s0 Operation
s1 = clr’set’ld’shl + clr 0 0 0 0 0 0 0 Maintain present value
s0 = clr’set’ld + clr 0 0 0 1 0 1 0 Shift left
0 0 1 X 0 0 1 Parallel load
0 1 X X 1 0 0 Set to all 1s
1 X X X 0 1 1 Clear to all 0s
a
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Datapath Components
Register Design Example

I3 I2 I1 I0

shl I3 I2 I1 I0
s2
s1 shl_in
ld combi- s0 shl_in
national
set
circuit Q3 Q2 Q1 Q0
clr
Q3 Q2 Q1 Q0

Step 4: Map control lines Inputs Outputs

clr set ld shl s2 s1 s0 Operation
s2 = clr’set 0 0 0 0 0 0 0 Maintain present value
s1 = clr’set’ld’shl + clr 0 0 0 1 0 1 0 Shift left
s0 = clr’set’ld + clr 0 0 1 X 0 0 1 Parallel load
0 1 X X 1 0 0 Set to all 1s
1 X X X 0 1 1 Clear to all 0s

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Datapath Components
Shifters

 Shifting (e.g., left shifting 0011 yields 0110) useful for:

 Manipulating bits
 Converting serial data to parallel (remember earlier above-mirror display example with
shift registers)
 Shift left once is same as multiplying by 2 (0011 (3) becomes 0110 (6))
 Why? Essentially appending a 0 -- Note that multiplying decimal number by 10 accomplished just
be appending 0, i.e., by shifting left (55 becomes 550)
 Shift right once same as dividing by 2
i3 i2 i1 i0

i3 i2 i1 i0 inR
i3 i2 i1 i0 inL

2 01 201 2 01 2 01
in
<<1 shL s0
01 01 01 01 shR s1
in sh
Symbol
a

q3 q2 q1 q0
q3 q2 q1 q0
q3 q2 q1 q0 Shifter with left shift, right
Left shifter
Shifter with left shift or shift, and no shift
no shift

Datapath Components
Shifter Example: Temperature Averager

 Four registers storing a history of

temperatures 0000111 (7) 001000 (8) 001100 (12) 001111 (15)
 Want to output the average of those T
Ra Rb Rc Rd
temperatures clk
 Add, then divide by four ld
ld

 Same as shift right by 2

+ +
 Use three adders, and right shift by
two
+ divide by 4
shift in 0 0101010 (42)

0 >>2

0001010 (10)
a

Ravg
ld

Tavg

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Datapath Components
Strength Reduction

 Many multiplications not by power of 2 constants (2, 4, 8, …)

 E.g., by 5, or 10
 Could use multiplier component, but shifters are small and fast
 Replace multiplication by shifts and adds
 Operator strength reduction (multiply is “stronger” than shift/add)
 E.g., 5*C  4*C + C (4*C same as C<<2)
 Replacing division by shifts and adds slightly harder
 Approximate fraction using fraction having power of 2 denominator
 E.g., C/5 = 0.20*C, approx. equals (102/512)*C = 0.199*C
 (102/512)*C = C*(64+32+4+2)/512 = (C*64 + C*32 + C*4+C*2)/512
 = ((C<<6) + (C<<5) + (C<<2) + (C<<1)) >> 9

Datapath Components
Barrel Shifter
i3 i2 i1 i0
 A shifter that can shift by any amount
in
 4-bit barrel left shift can shift left by 0, 1, 2, 01 01 01 01
or 3 positions sh
 8-bit barrel left shifter can shift left by 0, 1, 2,
3, 4, 5, 6, or 7 positions q3 q2 q1 q0
 (Shifting an 8-bit number by 8 positions is Shift by 1 shifter uses 2x1 muxes. 8x1 mux
pointless -- you just lose all the bits) solution for 8-bit barrel shifter: too many
wires.
 Could design using 8x1 muxes and lots of
wires
 Too many wires Q: xyz=???
to shift by 5? I 00000110
8
 More elegant design 1
 Chain three shifters: 4, 2, and 1 x sh <<4 in 0

 Can achieve any shift of 0..7 by enabling the 8 01100000 (by 4)

correct combination of those three shifters, 0
y sh <<2 in 0
i.e., shifts should sum to desired amount
8 01100000
1
z sh <<1 in 0
8
Q
Net result: shift by 5: 11000000 (by 1) a

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Datapath Components
Counters

 N-bit up-counter: N-bit register that can

increment (add 1) to its own value on each
clock cycle
10
cnt 4-bit up-counter
 0000, 0001, 0010, 0011, ...., 1110, 1111, 0000 tc C
 Note how count “rolls over” from 1111 to 0000 4
 Terminal (last) count, tc, equals1 during value
just before rollover
010 0001
0000
0101
0100
0011
0010
1110
1111
0001
0000
...
 Internal design
 Register, incrementer, and N-input AND gate
to detect terminal count 4-bit up-counter

cnt
ld
4-bit register

4 4
4 +1 4
tc C

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Datapath Components
Down-Counter

 4-bit down-counter 4-bit down-counter

 1111, 1110, 1101, 1100, …, 0011,
0010, 0001, 0000, 1111, … cnt
ld
 Terminal count is 0000 4-bit register
 Use NOR gate to detect
 Need decrementer (-1) – design like
designed incrementer 4 4

4 –1

tc C 4

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Datapath Components
Up/Down-Counter

 Can count either up or down 4-bit up/down counter

 Includes both incrementer and
decrementer dir
1 4-bit 2x1 0
 Use dir input to select, using 2x1: 4
dir=0 means up
clr
 Likewise, dir selects appropriate clr
cn t
ld 4-bit register
terminal count value

4 4 4 4

4 –1 +1
4 4

1 2x1 0
tc C

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Datapath Components
Counter with Parallel Load

 Up-counter that can be loaded with L 4

external value ld
 Designed using 2x1 mux – ld input 1 4-bit 2x1 0

selects incremented value or 4

external value
cn t ld
 Load the internal register when 4-bit register
loading external value or when
counting
4 4

4 +1

tc C

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Datapath Components
Counter with Parallel Load

 Useful to create pulses at specific multiples 1000

of clock 4
 Not just at N-bit counter’s natural wrap-
around of 2N-1 to 0
ld L
 Example: Pulse every 9 clock cycles 1
cn t
 Use 4-bit down-counter with parallel load 4-bit down-counter
 Set parallel load input to 8 (1000) tc C
clk
 Use terminal count to reload
4
 When count reaches 0, next cycle loads 8.
 Why load 8 and not 9? Because 0 is included
in count sequence:
 8, 7, 6, 5, 4, 3, 2, 1, 0  9 counts

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Datapath Components (An RTL Preview!!)

Counter Example: Timer

 A type of counter used to measure time

 If we know the counter’s clock frequency and the count, we know the time that’s been
counted
 Example: Compute car’s speed using two sensors
 First sensor (a) clears and starts timer
 Second sensor (b) stops timer
 Assuming clock of 1kHz, timer output represents time to travel between sensors.
Knowing the distance, we can compute speed

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Datapath Components
Timers

 Pulses output at user-specified timer M

interval when enabled -1

32
 “Ticks” like a clock load
ld
 Interval specified as multiple of base 32-bit register
time unit
 If base is 1 microsec and user wants 1 32-bit 2x10
pulse every 300 ms, loads 300,000
into timer ld
enable 32-bit
 Can design using oscillator, register, cnt
down-counter
and down-counter 1 microsec
oscillator
tc C

Q unused
(a)

32

M
load
Q
enable 32-bit
1-microsec
(b)
Q timer

(c)

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Datapath Components
Register Files

 Accessing one of several

32
registers is: C
 OK if just a few registers d0 load reg0 huge mux
 Problematic when many 32
4x16 i0
 Ex: Earlier above-mirror display, too much
with 16 registers fanout
32-bit
4 16x1
 Much fanout (branching of
wire): Weakens signal
i3-i0
 Many wires: Congestion d D
32

congestion
d15 load reg15 16*32 = 512
e
i15 wires
load 32 s3-s0

16 32-bit registers
begins to have fanout and wire problems

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Datapath Components
Register File

 MxN register file: Efficient design for one-at-a-time write/read of many registers
 Consider 16 32-bit registers

32 32 32-bit data that is read

32-bit data to write

“read port”
W_data R_data
“write port”

4-bit “address” specifies 4 4 4-bit address to specifies

which register to write W_addr R_addr which register to read

Enable (load) line: Reg W_en R_en Enable read

16×32
written on next clock register file

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Datapath Components
Register File

 Internal design uses 32

W_data bus 32
drivers and bus R_data
d0 load reg0 driver d0
32
2x4 2x4
driver
d1 load reg1 d1 a

d q i0 32
W_addr i0
R_addr
i1 i1
q=d d2 load reg2 d2
Boosts signal 32
write read
decoder decoder
d3 load reg3 d3
e e
three-state driver
a 32
c W_en R_en
d q 4x32 register file

c=1: q=d d q
 d
c=0: q= Z q
like no connection Note: Each driver in figure actually
represents 32 1-bit drivers

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Datapath Components
Register File Timing Diagram

 Can write one register and read one register each clock cycle
 May be same register

32 32 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6

W_data R_data
clk
1 2 3 4 5 6
2 2
W_addr R_addr
W_data 9 22 X X 177 555
W_en R_en
4x32 W_addr 3 1 X X 2 3
register file
W_en

R_data Z Z Z Z

R_addr X X X

R_en

0: ? 0: 0: 0: 0: 0: 0:
1: ? 1: 1: 1: 1: 1: 1:
2: ? 2: 2: 2: 2: 2: 2:
3: ? 3: 3: 3: 3: 3: 3:

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