10/18/2023

EE 3007 SoC Design

Sequential Logic Design - Controllers

Finite-State Machines (FSMs) and Controllers

 Want sequential circuit with

b Controller
particular behavior over time x
laser

 Example: Laser timer clk

 Pushing button causes x=1 for
exactly 3 clock cycles patient

 Precisely-timed laser pulse

 How? Let’s try three flip-flops 0
 b=1 gets stored in first D flip-flop 0 b
D Q D Q D Q
 Then 2nd flip-flop on next cycle, 1
then 3rd flip-flop on next clk
a
 OR the three flip-flop outputs, so
x
x should be 1 for three cycles
1

Bad job – what if button

a pressed a second time during
those 3 cycles? 2

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Need a Better Way to Design Sequential

Circuits

 Also bad because of ad hoc design process

 How create other sequential circuits?
 Need
 A way to capture desired sequential behavior
 A way to convert such behavior to a sequential circuit

Step Description
Step 1: Create a truth table or equations, whichever is
Capture the
Capture most natural for the given problem, to describe
function
behavior the desired behavior of each output of the
Like we had for combinational logic.

designing This substep is only necessary if you captured the

combinational Step 2:
2A: Create
equations
function using a truth table instead of equations. Create
an equation for each output by ORing all the minterms
circuits Convert for that output. Simplify the equations if desired.
to circuit 2B: Implement For each output, create a circuit corresponding
as a gate- to the output’s equation. (Sharing gates among
based circuit multiple outputs is OK optionally.)

Sequential Logic Design

Describing Behavior of Sequential Circuit: FSM

 Finite-State Machine (FSM) Outputs: x

 A way to describe desired behavior of clk ^
x=0 x=1
sequential circuit
 Akin to Boolean equations for
O ff On
combinational behavior
 List states, and transitions among
clk ^
states
 Example: Make x change toggle (0 to 1,
or 1 to 0) every clock cycle
Off On Off On Off On Off On
 Two states: “Off” (x=0), and “On” (x=1)
 Transition from Off to On, or On to Off
cycle 1 cycle 2 cycle 3 cycle 4
(between states), on rising clock edge clk
 Arrow with no starting state points to initial
state (when circuit first starts) state Off On Off On
Outputs:

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Sequential Logic Design

FSM Example: Three-Cycles High Laser Timer

Inputs: b; Outputs: x
 Three Cycle High Laser Timer
x=0
 Turn on laser for three cycles whenever clk^
button is pressed Off b’*clk ^

 FSM needs four states

b*clk ^
 Wait in Off state while b is 0 (b’) x=1 clk^ x=1 clk^ x=1
 When b is 1 (and rising clock edge),
On1 On2 On3
transition to On1
 Sets x=1
 On next two clock edges, transition to
On2, then On3, which also set x=1
 So x=1 for three cycles after button clk
pressed Inputs:
b

State Off Off Off Off Off On1 On2 On3 Off

Outputs:
x

Sequential Logic Design

FSM Simplification: Rising Clock Edges Implicit

Inputs: b; Outputs: x
 Showing rising clock on every transition:
x=0
cluttered clk ^
 Make implicit -- assume every edge has Off b’ *clk ^
rising clock, even if not shown
b*clk ^
 What if we wanted a transition without a clk ^ clk ^
x=1 x=1 x=1
rising edge
 We don’t consider such asynchronous FSMs -- On1 On2 On3
less common, and advanced topic
 Only consider synchronous FSMs -- rising
edge on every transition
Inputs: b; Outputs: x
x=0

Off b’

a
b
x=1 x=1 x=1

On1 On2 On3

Note: Transition with no associated condition thus

transistions to next state on next clock cycle
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Sequential Logic Design

FSM Definition

 FSM consists of Inputs: b; Outputs: x

 Set of states x=0
 Ex: {Off, On1, On2, On3}
Off b’
 Set of inputs, set of outputs
 Ex: Inputs: {b}, Outputs: {x} b
 Initial state x=1 x=1 x=1

 Ex: “Off” On1 On2 On3

 Set of transitions
 Describes next states
 Ex: Has 5 transitions
We often draw FSM graphically, known
 Set of actions as state diagram
 Sets outputs while in states
 Ex: x=0, x=1, x=1, and x=1
Can also use table (state table), or
textual languages

Sequential Logic Design

FSM Example: Secure Car Key

 Many new car keys include tiny

computer chip
 When car starts, car’s computer (under
engine hood) requests identifier from
key
 Key transmits identifier
 If not, computer shuts off car
Inputs: a; Outputs: r
 FSM
 Wait until computer requests ID (a=1) Wait
 Transmit ID (in this case, 1101) r=0 a’
a

K1 K2 K3 K4

r=1 r=1 r=0 r=1

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Sequential Logic Design

FSM Example: Secure Car Key (cont.)

 Nice feature of FSM Inputs: a; Outputs: r

 Can evaluate output behavior for Wait

different input sequence r=0
a a’
 Timing diagrams show states and
output values for different input K1 K2 K3 K4
waveforms r=1 r=1 r=0 r=1

clk clk
Inputs Inputs
a
a
State Wait Wait K1 K2 K3 K4 Wait Wait State Wait Wait K1 K2 K3 K4 Wait K1

Outputs Output a

r r

Sequential Logic Design

FSM Example: Code Detector

 What is the state in the FSM in at the

indicated time?
1. K1
2. K2
3. K3
4. K4

Inputs: a; Outputs: r

Wait
r=0 a’
a

K1 K2 K3 K4 clk
r=1 r=1 r=0 r=1 Inputs
a

State ?? ?? ?? ?? ?? ?? ?? K1

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Sequential Logic Design

Ex: Earlier Flight-Attendant Call Button

 Previously built using SR latch, then D

Call Blue light
flip-flop button Bit
 Capture desired bit storage behavior Cancel Storage
button
using FSM instead
 Clear and precise description of desired
behavior
Inputs: Call, Cncl Outputs: L
 We’ll later convert to a circuit
L=0 Call L=1

Call' LightOff LightOn

(Cncl*Call')'
Cncl*Call'

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Sequential Logic Design

How To Capture Desired Behavior as FSM

 List states
 Give meaningful names, show initial state
 Optionally add some transitions if they help
 Create transitions
 For each state, define all possible transitions leaving that state.
 Refine the FSM
 Execute the FSM mentally and make any needed improvements.

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Sequential Logic Design

FSM Capture Example: Code Detector

 Unlock door (u=1) only when buttons s 1/0

Start u
pressed in sequence:
 start, then red, blue, green, red Red r Door
Code
g detector lock
 Input from each button: s, r, g, b Green
b
 Also, output a indicates that one of colored Blue
a
buttons is pressed
a
 Capture as FSM
 List states
 Some transitions included
Inputs: s, r, g, b, a
Outputs: u
Wait for start button
Wait
u=0 s'
s
a

Start Wait for first colored button

u=0
ar (a = 1 & r = 1)
ab ag ar
Red1 Blue Green Red2

u=0 u=0 u=0 u=1

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Sequential Logic Design

FSM Capture Example: Code Detector

 Capture as FSM s 1
Start u
 List states r Door
Red Code
 Create transitions Green
g detector lock
Blue b
a

Inputs: s, r, g, b, a
Outputs: u

Wait ar'
u=0 s'
s
a

Start

u=0 a'
ar
ab ag ar
Red1 Blue Green Red2

u=0 u=0 u=0 u=1

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Sequential Logic Design

FSM Capture Example: Code Detector

 Capture as FSM s 1
Start
u
 List states r Door
Red Code
 Create transitions Green
g detector lock
 Repeat for remaining Blue b
states a
 Refine FSM a

 Mentally execute
 Works for normal
sequence
Inputs: s, r, g, b, a
 Check unusual cases
Outputs: u

Wait
u=0 s'
s
ar' ab' ag' ar'

Start

u=0 a'
ar
ab ag ar
Red1 Blue Green Red2
a' a' a'
u=0 u=0 u=0 u=1
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Sequential Logic Design

FSM Example: Code Detector

 Can you trick this FSM to open the door,

without knowing the code?
1. Yes
2. No
3. Not sure

Inputs: s, r, g, b, a
Outputs: u

Wait
u=0 s'
s
ar' ab' ag' ar'

Start

u=0 a'
ar
ab ag ar
Red1 Blue Green Red2
a' a' a'
u=0 u=0 u=0 u=1

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Sequential Logic Design

Improve FSM for Code Detector

 New transition conditions detect if wrong button pressed, returns to “Wait”

 FSM provides formal, concrete means to accurately define desired behavior

Inputs: s,r,g,b,a;
Outputs: u
Wait
u=0 s s’ ar’ ab’ ag’ ar’

Start
a’
u=0
ar
ab ag ar
Red1 Blue Green Red2
a’ a’ a’
u=0 u=0 u=0 u=1

Note: small problem still

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remains; we’ll discuss later

Sequential Logic Design

Standard Controller Architecture

 How implement FSM as sequential circuit?

inputs

outputs

O
FSM

I
FSM

Combinational
 Use standard architecture logic
 State register -- to store the present state
S
 Combinational logic -- to compute outputs, and a m
next state m-bit m
clk
state register
 For laser timer FSM
 2-bit state register, can represent four states N

 Input b, output x General version

 Known as controller

Inputs: b; Outputs: x
inputs

outputs

b x
FSM

FSM

x=0 Combinational n1
logic
Off b’ n0
s1 s0
b
clk State register
x=1 x=1 x=1

On1 On2 On3

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Sequential Logic Design

Controller Design

Step Description
Step 1:
Capture the FSM Create an FSM that describes the desired behavior of the
Capture
behavior controller.

Step 2: 2A: Set up Use state register of appropriate width and combinational logic. The
Convert architecture logic’s inputs are the state register bits and the FSM inputs; outputs
to circuit are next state bits and the FSM outputs.

2B: Encode Assign unique binary number (encoding) to each state. Usually use
the states fewest bits, assign encoding to each state by counting up in binary.

2C: Fill in Translate FSM to truth table for combinational logic such that the logic
the truth table will generate the outputs and next state signals for the given FSM.
Ordering the inputs with state bits first makes the correspondence
between the table and the FSM clear.

2D: Implement Implement the combinational logic using any method.

combinational logic

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Sequential Logic Design

Controller Design: Laser Timer Example

 Step 1: Capture the FSM Inputs: b; Outputs: x

 Already done x=0
00
 Step 2A: Setup architecture Off b’
a
 2-bit state register (for 4 states) b
 Input b, output x x=1 x=1 x=1
 Next state signals n1, n0 01 On1 10 On2 11 On3

 Step 2B: Encode the states

 Any encoding with each state
outputs
inputs

b x
FSM

FSM

unique will work Combinational n1

logic
n0
s1 s0 a

clk State register

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Sequential Logic Design

Controller Design: Laser Timer Example (cont)

 Step 2C: Fill in the truth table

Inputs: b; Outputs: x
x=0
00
Off b’
a
b
x=1 x=1 x=1
01 On1 10 On2 11 On3

outputs
inputs
FSM
b x

FSM
Combinational n1
logic
n0
s1 s0
clk State register

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Sequential Logic Design

Controller Design: Laser Timer Example (cont)

 Step 2D: Implement combinational logic

outputs
inputs
FSM

b x
FSM

Combinational n1
logic
n0
s1 s0
clk State register

x = s1 + s0 (note from the table that x=1 if s1 = 1 or s0 = 1)

n1 = s1’s0b’ + s1’s0b + s1s0’b’ + s1s0’b

n1 = s1’s0 + s1s0’

n0 = s1’s0’b + s1s0’b’ + s1s0’b

n0 = s1’s0’b + s1s0’

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Sequential Logic Design

Controller Design: Laser Timer Example (cont)
FSM outputs
 Step 5: Implement combinational logic Combinational Logic
b x
(cont)

outputs
inputs
FSM
b x

FSM
Combinational n1
FSM inputs logic n1 a
n0
s1 s0
clk State register
n0

s1 s0

clk State register

x = s1 + s0
n1 = s1’s0 + s1s0’
n0 = s1’s0’b + s1s0’

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Sequential Logic Design

Understanding the Controller’s Behavior

x=0 x=0 x=0

00 b’ 00 b’ 00 b’
Off Off Off
b b b
x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1
01 On1 10 On2 11 On3 01 On1 10 On2 11 On3 01 On1 10 On2 11 On3

b x b x b x
0 0 0
0 0 1 0 1 1
0 0 1
0 0 1
n1 n1 n1
0 0 1
0 0 0 a
0 1 0
n0 n0 n0
0 1 0
0 0 0
s1 s0 s1 s0 s1 s0
clk clk clk
0 0 0 0 0 1
0 0 0 1 1 0

clk state=00 state=00 state=01

Input (b):

Output (x):

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Sequential Logic Design

Understanding the Controller’s Behavior

x=0 x=0 x=0

00 b’ 00 b’ 00 b’
Off Off Off
b b b
x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1
01 On1 10 On2 11 On3 01 On1 10 On2 11 On3 01 On1 10 On2 11 On3

b x b x b x
0 0 0
0 0 1 0 1 1
0 0 1
0 0 1
n1 n1 n1
0 0 1
0 0 0
0 1 0
n0 n0 n0
0 1 0
0 0 0
s1 s0 s1 s0 s1 s0
clk clk clk
0 0 0 0 0 1
0 0 0 1 1 0

clk state=00 state=00 state=01

Input (b):

Output (x):

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Controller Example: Button Press

Synchronizer

cycle1 cycle2 cycle3 cycle4

clk
Inputs:
bi
Button press
bi bo
synchronizer Outputs:
controller
bo

 Want simple sequential circuit that converts button press to single cycle
duration, regardless of length of time that button was actually pressed
 We assumed such an ideal button press signal in earlier example,
like the button in the laser timer controller

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Check Yourself –
Controller Example: Sequence Generator
 Want generate sequence 0001, 0011, 1100, 1000, (repeat)
 Each value for one clock cycle
 Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor”

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