PIC16F88X Memory Programming Specification

PIC16F88X
PIC16F88X Memory Programming Specification

This document includes the 1.2 Program/Verify Mode
programming specifications for the The Program/Verify mode for the PIC16F88X devices
following devices: allow programming of the user program memory, data
memory, user ID locations, Calibration Words and the
• PIC16F882
Configuration Word.
• PIC16F883
Programming and verification can take place in any
• PIC16F884
memory region, independent of the remaining regions.
• PIC16F886 This allows independent programming of program and
• PIC16F887 data memory regions.
1.0 PROGRAMMING THE

PIC16F88X DEVICES
The PIC16F88X can be programmed using the high-
voltage In-Circuit Serial Programming™ (ICSP™)
method or the low-voltage ICSP method. Both of these
can be done with the device in the user’s system. The
low-voltage ICSP method is slightly different than the
high-voltage method and these differences are noted
where applicable. This programming specification
applies to these devices in all package types.
1.1 Hardware Requirements

In the High-Voltage ICSP mode, the PIC16F88X
devices require two programmable power supplies;
one for VDD and one for MCLR/VPP. (See Section 6.0
“Program/Verify Mode Electrical Characteristics”
for more details.)
TABLE 1-1: PIN DESCRIPTIONS IN PROGRAM/VERIFY MODE

During Programming
Pin Name
Function Pin Type Pin Description
RB3 PGM I Low-voltage ICSP™ programming input if LVP
Configuration bit equals ‘1’
RB6 ICSPCLK I Clock Input – Schmitt Trigger input
RB7 ICSPDAT I/O Data Input/Output – Schmitt Trigger input
MCLR Program/Verify mode P(1) Program Mode Select
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power
Note 1: In the PIC16F88X, the programming high voltage is internally generated. To activate the Program/Verify
mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR
does not draw any significant current.
© 2007 Microchip Technology Inc. Advance Information DS41287C-page 1

PIC16F88X
FIGURE 1-1: PIC16F882/883/886 28-PIN PDIP, SOIC, SSOP DIAGRAM
MCLR/VPP/RE3 1 28 RB7/ICSPDAT
RA0/AN0/ULPWU/C12IN0- 2 27 RB6/ICSPCLK
RA1/AN1/C12IN1- 3 26 RB5/AN13/T1G
RA2/AN2/VREF-/CVREF/C2IN+ 4 25 RB4/AN11/P1D
PIC16F882/883/886
RA3/AN3/VREF+/C1IN+ 5 24 RB3/AN9/PGM/C12IN2-
RA4/T0CKI/C1OUT 6 23 RB2/AN8/P1B
RA5/AN4/SS/C2OUT 7 22 RB1/AN10/P1C/C12IN3-
VSS 8 21 RB0/AN12/INT
RA7/OSC1/CLKIN 9 20 VDD
RA6/OSC2/CLKOUT 10 19 VSS
11 18 RC7/RX/DT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2 12 17 RC6/TX/CK
13 16 RC5/SDO
RC2/CCP1/P1A
RC3/SCK/SCL 14 15 RC4/SDI/SDA
FIGURE 1-2: PIC16F882/883/886 28-PIN QFN DIAGRAM

RA0/AN0/ULPWU/C12IN0-
RA1/AN1/C12IN1-
MCLR/VPP/RE3
RB5/AN13/T1G
RB4/AN11/P1D
RB6/ICSPCLK
RB7/ICSPDAT
28
27
26
24
23
22
25
RA2/AN2/VREF-/CVREF/C2IN+ 1 21 RB3/AN9/PGM/C12IN2-
RA3/AN3/VREF+/C1IN+ 2 20 RB2/AN8/P1B
RA4/T0CKI/C1OUT 3 19 RB1/AN10/P1C/C12IN3-
RA5/AN4/SS/C2OUT 4 PIC16F882/883/886 18 RB0/AN12/INT
VSS 5 17 VDD
RA7/OSC1/CLKIN 6 16 VSS
RA6/OSC2/CLKOUT 7 15 RC7/RX/DT
10
12
13
14
11
8
9
RC3/SCK/SCL
RC1/T1OSI/CCP2
RC5/SDO
RC0/T1OSO/T1CKI
RC2/CCP1/P1A
RC4/SDI/SDA
RC6/TX/CK
DS41287C-page 2 Advance Information © 2007 Microchip Technology Inc.

PIC16F88X
FIGURE 1-3: PIC16F884/887 40-PIN PDIP
MCLR/VPP/RE3 1 40 RB7/ICSPDAT
RA0/AN0/ULPWU/C12IN0- 2 39 RB6/ICSPCLK
RA1/AN1/C12IN1- 3 38 RB5/AN13/T1G
RA2/AN2/VREF-/CVREF/C2IN+ 4 37 RB4/AN11
RA3/AN3/VREF+/C1IN+ 5 36 RB3/AN9/PGM/C12IN2-
RA4/T0CKI/C1OUT 6 35 RB2/AN8
RA5/AN4/SS/C2OUT 7 34 RB1/AN10/C12IN3-
PIC16F884/887
RE0/AN5 8 33 RB0/AN12/INT
RE1/AN6 9 32 VDD
RE2/AN7 10 31 VSS
VDD 11 30 RD7/P1D
VSS 12 29 RD6/P1C
RA7/OSC1/CLKIN 13 28 RD5/P1B
RA6/OSC2/CLKOUT 14 27 RD4
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
RC1/T1OSI/CCP2 16 25 RC6/TX/CK
RC2/CCP1/P1A 17 24 RC5/SDO
RC3/SCK/SCL 18 23 RC4/SDI/SDA
RD0 19 22 RD3
RD1 20 21 RD2

PIC16F88X
FIGURE 1-4: PIC16F884/887 44-PIN TQFP DIAGRAM
RC1/T1OSI/CCP2
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK
RC5/SDO
RD3
RD2
RD1
RD0
NC
41
40
39
37
36
35
34
42
44
43
38
RC7/RX/DT 1 33 NC
RD4 2 32 RC0/T1OSO/T1CKI
RD5/P1B 3 31 RA6/OSC2/CLKOUT
RD6/P1C 4 30 RA7/OSC1/CLKIN
RD7/P1D 5 29 VSS
VSS 6 PIC16F884/887 28 VDD
VDD 7 27 RE2/AN7
RB0/AN12/INT 8 26 RE1/AN6
RB1/AN10/C12IN3- 9 25 RE0/AN5
RB2/AN8 10 24 RA5/AN4/SS/C2OUT
RB3/AN9/PGM/C12IN2- 11 23 RA4/T0CKI/C1OUT
12
13
14
15
16
17
18
19
20
21
22
RA0/AN0/C12IN0-
RA1/AN1/C12IN1-
MCLR/VPP/RE3
RA3/AN3/VREF+/C1IN+
RB7/ICSPDAT
RB6/ICSPCLK
RA2/AN2/VREF-/CVREF/C2IN+
RB4/AN11
RB5/AN13/T1G
NC
NC

PIC16F88X
FIGURE 1-5: PIC16F884/887 44-PIN QFN DIAGRAM
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK
RC5/SDO
RD3
RD2
RD1
RD0
44
43
42
41
40
39
37
36
35
34
38
RC7/RX/DT 1 33 RA6/OSC2/CLKOUT
RD4 2 32 RA7/OSC1/CLKIN
RD5/P1B 3 31 VSS
RD6/P1C 4 30 VSS
RD7/P1D 5 29 NC
VSS 6 PIC16F884/887 28 VDD
VDD 7 27 RE2/AN7
VDD 8 26 RE1/AN6
RB0/AN12/INT 9 25 RE0/AN5
RB1/AN10/C12IN3- 10 24 RA5/AN4/SS/C2OUT
RB2/AN8 11 23 RA4/T0CKI/C1OUT
22
12
13
14
15
16
17
18
19
20
21
RB6/ICSPCLK
MCLR/VPP/RE3
RA0/AN0/ULPWU/C12IN0-
RA1/AN1/C12IN1-
NC
RB7/ICSPDAT
RB5/AN13/T1G
RA3/AN3/VREF+/C1IN+
RB4/AN11
RA2/AN2/VREF-/CVREF/C2IN+
RB3/AN9/PGM/C12IN2-

PIC16F88X
2.0 MEMORY DESCRIPTION 2.2 User ID Locations
A user may store identification information (user ID) in
2.1 Program Memory Map four designated locations. The user ID locations are
The user memory space extends from 0x0000-0x07FF mapped in 0x2000-0x2003. It is recommended that the
for the PIC16F882, 0x0000-0x0FFF for the user use only the seven Least Significant bits (LSb) of
PIC16F883/884, and from 0x0000-0x1FFF for each user ID location. The user ID locations read out
PIC16F886/887. In Program/Verify mode, the program normally, even after code protection is enabled. It is
memory space extends from 0x0000 to 0x3FFF, with recommended that ID locations are written as
the first half being user program memory and the ‘xx xxxx xbbb bbbb’ where ‘bbb bbbb’ is user ID
second half (0x2000-0x3FFF) being configuration information.
memory. The PC will increment from 0x0000 to 0x1FFF The 14 bits may be programmed, but only the 7 LSbs
and wrap to 0x0000, 0x2000 to 0x3FFF and wrap are displayed by MPLAB® IDE. The xxxx’s are “don’t
around to 0x2000 (not to 0x0000). Once in configura- care” bits and are not read by MPLAB IDE.
tion memory, the highest bit of the PC stays a ‘1’, thus
always pointing to the configuration memory. The only 2.3 Calibration Word
way to point to user program memory is to reset the
part and re-enter Program/Verify mode as described in For the PIC16F88X devices, the 8 MHz Internal Oscil-
Section 3.0 “Program/Verify Mode”. lator (INTOSC), the Power-on Reset (POR) and the
Brown-out Reset (BOR) modules are factory calibrated
For the PIC16F88X devices, the configuration memory
and stored in the Calibration Word (0x2009). See the
space, 0x2000-0x2009, is physically implemented.
applicable device data sheet for more information.
However, only locations 0x2000-0x2003 and 0x2007-
0x2009 are available. Other locations are reserved. The Calibration Words do not necessarily participate in
the erase operation unless a specific procedure is
executed. Therefore, the device can be erased without
effecting the Calibration Words. This simplifies the
erase procedure, for these values do not need to be
read and restored after the device is erased. See
Section 3.2.6.10 “Bulk Erase Program Memory” for
more information on the various erase sequences.

PIC16F88X
FIGURE 2-1: PIC16F882 PROGRAM MEMORY MAPPING
2 KW
Implemented
07FF
Program Memory
Maps to
User ID Location 0-7FF
2000
2001 User ID Location
1FFF
2002 User ID Location 2000
Implemented
2004 Reserved
2005 Reserved
Maps to Configuration Memory
Device ID 2000-203F
2006
2007 Configuration Word 1
2009 Calibration Word 3FFF
200A-207F Reserved

PIC16F88X
FIGURE 2-2: PIC16F883/884 PROGRAM MEMORY MAPPING
4 KW
Implemented
0FFF
Program Memory
Maps to
User ID Location 0-FFF
2000
1FFF
Implemented
2004 Reserved
2005 Reserved
Device ID 2000-203F
2006
2009 Calibration Word 3FFF
200A-207F Reserved

PIC16F88X
FIGURE 2-3: PIC16F886/887 PROGRAM MEMORY MAPPING
8 KW
Implemented Program Memory
1FFF
Implemented
2004 Reserved
2005 Reserved
Device ID 2000-203F
2006
2009 Calibration 3FFF
200A-207F Reserved

PIC16F88X
3.0 PROGRAM/VERIFY MODE FIGURE 3-1: VPP-FIRST PROGRAM/
VERIFY MODE ENTRY
Two methods are available to enter Program/Verify
mode. The “VPP-first” is entered by holding ICSPDAT TPPDP THLD0
and ICSPCLK low while raising MCLR pin from VIL to
VIHH (high voltage), then applying VDD and data. This
method can be used for any Configuration Word VPP
selection and must be used if the INTOSC and internal
MCLR options are selected (FOSC<2:0> = 100 or 101
VDD
and MCLRE = 0). The VPP-first entry prevents the
device from executing code prior to entering Program/
Verify mode. See the timing diagram in Figure 3-1. ICSPDAT
The second entry method, “VDD-first”, is entered by

applying VDD, holding ICSPDAT and ICSPCLK low, ICSPCLK
then raising MCLR pin from VIL to VIHH (high voltage), Note: This method of entry is valid, regardless
followed by data. This technique is useful when of Configuration Word selected.
programming the device when VDD is already applied,
for it is not necessary to disconnect VDD to enter
Program/Verify mode. See the timing diagram in FIGURE 3-2: VDD-FIRST PROGRAM/
Figure 3-2. VERIFY MODE ENTRY
Once in this mode, the program memory, data memory, THLD0 TPPDP
and configuration memory can be accessed and
programmed in serial fashion. ICSPDAT and ICSPCLK
are Schmitt Trigger inputs in this mode. RB6 is tri-state,
VPP
regardless of fuse setting.
The sequence that enters the device into the Program- VDD
ming/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at VIL). Therefore, all
ICSPDAT
I/O’s are in the Reset state (high-impedance inputs)
and the Program Counter (PC) is cleared.
ICSPCLK
When powering down VDD, make sure VDD does not
undershoot VSS. If VDD undershoots VSS while VPP is
applied, damage could be done to the device. To pre-
vent possible damage to the device, power-down VPP FIGURE 3-3: PROGRAM/VERIFY MODE
either before VDD or at the same time as VDD. EXIT
When programming a device with the internal MCLR THLD0
and INTOSC, care must be taken to prevent code exe-
cution during power-down. If VDD is powered down VDD
before VPP, there is a possibility for a VDD undershoot
to cause device damage. If VPP is powered down
before VDD, there is the possibility of code execution. If VPP
VDD is powered down at the same time as VPP or just
slightly after VPP, code execution is prevented. See
Figure 3-3 for the timing. ICSPDAT
ICSPCLK

PIC16F88X
3.1 Low-Voltage ICSP™ Mode The sequence for programming eight words of program
memory at a time is as follows:
The Low-Voltage ICSP Programming mode allows the
PIC16F88X devices to be programmed using VDD only. 1. Load a word at the current program memory
However, when this mode is enabled by a Configura- address using Load Data For Program Memory
tion bit (LVP), the PIC16F88X device dedicates RB3 to command.
control entry/exit into Programming mode. When LVP 2. Issue an Increment Address command.
bit is set to ‘1’, the low-voltage ICSP programming entry 3. Load a word at the current program memory
is enabled. Since the LVP Configuration bit allows low- address using Load Data For Program Memory
voltage ICSP programming entry in its erased state, an command.
erased device will have the LVP bit enabled at the fac- 4. Repeat Step 2 and Step 3 six times.
tory. While LVP is ‘1’, RB3 is dedicated to low-voltage 5. Issue a Begin Programming command either
ICSP programming. Bring RB3 and then MCLR to VDD internally or externally timed.
to enter Programming mode. All other specifications for
6. Wait TPROG1 (internally timed) or TPROG2
high-voltage ICSP apply. To disable the Low-Voltage
(externally timed).
ICSP mode, the LVP bit must be programmed to ‘0’.
This must be done while entered in the High-Voltage 7. Issue End Programming if externally timed.
Entry mode (LVP bit = ‘1’). RB3 is now a general 8. Issue an Increment Address command.
purpose I/O pin. 9. Repeat this sequence as required to write
program memory.
3.2 Program/Erase Algorithms See Figure 3-18 for more information.
The PIC16F88X devices’ program memory may be
3.2.2 FOUR-WORD PROGRAMMING
written in three ways. The PIC16F882/883/884 uses
one-word and four-word writes. The PIC16F886/887 Four-word programming can be used on all devices in
uses one-word, four-word and eight-word writes. The the PIC16F88X family. Only the program memory can
four-word or eight-word algorithm is used to program be written using this algorithm. Data and configuration
the program memory only. The one-word algorithm can memory (>0x2000) must use the one-word
write any available memory location (i.e., program programming algorithm (Section 3.2.3 “One-Word
memory, configuration memory and data memory). Programming”).
After writing the array, the PC may be reset and read This algorithm writes four sequential addresses in
back to verify the write. It is not possible to verify program memory. The four addresses must point to a
immediately following the write because the PC can four-word block with addresses modulo 4 of 0, 1, 2 and
only increment, not decrement. 3. For example, programming address 4 through 7 can
be programmed together. Programming addresses 2
A device Reset will clear the PC and set the address to
through 5 will create an unexpected result.
‘0’. The Increment Address command will increment
the PC. The Load Configuration command will set the The sequence for programming four words of program
PC to 0x2000. The available commands are shown in memory at a time is as follows:
Table 3-1. 1. Load a word at the current program memory
address using Load Data For Program Memory
3.2.1 EIGHT-WORD PROGRAMMING command.
Only the program memory on PIC16F886/887 can be 2. Issue an Increment Address command.
written using this algorithm. Data and configuration 3. Load a word at the current program memory
memory (>0x2000) must use the one-word address using Load Data For Program Memory
programming agorithm (Section 3.2.3 “One-Word command.
Programming”).
4. Repeat Step 2 and Step 3 two times.
This algorithm writes eight sequential addresses in 5. Issue a Begin Programming command either
program memory. The eight addresses must point to an internally or externally timed.
eight-word block with addresses modulo 8 of 0, 1, 2, 3,
6. Wait TPROG1 (internally timed) or TPROG2
4, 5, 6 and 7. For example, programming address 8
(externally timed).
through 15 can be programmed together. Program-
ming addresses 2 through 9 will create an unexpected 7. Issue End Programming if externally timed.
result. 8. Issue an Increment Address command.
9. Repeat this sequence as required to write
program memory.
See Figure 3-17 for more information.

PIC16F88X
3.2.3 ONE-WORD PROGRAMMING 3.2.5 ERASE ALGORITHMS
The program memory may also be written one word at The PIC16F88X will erase different memory locations
a time to allow compatibility with other 8-pin and 14-pin depending on the Program Counter (PC), CP and CPD
Flash PIC® MCU devices. Configuration memory values, and which erase command is executed. The
(>0x2000) and data memory must be written one word following sequences can be used to erase noted
(or byte) at a time. memory locations. In each sequence, the data memory
will be erased if the CPD bit in the Configuration Word
Note: The write latches must be reset after
is programmed (clear).
programming the user IDs (0x2000-
0x2003), Configuration Words (0x2007- To erase the program memory and Configuration
0x2008) or Calibration Word (0x2009). See Words (0x2007-0x2008), the following sequence must
Section 3.2.4 “Resetting Write Latches”. be performed. Note the Calibration Word (0x2009) and
user ID (0x2000-0x2003) will not be erased.
The sequence for programming one word of program
memory at a time is as follows: 1. Do a Bulk Erase Program Memory command.
1. Load a word at the current program memory 2. Wait TERA to complete erase.
address using Load Data For Program Memory To erase the user ID (0x2000-0x2003), Configuration
command. Words (0x2007-0x2008) and program memory, use the
2. Issue a Begin Programming command either following sequence.
internally or externally timed. Note: The Calibration Word (0x2009) will not be
3. Wait TPROG1 (internally timed) or TPROG2 erased.
(externally timed).
1. Perform Load Configuration with dummy data to
4. Issue End Programming if externally timed.
point the Program Counter (PC) to 0x2000.
5. Issue an Increment Address command.
2. Perform a Bulk Erase Program Memory
6. Repeat this sequence as required to write command.
program, data or configuration memory.
3. Wait TERA to complete erase.
See Figure 3-16 for more information.
To erase the user ID (0x2000-0x2003), Configuration
Words (0x2007-0x2008), Calibration Word (0x2009)
3.2.4 RESETTING WRITE LATCHES
and program memory, use the following sequence.
The user IDs (0x2000-0x2003), Configuration Words
(0x2007-0x2008) and Calibration Word (0x2009) are Note: The Calibration Word (0x2009) will be
mapped into the configuration memory, but do not erased.
physically reside in it. As a result, the write latches are 1. Perform Load Configuration with dummy data to
not reset when programming these locations and must point the Program Counter (PC) to 0x2000.
be reset by the programmer. This can be done in two 2. Perform 9 Increment Address commands to
ways, either loading all eight latches with ‘1’s or by point the PC to the Calibration Word at 0x2009.
exiting Program/Verify mode.
3. Do a Bulk Erase Program Memory command.
The sequence for manually resetting the write latches 4. Wait TERA to complete erase.
is as follows:
To erase the data memory, use the following sequence:
1. Load a word using Load Data For Program
Memory or Load Data For Configuration 1. Perform a Bulk Erase Data Memory command.
Memory command with a data word of all ‘1’s. 2. Wait TERA to complete erase.
2. Issue an Increment Address command.
3. Repeat this sequence three times on the
PIC16F883/884 and seven times on the
PIC16F886/887 to reset all write latches.

PIC16F88X
3.2.6 SERIAL PROGRAM/VERIFY During a read operation, the LSb will be transmitted
OPERATION onto ICSPDAT pin on the rising edge of the second
cycle. For a load operation, the LSb will be latched on
The ICSPCLK pin is used as a clock input and the
the falling edge of the second cycle. A minimum TDLY1
ICSPDAT pin is used for entering command bits and
delay is also specified between consecutive
data input/output during serial operation. To input a
commands, except for the End Programming
command, ICSPCLK is cycled six times. Each
command, which requires a TDIS.
command bit is latched on the falling edge of the clock
with the LSb of the command being input first. The data All commands and data words are transmitted LSb first.
input onto the ICSPDAT pin is required to have a Data is transmitted on the rising edge and latched on
minimum setup and hold time (see Table 6-1), with the falling edge of the ICSPCLK. To allow for decoding
respect to the falling edge of the clock. Commands that of commands and reversal of data pin configuration, a
have data associated with them (Read and Load) are time separation of at least TDLY1 is required between a
specified to have a minimum delay of TDLY1 between command and a data word.
the command and the data. After this delay, the clock The commands that are available are described in
pin is cycled 16 times with the first cycle being a Start Table 3-1.
bit and the last cycle being a Stop bit.
TABLE 3-1: COMMAND MAPPING FOR PIC16F88X

Command Mapping (MSb … LSb) Data
Load Configuration x x 0 0 0 0 0, data (14), 0
Load Data For Program Memory x x 0 0 1 0 0, data (14), 0
Load Data For Data Memory x x 0 0 1 1 0, data (8), zero (6), 0
Read Data From Program Memory x x 0 1 0 0 0, data (14), 0
Read Data From Data Memory x x 0 1 0 1 0, data (8), zero (6), 0
Increment Address x x 0 1 1 0
Begin Programming x 0 1 0 0 0 Internally Timed
Begin Programming x 1 1 0 0 0 Externally Timed
End Programming x 0 1 0 1 0
Bulk Erase Program Memory x x 1 0 0 1 Internally Timed
Bulk Erase Data Memory x x 1 0 1 1 Internally Timed
Row Erase Program Memory x 1 0 0 0 1 Internally Timed

PIC16F88X
3.2.6.1 Load Configuration After the 6-bit command is input, ICSPCLK pin is
cycled an additional 16 times for the Start bit, 14 bits of
The Load Configuration command is used to access
data and a Stop bit. See Figure 3-4.
the Configuration Words (0x2007-0x2008), user ID
(0x2000-0x2003) and Calibration Word (0x2009). This After the configuration memory is entered, the only way
command sets the Program Counter (PC) to address to get back to the program memory is to exit the
0x2000 and loads the data latches with one word of Program/Verify mode by taking MCLR low (VIL).
data.
After receiving a Load Configuration command, the
Configuration Word is accessed by performing an
Increment Address command 7 or 8 times to point the
PC to Configuration Word 0x2007 or 0x2008. It can
then be programmed with the loaded data using a
Begin Programming command either internally or
externally timed.
FIGURE 3-4: LOAD CONFIGURATION COMMAND
TDLY2
1 2 3 4 5 6 1 2 3 4 5 15 16
ICSPCLK
0 00 0 0 x x strt_bit LSb MSb stp_bit

ICSPDAT
TDLY1 TSET1
THLD1
3.2.6.2 Load Data For Program Memory

After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. A timing diagram for the Load
Data For Program Memory command is shown in
Figure 3-5.
FIGURE 3-5: LOAD DATA FOR PROGRAM MEMORY COMMAND
TDLY2
1 2 3 4 5 6 1 2 3 4 5 15 16
ICSPCLK
0 1 0 0 x x strt_bit LSb MSb stp_bit

ICSPDAT
TSET1 TDLY1 TSET1
THLD1 THLD1

PIC16F88X
3.2.6.3 Load Data For Data Memory
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied.
However, the data memory is only 8 bits wide and thus,
only the first 8 bits of data after the Start bit will be
programmed into the data memory. It is still necessary
to cycle the clock the full 16 cycles in order to allow the
internal circuitry to reset properly. The data memory
contains 256 bytes.
FIGURE 3-6: LOAD DATA FOR DATA MEMORY COMMAND

TDLY2
1 2 3 4 5 6 1 2 3 4 5 15 16
ICSPCLK
TDLY3
1 1 0 0 x x stp_bit
ICSPDAT strt_bit
LSb
MSb on 9th falling edge
TDLY1
3.2.6.4 Read Data From Program Memory

After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently accessed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge.
If the program memory is code-protected (CP = 0), the
data is read as zeros.
FIGURE 3-7: READ DATA FROM PROGRAM MEMORY COMMAND
TDLY2
1 2 3 4 5 6 1 2 3 4 5 15 16
ICSPCLK
TDLY3
1 0 0 1 0 x x MSb stp_bit
ICSPDAT strt_bit
LSb
TSET1
THLD1 TDLY1
Input Output Input

PIC16F88X
3.2.6.5 Read Data From Data Memory
After receiving this command, the chip will transmit
data bits out of the data memory starting with the sec-
ond rising edge of the clock input. The ICSPDAT pin will
go into Output mode on the second rising edge, and it
will revert to Input mode (high-impedance) after the
16th rising edge. As previously stated, the data mem-
ory is 8 bits wide, and therefore, only the first 8 bits that
are output are actual data. If the data memory is code-
protected, the data is read as all zeros. A timing
diagram of this command is shown in Figure 3-8.
FIGURE 3-8: READ DATA FROM PROGRAM MEMORY COMMAND
TDLY2
1 2 3 4 5 6 1 2 3 4 5 15 16
ICSPCLK
TDLY3
1 0 1 0 x x stp_bit
ICSPDAT strt_bit
LSb MSb on 9th falling edge
TSET1
THLD1 TDLY1
Input Output Input
3.2.6.6 Increment Address

The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 3-9.
It is not possible to decrement the address counter. To
reset this counter, the user should exit and re-enter
Program/Verify mode.
FIGURE 3-9: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
TDLY2
Next Command
1 2 3 4 5 6 1 2
ICSPCLK
0 1 1 0 x x x 0
ICSPDAT
TSET1
THLD1
TDLY1

PIC16F88X
3.2.6.7 Begin Programming (Internally
Timed)
A Load command must be given before every Begin
Programming command. Programming of the appropri-
ate memory (user program memory, configuration
memory or data memory) will begin after this command
is received and decoded. An internal timing mechanism
executes a write. The user must allow for program
cycle time for programming to complete. No End
Programming command is required.
The addressed location is not erased before program-
ming. However, the address location is erased if Data
Memory is being programmed.
FIGURE 3-10: BEGIN PROGRAMMING (INTERNALLY TIMED)
TPROG1
Next Command
1 2 3 4 5 6 1 2
ICSPCLK
0 0 0 1 0 x x 0
ICSPDAT
TSET1
THLD1
3.2.6.8 Begin Programming (Externally

Timed)
A Load command must be given before every Begin
Programming command. Programming of the appropri-
ate memory (program memory, configuration or data
memory) will begin after this command is received and
decoded. Programming requires (TPROG2) time and is
terminated using an End Programming command.
The addressed location is not erased before
programming.
FIGURE 3-11: BEGIN PROGRAMMING COMMAND (EXTERNALLY TIMED
VIHH
MCLR TPROG2
End Programming Command
1 2 3 4 5 6 1 2
ICSPCLK
ICSPDAT 0 0 0 1 1 x x 0
TSET1
THLD1

PIC16F88X
3.2.6.9 End Programming
FIGURE 3-12: END PROGRAMMING (SERIAL PROGRAM/VERIFY)
VIHH
MCLR
Next Command
1 2 3 4 5 6 1 2
ICSPCLK
ICSPDAT 0 1 0 1 0 x x 0
TDIS
TSET1
THLD1
3.2.6.10 Bulk Erase Program Memory

After this command is performed, the entire program
memory and Configuration Words (0x2007-0x2008)
are erased. Data memory will also be erased if the CPD
bit in the Configuration Word is programmed (clear).
See Section 3.2.5 “Erase Algorithms” for erase
sequences.
Note: All Bulk Erase operations must take place
between 4.5V and 5.5V VDD.
FIGURE 3-13: BULK ERASE PROGRAM MEMORY COMMAND
TERA
Next Command
1 2 3 4 5 6 1 2
ICSPCLK
1 0 0 1 x x x 0
ICSPDAT
TSET1 TSET1
THLD1 THLD1

PIC16F88X
3.2.6.11 Bulk Erase Data Memory
To perform an erase of the data memory, the following
sequence must be performed.
1. Perform a Bulk Erase Data Memory command.
2. Wait TERA to complete Bulk Erase.
Data memory won’t erase if code-protected (CPD = 0).
Note 1: All Bulk Erase operations must take place
between 4.5V and 5.5V VDD.
2: Data memory won’t erase if code-protected
(CPD = 0).
FIGURE 3-14: BULK ERASE DATA MEMORY COMMAND
TERA
Next Command
1 2 3 4 5 6 1 2
ICSPCLK
1 1 0 1 x x x 0
ICSPDAT
TSET1
THLD1
3.2.6.12 Row Erase Program Memory

This command erases the 16-word row of program
memory pointed to by PC<11:4>. If the program mem-
ory array is protected (CP = 0) or the PC points to the
configuration memory (>0x2000), the command is
ignored.
To perform a Row Erase Program Memory, the
following sequence must be performed.
1. Execute a Row Erase Program Memory
command.
2. Wait TERA to complete a row erase.
FIGURE 3-15: ROW ERASE PROGRAM MEMORY COMMAND
TERA
Next Command
1 2 3 4 5 6 1 2
ICSPCLK
1 0 0 0 1 x x 0
ICSPDAT

PIC16F88X
FIGURE 3-16: ONE-WORD PROGRAMMING FLOWCHART
Start
Bulk Erase
Program Program Cycle
Memory(1),(3)
Load Data
for
One-word Program Memory
Program Cycle
Begin Begin
Read Data Programming Programming
from Command Command
Program Memory (Internally timed) (Externally timed)
Report
No
Data Correct? Programming
Wait TPROG1 Wait TPROG2
Failure
Yes
Increment End
No All Locations
Address Programming
Done?
Command
Yes
Program Data
Memory(2) Wait TDIS
Figure 3-19
Program
User ID/Config. bits
Figure 3-18
Done
Note 1: This step is optional if device has already been erased or has not been previously programmed.
2: This step is optional if the data memory does not require updates.
3: If the device is code-protected or must be completely erased, then Bulk Erase device per Figure 3-21.

PIC16F88X
FIGURE 3-17: FOUR-WORD PROGRAMMING FLOWCHART
Program Cycle
Load Data
for
Program Memory
Increment
Address
Start Command
Bulk Erase
Load Data
Program
for
Memory(1),(4)
Program Memory
Four-word Increment
Program Cycle Address
Command
Increment Load Data

No All Locations
Address for
Done?
Command Program Memory
Yes
Program Data Increment

Memory(2),(3) Address
Figure 3-19 Command
Program
Load Data
User ID/Config. bits
for
Figure 3-18
Program Memory
Done
Begin Begin
Programming Programming
Command Command
(Internally timed) (Externally timed)
End
Programming
Wait TDIS
Note 1: This step is optional if device is erased or not previously programmed.

2: Verification in Four-Word mode is accomplished after programming by reading back the entire memory.

PIC16F88X
FIGURE 3-18: EIGHT-WORD PROGRAMMING FLOWCHART
Program Cycle
Load Data
for Latch 1
Program Memory
Start Increment
Address
Command
Bulk Erase
Program
Memory(1,4) Load Data
Latch 2
for
Program Memory
Eight-word
Program Cycle
Increment
No All Locations
Address
Done?
Command
Yes Increment
Address
Program Data
Command
Memory(2,3)
(Figure 3-19)
Load Data
Program for Latch 8
User ID/Config. bits Program Memory
(Figure 3-18)
Begin Begin
Done Programming Programming
Command Command
(Internally timed) (Externally timed)
End
Programming
Wait TDIS
Note 1: This step is optional if device is erased or not previously programmed.

2: Verification in Eight-Word mode is accomplished after programming by reading back the entire memory.

PIC16F88X
FIGURE 3-19: PROGRAM FLOWCHART – PIC16F88X CONFIGURATION MEMORY
Start
Load
Configuration
Program Cycle
Bulk Erase
Program
Memory Load Data
for
Program Memory
One-word
Program Cycle
(User ID) Begin Begin
Command Command
Read Data (Internally timed) (Externally timed)
From Program
Memory Command

No Report
Failure
End
Yes Programming
Increment
Address
Command
Wait TDIS
Increment
No Address = Yes
Address
0x2004?
Command (x3)
One-word
Program Cycle
(Config. Word 1)
Increment
Address
Command
One-word
Program Cycle
(Config. Word 2)
Read Data
From Program
Memory Command
Report
No
Failure
Yes
Done

PIC16F88X
FIGURE 3-20: PROGRAM FLOWCHART – PIC16F88X DATA MEMORY
Start
Program Cycle
Bulk Erase
Data Memory
Load Data
for
Data Memory
Program Cycle
Begin Begin
Read Data Command Command
From Data (Internally timed) (Externally timed)
Memory Command

Report
No
Failure
End
Yes
Programming
Increment No All Locations

Address
Done?
Command
Wait TDIS
Yes
Done

PIC16F88X
FIGURE 3-21: PROGRAM FLOWCHART – ERASE FLASH DEVICE
Start
Bulk Erase
Program Memory
Load Configuration
Bulk Erase
Program Memory
Bulk Erase
Data Memory
Done
Note: This sequence does not erase the Calibration Word at address 2009h.

PIC16F88X
4.0 CONFIGURATION WORD
The PIC16F88X has several Configuration bits. These
bits can be programmed (reads ‘0’), or left unchanged
(reads ‘1’), to select various device configurations.
4.1 Low-Voltage Programming (LVP)

Bit
The LVP bit in the Configuration Word 1 register
enables low-voltage ICSP programming. The LVP bit
defaults to a ‘1’ following an erase. If Low-Voltage Pro-
gramming mode is not used, the LVP bit can be pro-
grammed to a ‘0’ and RB3/PGM becomes a digital I/O
pin. However, the LVP bit may only be programmed by
entering the High-Voltage ICSP mode, where MCLR/
VPP is raised to VIHH. Once the LVP bit is programmed
to a ‘0’, only the High-Voltage ICSP mode is available
and only the High-Voltage ICSP mode can be used to
program the device.
Note 1: The normal High-Voltage ICSP mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR/VPP pin.
2: While in Low-Voltage ICSP mode, the
RB3 pin can no longer be used as a
general purpose I/O.
3: If the device Master Clear is disabled,
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low-Voltage Programming
(Config Word 1<12> = 0); or
b) make certain that RB3/PGM is held low
during entry into ICSP.

PIC16F88X
REGISTER 4-1: CONFIGURATION WORD 1 (ADDRESS: 2007h)

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
DEBUG LVP FCMEN IESO BOREN1 BOREN0 CPD
bit 13 bit 7
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

CP MCLRE PWRTE WDTEN FOSC2 FOSC1 FOSC0
bit 6 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Default value ‘1’ = Bit is erased ‘0’ = Bit is programmed
P = Programmable bit x = Bit is unknown
bit 13 DEBUG: Debugger Mode bit

1 = Background debugger function not enabled
0 = Background debugger functional
bit 12 LVP: Low-Voltage Programming Enable bit
1 = RB3/PGM pin has PGM function, low-voltage programming enabled
0 = RB3 pin is digital I/O, HV on MCLR must be used for programming
bit 11 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock is enabled
0 = Fail-Safe Clock is disabled
bit 10 IESO: Internal/External Switch Over bit
1 = Internal/External Switch Over mode enabled
0 = Internal/External Switch Over mode disabled
bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit (PCON<4>)
00 = BOR disabled
bit 7 CPD: Data EE Memory Code Protection bit
1 = Code protection off
0 = Data EE memory code-protected
bit 6 CP: Flash Program Memory Code Protection bit
PIC16F886/887
0 = 0000h to 1FFFh code protection on
PIC16F883/884
0 = 0000h to 0FFFh code protection on
bit 5 MCLRE: MCLR/VPP/RE3 Pin Function Select bit
1 = MCLR/VPP/RE3 pin function is MCLR
0 = MCLR/VPP/RE3 pin function is digital input
bit 4 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled

PIC16F88X
REGISTER 4-1: CONFIGURATION WORD 1 (ADDRESS: 2007h) (CONTINUED)
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
110 = RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/
CLKIN
100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/
CLKIN
011 = EC oscillator: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/
CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN
REGISTER 4-2: CONFIGURATION WORD 2 (ADDRESS: 2008h)

U-1 U-1 U-1 R/P-1 R/P-1 R/P-1 U-1
— — — WRT1 WRT0 BOR4V —
bit 13 bit7
U-1 U-1 U-1 U-1 U-1 U-1 U-1

— — — — — — —
bit 6 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Default value ‘1’ = Bit is erased ‘0’ = Bit is programmed
P = Programmable bit x = Bit is unknown
bit 13-11 Unimplemented: Read as ‘1’

bit 10-9 WRT<1:0>: Flash Program Memory Write Enable bits
PIC16F886/887
00 = 0000h to 0FFFh write-protected, 1000h to 1FFFh may be modified by EECON control
01 = 0000h to 07FFh write-protected, 0800h to 1FFFh may be modified by EECON control
11 = Write protection off
PIC16F883/884
PIC16F882
00 = 0000h to 07FFh write protected, entire program memory is write protected
01 = 0000h to 03FFh write protected, 0100h to 07FFh may be modified by EECON control
10 = 0000h to 00FFh write protected, 0100h to 07FFh may be modified by EECON control
bit 8 BOR4V: Brown-out Reset Selection bit
1 = Brown-out Reset set to 4V
0 = Brown-out Reset set to 2.1V
bit 7-0 Unimplemented: Read as ‘1’

PIC16F88X
REGISTER 4-3: CALIBRATION WORD (CONFIG: 2009h)

U-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
— FCAL6 FCAL5 FCAL4 FCAL3 FCAL2 FCAL1
bit 13 bit 7
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

FCAL0 POR2 POR1 POR0 BOR2 BOR1 BOR0
bit 6 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
x = Bit is unknown
bit 13 Unimplemented
bit 12-6 FCAL<6:0>: Internal Oscillator Calibration bits(2)
0111111 = Maximum frequency
•
•
0000001
0000000 = Center frequency. Oscillator is running at the calibrated frequency
1111111
•
•
1000000 = Minimum frequency
bit 5-3 POR<2:0>: POR Calibration bits(2)
111 = Maximum POR voltage
110 =
101 =
100 = Center POR voltage
001 =
010 =
011 = Minimum BOR voltage
bit 2-0 BOR<2:0>: BOR Calibration bits(2)
111 = Maximum POR voltage
110 =
101 =
001 =
010 =
011 = Minimum BOR voltage
Note 1: This location does not participate in Bulk Erase operations.
2: The calibration bits must be read, preserved, then replaced by the user during Program Memory Bulk Erase operation with PC = 2009h.
4.2 Device ID Word

The device ID word for the PIC16F88X is located at
2006h. This location can not be erased.
TABLE 4-1: DEVICE ID VALUES

Device ID Values
Device
Dev Rev
PIC16F882 10 0000 000 x xxxx
PIC16F883 10 0000 001 x xxxx
PIC16F884 10 0000 010 x xxxx
PIC16F886 10 0000 011 x xxxx
PIC16F887 10 0000 100 x xxxx

PIC16F88X
5.0 CODE PROTECTION 5.3 Checksum Computation
For PIC16F88X, once the CP bit is programmed to ‘0’, 5.3.1 CHECKSUM
all program memory locations read all ‘0’s. Further pro-
gramming is disabled for the entire program memory. Checksum is calculated by reading the contents of the
PIC16F88X memory locations and adding up the
Data memory is protected with its own Code-Protect bit opcodes up to the maximum user addressable location,
(CPD). When enabled, the data memory can still be (e.g., 0x1FFF for PIC16F886/887). Any carry bits
programmed and read using the EECON1 register exceeding 16 bits are neglected. Finally, the Configura-
(See the applicable data sheet for more information). tion Words (appropriately masked) are added to the
The user ID locations and the Configuration Word can checksum. Checksum computation for the PIC16F88X
be programmed and read out regardless of the state of devices is shown in Table 5-1.
the CP and CPD bits. The checksum is calculated by summing the following:
• The contents of all program memory locations
5.1 Disabling Code Protection
• The Configuration Words, appropriately masked
It is recommended to use the procedure in Figure 3-21 • Masked user ID locations (when applicable)
to disable code protection of the device. This sequence
The Least Significant 16 bits of this sum is the
will erase the program memory, data memory, Configu-
checksum.
ration Word (0x2007-0x2008) and user ID locations
(0x2000-0x2003). The Calibration Words (0x2009) will The following table describes how to calculate the
not be erased. checksum for each device. Note that the checksum
calculation differs depending on the code-protect
Note: To ensure system security, if CPD bit = 0, setting. Since the program memory locations read out
Bulk Erase Program Memory command zeroes when code-protected, the table describes how
will also erase data memory. to manipulate the actual program memory values to
simulate values that would be read from a protected
5.2 Embedding Configuration Words device. When calculating a checksum by reading a
and User ID Information in the Hex device, the entire program memory can simply be read
File and summed. The Configuration Words and user ID
locations can always be read regardless of code-
To allow portability of code, the programmer is required protect setting.
to read the Configuration Words and user ID locations
from the hex file when loading the hex file. If Configura- Note: Some older devices have an additional
tion Words information was not present in the hex file, value added in the checksum. This is to
a simple warning message may be issued. Similarly, maintain compatibility with older device
while saving a hex file, Configuration Words and user programmer checksums.
ID information must be included. An option to not
include this information may be provided.
Specifically for the PIC16F88X, the data memory
should also be embedded in the hex file (see
Section 5.3.2 “Embedding Data Memory Contents
In Hex File”).
Microchip Technology Incorporated feels strongly that
this feature is important for the benefit of the end
customer.

PIC16F88X
TABLE 5-1: CHECKSUM COMPUTATIONS
0x25E6 at 0
Code Blank
Device Checksum* and Max
Protect Value
Address
PIC16F882 CP = 1 SUM[0x0000:0x07FF] + (CFG1 & 0x3FFF) + (CFG2 & 0x0700) 0x3EFF 0x0ACD
CP = 0 (CFG1 & 0x3FFF) + (CFG2 & 0x0700) + SUM_ID 0x85BE 0x518C
PIC16F883 CP = 1 SUM[0x0000:0x0FFF] + (CFG1 & 0x3FFF) + (CFG2 & 0x0700) 0x36FF 0x02CD
CP = 0 (CFG1 & 0x3FFF) + (CFG2 & 0x0700) + SUM_ID 0x7DBE 0x498C
PIC16F884 CP = 1 SUM[0x0000:0x0FFF] + (CFG1 & 0x3FFF) + (CFG2 & 0x0700) 0x36FF 0x02CD
PIC16F886 CP = 1 SUM[0x0000:0x1FFF] + (CFG1 & 0x3FFF) + (CFG2 & 0x0700) 0x26FF 0xF2CD
PIC16F887 CP = 1 SUM[0x0000:0x1FFF] + (CFG1 & 0x3FFF) + (CFG2 & 0x0700) 0x26FF 0xF2CD
Legend: CFG = Configuration Word. Example calculations assume Configuration Word is erased (all ‘1’s).
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant
nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234.
The 4 LSbs of the unprotected checksum is used for the example calculations.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
5.3.2 EMBEDDING DATA MEMORY

CONTENTS IN HEX FILE
The programmer should be able to read data memory
information from a hex file and conversely (as an
option), write data memory contents to a hex file along
with program memory information and Configuration
Words (0x2007-0x2008) and user ID (0x2000-0x2003)
information.
The physical address range of the 256 data memory is
0x0000-0x00FF. However, these addresses are logi-
cally mapped to address 0x2100-0x21FF for use in
writing assembly code. This provides a way of differen-
tiating between the data and program memory loca-
tions in this range. The format for data memory storage
is one data byte per address location, LSb aligned. A
simple example of data memory is given below:
org 0x2100
de “My Program, v1.0”, 0

PIC16F88X
6.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 6-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY

MODE
Standard Operating Conditions (unless otherwise stated)
AC/DC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C
Operating Voltage 4.5V ≤ VDD ≤ 5.5V
Sym Characteristics Min Typ Max Units Conditions/Comments
General
VDD level for read/write operations,
2.0 — 5.5 V
program and data memory
VDD
VDD level for Bulk Erase operations,
4.5 — 5.5 V
program and data memory
High voltage on MCLR for
VPP 10 — 12 V
Program/Verify mode entry
MCLR rise time (VSS to VHH) for
TVHHR — — 1.0 μs
Program/Verify mode entry
TPPDP Hold time after VPP changes 5 — — μs
VIH1 (ICSPCLK, ICSPDAT) input high level 0.8 VDD — — V
VIL1 (ICSPCLK, ICSPDAT) input low level 0.2 VDD — — V
ICSPCLK, ICSPDAT setup time
TSET0 before MCLR↑ (Program/Verify mode 100 — — ns
selection pattern setup time)
THLD0 Hold time after VPP changes 0 — 1 μs
Serial Program/Verify
TSET1 Data in setup time before clock↓ 100 — — ns
THLD1 Data in hold time after clock↓ 100 — — ns
Data input not driven to next clock
input (delay required between
TDLY1 1.0 — — μs
command/data or command/
command)
Delay between clock↓ to clock↑ of
TDLY2 1.0 — — μs
next command or data
Clock↑ to data out valid (during a
TDLY3 — — 80 ns
Read Data command)
TERA Erase cycle time — 5 6 ms
Programming cycle time (internally 3 — Program memory
TPROG1 — ms
timed) 6 — Data memory
Programming cycle time (externally 10°C ≤ TA ≤ +40°C
TPROG2 2 — 2.5 ms
timed) Program memory
Time delay from program to compare
TDIS 100 — — μs
(HV discharge time)

PIC16F88X
APPENDIX A: REVISION HISTORY
Revision A (3/06)
Original release.
Revision B (8/06)
Revised Section 2.1 (paragraph 2); Section 3.0 (para-
graph 5); Section 3.2 (paragraph 1); Section 3.2.3
(Note); Section 3.2.4 (paragraph 1 and No. 3); Section
3.2.5 (Notes); Section 4.1 (paragraph 1); Register 4-1
(bit 13 DEBUG and bit 5 MCLRE); Register 4-2 (bit 10-
9 WRT); Register 4-3 (bit 5-3 POR and bit 2-0 BOR);
Section 5.3.1 (paragraph 1); Table 6-1 (TPROG1 min
and max).
Revision C (03/07)
Added the PIC16F882 device.

PIC16F88X
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
ensure that your application meets with your specifications.
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
MICROCHIP MAKES NO REPRESENTATIONS OR
SmartShunt are registered trademarks of Microchip
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
Technology Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
QUALITY, PERFORMANCE, MERCHANTABILITY OR and The Embedded Control Solutions Company are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
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PIC16F88X Memory Programming Specification

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PIC16F88X

PIC16F88X Memory Programming Specification

1.0 PROGRAMMING THE

1.1 Hardware Requirements

TABLE 1-1: PIN DESCRIPTIONS IN PROGRAM/VERIFY MODE

© 2007 Microchip Technology Inc. Advance Information DS41287C-page 1

FIGURE 1-2: PIC16F882/883/886 28-PIN QFN DIAGRAM

DS41287C-page 2 Advance Information © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. Advance Information DS41287C-page 3

DS41287C-page 4 Advance Information © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. Advance Information DS41287C-page 5

DS41287C-page 6 Advance Information © 2007 Microchip Technology Inc.

2001 User ID Location

2003 User ID Location 2080

2007 Configuration Word 1

2008 Configuration Word 2

2009 Calibration Word 3FFF

© 2007 Microchip Technology Inc. Advance Information DS41287C-page 7

2001 User ID Location

2003 User ID Location 2080

2007 Configuration Word 1

2008 Configuration Word 2

2009 Calibration Word 3FFF

DS41287C-page 8 Advance Information © 2007 Microchip Technology Inc.

Implemented Program Memory

2000 User ID Location

2001 User ID Location

2003 User ID Location 2080

2007 Configuration Word 1

2008 Configuration Word 2

2009 Calibration 3FFF

© 2007 Microchip Technology Inc. Advance Information DS41287C-page 9

The second entry method, “VDD-first”, is entered by

DS41287C-page 10 Advance Information © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. Advance Information DS41287C-page 11

DS41287C-page 12 Advance Information © 2007 Microchip Technology Inc.

TABLE 3-1: COMMAND MAPPING FOR PIC16F88X

© 2007 Microchip Technology Inc. Advance Information DS41287C-page 13

FIGURE 3-4: LOAD CONFIGURATION COMMAND

0 00 0 0 x x strt_bit LSb MSb stp_bit

3.2.6.2 Load Data For Program Memory

FIGURE 3-5: LOAD DATA FOR PROGRAM MEMORY COMMAND

0 1 0 0 x x strt_bit LSb MSb stp_bit

DS41287C-page 14 Advance Information © 2007 Microchip Technology Inc.

FIGURE 3-6: LOAD DATA FOR DATA MEMORY COMMAND

3.2.6.4 Read Data From Program Memory

FIGURE 3-7: READ DATA FROM PROGRAM MEMORY COMMAND

Input Output Input

© 2007 Microchip Technology Inc. Advance Information DS41287C-page 15

FIGURE 3-8: READ DATA FROM PROGRAM MEMORY COMMAND

Input Output Input

3.2.6.6 Increment Address

FIGURE 3-9: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)

DS41287C-page 16 Advance Information © 2007 Microchip Technology Inc.

FIGURE 3-10: BEGIN PROGRAMMING (INTERNALLY TIMED)

3.2.6.8 Begin Programming (Externally

FIGURE 3-11: BEGIN PROGRAMMING COMMAND (EXTERNALLY TIMED

© 2007 Microchip Technology Inc. Advance Information DS41287C-page 17