Combinational Logic with MSI and LSI

Part I
 Objectives

• Decoders
• Encoders
• Multiplexers
• DeMultiplexers
 Functional Blocks

• Digital systems
consists of many
components (blocks)
• Useful blocks needed
in many designs
• Arithmetic blocks
• Decoders
• Encoders
• Multiplexers

iPhone motherboard (torontophonerepair.com)

• Discrete Quantities of Information are
represented by binary codes
• A binary code of n bits is capable of
representing up to 2n distinct elements of
the coded information.
 Decoder

n-to-2n .
n inputs . 2n outputs
.
Decoder
.

• Decoder is a device that identifies or recognize or

detects a particular code.
• Decoding - the conversion of an n-bit input code to a
maximum of 2n – bit unique output code (n <= m <= 2n )
• i.e. n-bit inputs can have 2n possible combinations.
• Circuits that perform decoding are called decoders
• A decoder is a minterm generator
 Decoder (Uses)

•Decode a 3-bit op-codes: •Home automation:

Add
Sub
And
op0 3-to-8 Xor
op1 Decoder Not Light
op2 C0 2-to-4 A/C
Load
Store C1 Decoder Door
Jump Light-A/C

Load a
Add b
Store c
.
.
 Decoder with Enable

• A decoder can have an additional input signal called

the enable which enables or disables the output
generated by the decoder

n-to-2n .
n inputs . 2n outputs
.
Decoder
.

Enable bit
 2-to-4 Decoder

• A 2-to-4 Decoder
– 2 inputs (A1, A0)
– 22 = 4 outputs (D3, D2, D1, D0)
 2-to-4 Decoder

• A 2-to-4 Decoder
– 2 inputs (A1, A0)
– 22 = 4 outputs (D3, D2, D1, D0)

– Truth Table

A1 A0 D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
 2-to-4 Decoder

• A 2-to-4 Decoder
– 2 inputs (A1, A0)
– 22 = 4 outputs (D3, D2, D1, D0)

– Truth Table

A1 A0 D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Src: Mano’s book
 2-to-4 Decoder with Enable

Truth Table

EN A1 A0 D0 D1 D2 D3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
 2-to-4 Decoder with Enable

Truth Table

EN A1 A0 D0 D1 D2 D3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

Src: Mano’s book

3-to-8 Decoder

D0
D1
D2
A0 3-to-8 D3
A1
Decoder D4
A2 D5
D6
D7
3-to-8 Decoder

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7
D0
D1 0 0 0 1 0 0 0 0 0 0 0
D2 0 0 1 0 1 0 0 0 0 0 0
A0 3-to-8 D3
A1 0 1 0 0 0 1 0 0 0 0 0
Decoder D4
A2 D5
D6 0 1 1 0 0 0 1 0 0 0 0
D7
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
3-to-8 Decoder

D0
D1
D2
A0 3-to-8 D3
A1
Decoder D4
A2 D5
D6
D7
3-to-8 Decoder (using 2 2-to-4 decoders)

D0
D0 A0 2-to-4 D1
D1 A1 Decoder D2
D2 D3
A0 E
3-to-8 D3
A1
Decoder D4 A2
A2 D5
D6
D7 D4
A0 2-to-4 D5
A1 Decoder D6
E D7
 Decoder-Based Combinational Circuits

• A Decoder generates all the minterms

• A boolean function can be expressed as a sum
of minterms
• Any boolean function can be implemented
using a decoder and an OR gate.
• Note: The Boolean function must be
represented in terms of its minterms and not its
minimized form
 Decoder-Based Combinational Circuits
(Example)

S = ∑m (1,2,4,7)
C = ∑m (3,5,6,7)
X Y Z C S
3 inputs and 8 possible minterms
0 0 0 0 0 3-to-8 decoder can be used for implementing this circuit
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
 Decoder-Based Combinational Circuits
(Example)

S = ∑m (1,2,4,7)
C = ∑m (3,5,6,7)
X Y Z C S
3 inputs and 8 possible minterms
0 0 0 0 0 3-to-8 decoder can be used for implementing this circuit
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Src: Mano’s book

 Decoder-Based Combinational Circuits
(Summary)

• Good if:
• Many output functions with same inputs
• Each output has few minterms
• Hint:
• Check if the function complement has fewer
minterms and use NOR instead of OR.
 Encoder

. 2n-to-n
2n inputs . n outputs
.
Encoder
.

• Encoding - the opposite of decoding - the conversion of

an m-bit input code(2n) to a n-bit output code with
such that each valid code word produces a unique output code
• Circuits that perform encoding are called encoders
• An encoder has 2n (or fewer) input lines and n output lines
which generate the binary code corresponding to the input
values
• Typically, an encoder converts a code containing exactly one
bit that is 1 to a binary code corresponding to the position in
which the 1 appears.
8-to-3 Encoder

•Description:
•23 = 8 inputs, 3 outputs

D0 •one input =1, others = 0’s

D1
D2
D3 8-to-3 A0 •Each input generate unique
D4 Encoder A1
D5 A2 binary code
D6
D7
8-to-3 Encoder (truth table)

inputs outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
D0
D1 0 0 0 0 0 0 0 1 0 0 0
D2
D3 8-to-3 A0 0 0 0 0 0 0 1 0 0 0 1
D4 Encoder A1 0 0 0 0 0 1 0 0 0 1 0
D5 A2
D6 0 0 0 0 1 0 0 0 0 1 1
D7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 8-to-3 Encoder (truth table)

inputs outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
1 D0
0 D1 0 0 0 0 0 0 0 1 0 0 0
0 D2
0 D3 8-to-3 A0 0 0 0 0 0 0 0 1 0 0 0 1
0 D4 Encoder A1 0
0 0 0 0 0 1 0 0 0 1 0
D5 A2 0
0
0 D6 0 0 0 0 1 0 0 0 0 1 1
0 D7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 8-to-3 Encoder (truth table)

inputs outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 D0
1 D1 0 0 0 0 0 0 0 1 0 0 0
0 D2
0 D3 8-to-3 A0 1 0 0 0 0 0 0 1 0 0 0 1
0 D4 Encoder A1 0
0 0 0 0 0 1 0 0 0 1 0
D5 A2 0
0
0 D6 0 0 0 0 1 0 0 0 0 1 1
0 D7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 8-to-3 Encoder (truth table)

inputs outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 D0
0 D1 0 0 0 0 0 0 0 1 0 0 0
0 D2
0 D3 8-to-3 A0 1 0 0 0 0 0 0 1 0 0 0 1
0 D4 Encoder A1 0
0 0 0 0 0 1 0 0 0 1 0
D5 A2 1
1
0 D6 0 0 0 0 1 0 0 0 0 1 1
0 D7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 8-to-3 Encoder (truth table)

inputs outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 D0
0 D1 0 0 0 0 0 0 0 1 0 0 0
0 D2
0 D3 8-to-3 A0 1 0 0 0 0 0 0 1 0 0 0 1
0 D4 Encoder A1 1
0 0 0 0 0 1 0 0 0 1 0
D5 A2 1
0
0 D6 0 0 0 0 1 0 0 0 0 1 1
1 D7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 8-to-3 Encoder (equations)

inputs outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
D0
D1 0 0 0 0 0 0 0 1 0 0 0
D2
D3 8-to-3 A0 0 0 0 0 0 0 1 0 0 0 1
D4 Encoder A1 0 0 0 0 0 1 0 0 0 1 0
D5 A2
D6 0 0 0 0 1 0 0 0 0 1 1
D7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
Output equations:
0 1 0 0 0 0 0 0 1 1 0
A0 = ? 1 0 0 0 0 0 0 0 1 1 1
A1 = ?
A2 = ? Note: This truth table is not complete! Why?
 8-to-3 Encoder (equations)

inputs outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
D0
D1 0 0 0 0 0 0 0 1 0 0 0
D2
D3 8-to-3 A0 0 0 0 0 0 0 1 0 0 0 1
D4 Encoder A1 0 0 0 0 0 1 0 0 0 1 0
D5 A2
D6 0 0 0 0 1 0 0 0 0 1 1
D7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
Output equations:
0 1 0 0 0 0 0 0 1 1 0
A0 = D1 + D3 + D5 + D7 1 0 0 0 0 0 0 0 1 1 1
A1 = ?
A2 = ?
 8-to-3 Encoder (equations)

inputs outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
D0
D1 0 0 0 0 0 0 0 1 0 0 0
D2
D3 8-to-3 A0 0 0 0 0 0 0 1 0 0 0 1
D4 Encoder A1 0 0 0 0 0 1 0 0 0 1 0
D5 A2
D6 0 0 0 0 1 0 0 0 0 1 1
D7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
Output equations:
0 1 0 0 0 0 0 0 1 1 0
A0 = D1 + D3 + D5 + D7 1 0 0 0 0 0 0 0 1 1 1
A1 = D2 + D3 + D6 + D7
A2 = ?
 8-to-3 Encoder (equations)

inputs outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
D0
D1 0 0 0 0 0 0 0 1 0 0 0
D2
D3 8-to-3 A0 0 0 0 0 0 0 1 0 0 0 1
D4 Encoder A1 0 0 0 0 0 1 0 0 0 1 0
D5 A2
D6 0 0 0 0 1 0 0 0 0 1 1
D7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
Output equations:
0 1 0 0 0 0 0 0 1 1 0
A0 = D1 + D3 + D5 + D7 1 0 0 0 0 0 0 0 1 1 1
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
 8-to-3 Encoder (circuit)

D1
D0 D3
D1 D5 A0
D2 D7
D3 8-to-3 A0
D4 Encoder A1 D2
A2 D3
D5 D6
A1
D6 D7
D7
D4
D5 A2
D6
Output equations: D7

A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
 8-to-3 Encoder (limitations)

inputs outputs
Two Limitations:
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
1. Two or more inputs = 1 0 0 0 0 0 0 0 1 0 0 0
• Example: D3 = D6 = 1
• A2A1A0 = 111 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
2. All inputs = 0
0 0 0 0 1 0 0 0 0 1 1
• Same as D0 =1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
Output equations:
0 1 0 0 0 0 0 0 1 1 0
A0 = D1 + D3 + D5 + D7 1 0 0 0 0 0 0 0 1 1 1
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
 Priority Encoder

• Address the previous two limitations

1. Two or more inputs = 1
– Consider the bit with highest priority
2. All inputs = 0
– Add another output v to indicate this
combination
 4-to-2 Priority Encoder

Description:
• 22 = 4 inputs, 2 + 1 outputs
• Two or more 1’s take highest
priority
 4-to-2 Priority Encoder

Description:
• 22 = 4 inputs, 2 + 1 outputs
• Two or more 1’s take highest
priority

inputs outputs
D3 D2 D1 D0 A1 A0 V
This is a condensed truth table!
0 0 0 0 X X 0 It has only 5 rows instead of 16!
0 0 0 1 0 0 1
0 0 1 X 0 1 1 Row 3 = 2 combinations
Row 4 = 4 combinations
0 1 X X 1 0 1 Row 5 = 8 combinations
1 X X X 1 1 1
 4-to-2 Priority Encoder

Description:
• 22 = 4 inputs, 2 + 1 outputs
• Two or more 1’s take highest
priority

inputs outputs
D3 D2 D1 D0 A1 A0 V
0 0 0 0 X X 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1
 4-to-2 Priority Encoder

Description:
• 22 = 4 inputs, 2 + 1 outputs
• Two or more 1’s take highest
priority

inputs outputs
D3 D2 D1 D0 A1 A0 V
0 0 0 0 X X 0
0 0 0 1 0 0 1
Equations:
0 0 1 X 0 1 1 A0 = D3 + D1 D2’
0 1 X X 1 0 1 A1 = D2 + D3
V = D0 + D1 + D2 + D3
1 X X X 1 1 1
 4-to-2 Priority Encoder

Description:
• 22 = 4 inputs, 2 + 1 outputs
• Two or more 1’s take highest
priority

inputs outputs
D3 D2 D1 D0 A1 A0 V
0 0 0 0 X X 0
0 0 0 1 0 0 1
Equations:
0 0 1 X 0 1 1 A0 = D3 + D1 D2’
0 1 X X 1 0 1 A1 = D2 + D3
V = D0 + D1 + D2 + D3
1 X X X 1 1 1
 Multiplexers (Data Selectors)

• Multiplexing means sharing.

• Multiplexer Is a combinational circuit
• Has a single output
• Directs one of 2n input to the output
• Input to output direction is done based on a set of n
select bits

2n x 1
2n inputs one output
MUX

n select lines
• Multiplexer selects 1-out-of-2n input data sources and
transmits the selected data to a single output channel
 2x1 MUX

• A 2x1 multiplexer (MUX) will have 2 input lines and 1

select line

D0 2x1 Y
D1 MUX

S0

• Y=D0 for S0=0, and

• Y=D1 for S0=1
• Minimizing will result in: Y = S0’.D0 + S0.D1
 4x1 MUX

• A 4x1 MUX will have 4 input lines (D0, D1, D2, D3) and 1 output Y
with 2 Select Lines (S0, S1)
• The output for different select values is defined as:
• S0S1 = 00, Y = D0
D0
• S0S1 = 01, Y = D1
D1
• S0S1 = 10, Y = D2 4x1
D2 MUX Y
• S0S1 = 11, Y = D3
D3

S1 S0
• Y = S1S0D0 + S1S0D1 + S1S0D2 + S1S0D3
• The output Y depends on the minterms of the Select lines
 Quad 2x1 MUX

• Does multiplexing of two 4-bit numbers.

• Has a 4-bit output and a single select line
• Is built using four 2x1 MUXes

A0 2x1 A1 2x1
Y0 Y1
B0 MUX B1 MUX

S0 S0
A2 2x1 A3 2x1
Y2 Y3
B2 MUX B3 MUX

S0 S0
 Quad 2x1 MUX

A0
A1
A2 Y0
QUAD
A3 Y1
Y = A If S0 = 0 2X1
B0 Y2
Y = B if S0=1 MUX
B1 Y3
B2
B3

S0
 MUX-based Design

• A MUX can be used to implement any function

expressed using its minterms

• Example: Implement F(A,B,C)=∑(1,3,5,6) using MUXes

• Solution1:
• We can use a MUX with the number of select lines
equal to the number of input variables of the function.

Since this function has 3 input variables, it will require

3 select lines, i.e. an 8x1 MUX
MUX-based Design (n-Select lines)

D0
F(A,B,C)=∑(1,3,5,6)
0
1 D1 A B C F
0 D2 0 0 0 0
1 D3 0 0 1 1
0 D4 Y
0 1 0 0
1 D5
S0 0 1 1 1
1 D6 S1
S2 1 0 0 0
0 D7
1 0 1 1
1 1 0 1
A B C
1 1 1 0
 MUX-based Design (n-1 Select lines)

• Implement the function F(A,B,C) =∑(1,2,6,7)

• We will use 2 select lines instead of the 3

required for the three input variables
• A => S1, B=> S0

• The third variable C and its complement will

serve as two of the inputs to the MUX
 MUX-based Design (n-1 Select lines)

A B C F
F(A,B,C)=∑(1,2,6,7)
0 0 0 0
F=C
0 0 1 1 C D0

0 1 0 1 C’ D1

F = C’ 0 D2 F
0 1 1 0 S1 S0
D3
1
1 0 0 0
F=0 A B
1 0 1 0
1 1 0 1
F=1
1 1 1 1
 Another Example

• Implement the function

F(A,B,C,D)=∑(1,3,4,11,12,13,14,15)

• We can implement this function with 3

Select lines => an 8x1 MUX is required
 Example

F(A,B,C,D)=∑(1,3,4,11,12,13,14,15)
A B C D F

0 0 0 0 0
F=D
0 0 0 1 1 D D0
0 0 1 0 0
F=D D1
0 0 1 1 1
D2
0 1 0 0 1
F = D’ 8x1
0 1 0 1 0 D3 F
0
0 1 1 0 0
F=0 D4 MUX
0 1 1 1 0
1 0 0 0 0
D5
F=0
1 0 0 1 0 1 D6
1 0 1 0 0
F=D D7
1 0 1 1 1 S2 S1 S0
1 1 0 0 1
F=1
1 1 0 1 1
1 1 1 0 1
F=1 A B C
1 1 1 1 1
 DeMultiplexer

• Performs the inverse of the operation of a MUX

• It has one input line, the input from which is transmitted
to one of 2n output lines
• The output lines are selected based on the select inputs
(n select lines)

1x2 D0
E
DeMUX D1

S
 1x4 DeMUX

D0
1x4 D1
E
DeMUX D2
D3

S0 S1

• The circuit has an input E, the outputs are given by:

• D0 = E, if S0S1=00 D0 = S1’S0’ E
• D1 = E, if S0S1=01 D1 = S1’S0 E
• D2 = E, if S0S1=10 D2 = S1S0’ E
• D3 = E, if S0S1=11 D3 = S1S0 E
 DeMUX/Decoder

•The circuit diagram of a 1x4 E

DeMUX resembles a 2x4 S1 S0
D0
Decoder with an Enable input
•For the decoder, the inputs
are A1 and A0, and the signal D1
E is the Enable
D2
•For the DeMUX, the inputs
S1 and S0 are the select
inputs and E is the actual D3
input
 Summary

• Useful Functional Blocks

• Decoders
• Encoders
• Multiplexers
• DeMultiplexers
• Can be used to build bigger systems
Combinational Logic with MSI and LSI
Part II
 Objectives

• Magnitude comparator
• Design of 4-bit magnitude comparator

• Design Examples using MSI components

• Adding Three 4-bit numbers
• Building 4-to-16 Decoders with 2-to-4
Decoders
• Getting the larger of 2 numbers (Maximum)
• Excess-3 Code Converter
 Magnitude Comparator

• Definition: A magnitude comparator is a combinational

circuit that compares two numbers A & B to determine
whether:
– A > B, or
– A = B, or n-bit input n-bit magnitude GT
– A<B A comparator

• Inputs
EQ
– First n-bit number A n-bit input
– Second n-bit number B B
LE
• Outputs
– 3 output signals (GT, EQ, LT), where:
• GT = 1 IF A > B
• EQ = 1 IF A = B
• LT = 1 IF A < B
• Note: Exactly One of these 3 outputs equals 1, while the
other 2 outputs are 0`s
 Example 1: Magnitude Comparator (4-bit)

• Problem: Design a magnitude comparator that

compares two 4-bit numbers A and B and determines
whether:
– A > B, or 4-bit input 4-bit magnitude GT
A comparator
– A = B, or
– A<B EQ
4-bit input
B
LE
 Example 1: Magnitude Comparator (4-bit)

• Solution:
• Inputs: 8-bits (A ⇒ 4-bits , B ⇒ 4-
bits)
4-bit input 4-bit magnitude GT
– A and B are two 4-bit numbers
A comparator
• Let A = A3A2A1A0 , and
• Let B = B3B2B1B0 EQ
4-bit input
• Inputs have 28 (256) possible B
LE
combinations (size of truth table
and K-map?)
• Not easy to design using
conventional techniques
The circuit possesses certain amount of regularity
⇒ can be designed algorithmically.
 Example 1: Magnitude Comparator (4-bit)

• Designing EQ:

• Define Xi = Ai xnor Bi = Ai Bi + Ai’ Bi’ for i =0, 1, 2 and 3

• ➔ Xi = 1 IF Ai = Bi ∀ i =0, 1, 2 and 3

• ➔ Xi = 0 IF Ai ≠ Bi 4-bit input 4-bit magnitude GT

A comparator

Therefore the condition for A = B or EQ=1 IF EQ

– A3= B3 → (X3 = 1), and 4-bit input

– A2= B2 → (X2 = 1), and B LE

– A1= B1 → (X1 = 1), and
– A0= B0 → (X0 = 1).

• Thus, EQ=1 IF X3 X2 X1 X0 = 1. In other words,

• EQ = X3 X2 X1 X0
 Example 1: Magnitude Comparator (4-bit)

• Designing GT and LT:

GT = 1 if A > B:
• If A3 > B3 → A3 = 1 and B3 = 0
• If A3 = B3 and A2 > B2
• If A3 = B3 and A2 = B2 and A1 > B1
• If A3 = B3 and A2 = B2 and A1 = B1 and A0 > B0

• Therefore,
– GT = A3B3‘ + X3 A2 B2‘ + X3 X2 A1 B1‘ + X3 X2 X1A0 B0‘
• Similarly,
– LT = A3’B3 + X3 A2‘B2 + X3 X2 A1’B1 + X3 X2 X1A0’ B0
 Example 1: Magnitude Comparator (4-bit)

• EQ = X3 X2 X1 X0

• GT = A3B3’
+ X3A2B2’
+ X3X2A1B1’
+ X3X2X1A0B0’

• LT = B3A3’
+ X3B2A2’
+ X3X2B1A1’
+ X3X2X1B0A0’

4-bit magnitude comparator

 4-bit Magnitude Comparator

XNOR

= A3' B3 + x3 A2' B2 + x3 x2 A1' B1 + x3 x2 x1 A0' B0

= A3 B3' + x3 A2 B2' + x3 x2 A1 B1' + x3 x2 x1 A0 B0'

= x3 x2 x1 x0
 Example 1: Magnitude Comparator (4-bit)

• Do you need all three outputs?

• Two outputs can tell about the third one
• Example: when A is NOT GREATER THAN B, and A
is NOT LESS THAN B THEN A is EQUAL TO B
• Therefore, we can save some logic gates:

4-bit input 4-bit magnitude GT

A comparator
EQ
EQ
4-bit input
B LE
 Example 2: Adding three 4-bit numbers

Problem: Add three 4-bit numbers using standard MSI

combinational components
Solution:
Let the numbers be X3X2X1X0, Y3Y2Y1Y0, Z3Z2Z1Z0 ,

X3X2X1X0 S3S2S1S0
+ Y3Y2Y1Y0 + Z3Z2Z1Z0
------------------- -------------------
C4 S3S2S1S0 D4 F3F2F1F0
Note: C4 and D4 is generated in position 4. They must be
added to generate the most significant bits of the result
Example 2: Adding three 4-bit numbers
 Example 3: 4-to-16 Decoder

A3 A2 A1 A0 Output
Problem: Design a 4x16 Decoder 0 0 0 0 D0

using 2x4 Decoders A3A2 = 00 0 0 0 1 D1

0 0 1 0 D2
0 0 1 1 D3
Solution: 0 1 0 0 D4

• Each group combination holds A3A2 = 01 0 1 0 1 D5

0 1 1 0 D6
a unique value for A3A2
0 1 1 1 D7
- One Decoder can be therefore 1 0 0 0 D8
used with inputs: A3A2 A3A2 = 10
1 0 0 1 D9
1 0 1 0 D10
- Four more decoders are
1 0 1 1 D11
needed for representing each 1 1 0 0 D12
individual color combination 1 1 0 1 D13
A3A2 = 11
1 1 1 0 D14
1 1 1 1 D15
 Example 3: 4-to-16 Decoder

D0
A0 2x4 D1
A1 Decoder D2
D3

D4
A0 2x4 D5
A1 Decoder D6
D7
A2 2x4
A3 Decoder D8
A0 2x4 D9
A1 Decoder D10
D11

D12
A0 2x4 D13
A1 Decoder D14
D15
 Example 4: The larger of 2 numbers

Problem: Given two 4-bit unsigned numbers, design a

circuit such that the output is the larger of the two
numbers

Solution: We will use a magnitude comparator and a

Quad 2x1 MUX. How?
 Example 4: The larger of 2 numbers

B0
B1
A0 B2 Y0
A1
QUAD
B3 Y1
A2 A>B
4-bit GT A0 2X1 Y2
A3
A<B
Magnitude LT A1 MUX Y3
B0 A=B
Comparator EQ A2
B1
B2
A3
B3 For So=1, A
S0 is selected,
For So=0, B
is selected
 Example 5: Excess-3 Code Converter

Problem: Design an excess-3 code converter that takes as input a

BCD number, and generates an excess-3 output.
Solution: Use decoders and encoders
W X Y Z A B C D
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0
Example 5: Excess-3 Code Converter

4-to-16 line Decoder 16-to-4 line Encoder

O0 I0
O1 I1
O2 I2
O3 I3
O4 I4
Z O5 I5
D0 D0 ?
I6
Y D1 O6
D1 ?
O7 I7
X D2
I8 D2 ?
W D3 O8
I9 D3 ?
O9
O10 I10
O11 I11
O12 I12
O13 I13
O14 I14
O15 I15

What will be the output?

 Example 5: Excess-3 Code Converter

• A decoder can be used with the

inputs being W,X,Y,Z
• It will be a 4x16 decoder, with only a
single output bit equal to 1 for any
input combination
• An encoder (16x4) will take as input
the 16 bit output from the decoder,
and will generate the appropriate
output in excess-3 format
• For this to function correctly, the
output from the decoder must be
displaced 3 places while being
connected to the encoder input
• It may be noted that outputs
10,11,12,13,14,15 of the decoder
are not used – since we are dealing
with BCD
 Summary

• Design = Different possibilities

• Better designer = more practice
• More design examples in the textbook