Unit-7

Sequential logic circuit

Digital Electronics (DE)

Code: 01EC0102 2nd sem

Information and Communication Technology

Prepared by Prof.Hetal Dave
 Outline
• Ripple/Asynchronous Counters
 Loopingo Ripple up-down, Modulo or Modulus counter
• Synchronous Counters
o Up counter, Down counter using different FFs
o Decade and BCD counter
o Presettable Counters
o Decoding a Counter
o Designing Counters with Arbitrary Sequences
• Registers
o Buffer, Shift, Bidirectional, Universal
o applications of shift registers,
❖ serial to parallel converter, parallel to serial converter
❖ ring counter, sequence generator,
Section - 2
 Registers
 As a flip-flop (FF) can store only one bit of data, a 0 or a 1, it is referred to as a single-bit
register.
 A register is a group of FFs used to store binary data.
 The storage capacity of a register is the number of bits (1s and 0s) of digital data it can retain.
 Loading a register means setting or resetting the individual FFs, i.e. inputting data into the
register so that their states correspond to the bits of data to be stored.
 To store n bit n D/SR/JK FF are connected together.
 Loading may be serial or parallel.
 In serial loading, data is transferred into the register in serial form i.e. one bit at a time.
 In parallel loading, the data is transferred into the register in parallel form meaning that all the
FFs are triggered into their new states at the same time.
 Types of registers are:
1. Shift register,
2. Bidirectional shift register,
3. Universal shift register 4
Shift Register
 A number of FFs connected together such that data may be shifted into and shifted out of them
is called a shift register.
 Data may be shifted into or out of the register either in serial form or in parallel form.
 So, there are four basic types of shift registers:
1. serial-in, serial-out (SISO)
2. serial-in, parallel-out (SIPO) Find-out IC name
3. parallel-in, serial-out(PISO)
4. parallel-in, parallel-out(PIPO) (Buffer register)
 Data may be rotated left or right. Data may be shifted from left to right or right to left at will, i.e.
in a bidirectional way.
 Also, data may be shifted in serially (in either way) or in parallel and shifted out serially (in
either way) or in parallel.

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 Data transmission in shift register
Serial data
Serial data Serial data input
input output

Parallel data output

Serial-in, serial-out shift-right, shift register Serial-in, parallel-out, shift register

Parallel data input Parallel data input

Serial data
output

Parallel-in, serial-out, shift register Parallel data output

Parallel-in, parallel-out, shift register

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 Serial-in, Serial-out, Shift-right, Shift register
To store 4bit 4 D Flip-flops are connected.

Serial Input
1 0 1 0
10 10 10 0
D1 Q1 D2 Q2 D3 Q3 D4 Q4 Serial output

> FF1 > FF2 > FF3 > FF4

Q1’ Q2’ Q3’ Q4’

CLK

Data = 1010

In SISO n number of clock pulses are required to store n bit word.

For description refer this site: http://studytronics.weebly.com/shift-registers.html
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If data is 1011.Truth table is as below,

To the waveform see this you tube video: https://www.youtube.com/watch?v=zazz_LH1Sxo

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SISO using SR FF

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10
Serial In Parallel Out using DFF(SIPO)

Serial Input QA QB QC QD

D1 Q1 D2 Q2 D3 Q3 D4 Q4

> FF1 > FF2 > FF3 > FF4

CLK

For description refer this site:

http://studytronics.weebly.com/shift-registers.html .
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Serial In Parallel Out using DFF(SIPO)

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 Parallel-in, Parallel-out, Shift register(PIPO)

B0 B1 B2 B3

D0 Q0 D1 Q1 D2 Q2 D3 Q3

> FF0 > FF1 > FF2 > FF3

CLK

QA QB QC QD
• It is called Buffer register.
•In one clock pulse all bits are stored simultaneously . Only one clock pulse is required.
For description refer this site: http://studytronics.weebly.com/shift-registers.html

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Parallel-in, Parallel-out, Shift register(PIPO)

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Parallel-in, Serial-out, Shift register
A 1 B 0 C 1 D 0

01 1
Shift/Load
1 1 1 0 1 1 1 1 1

0 1 0

1
D1 Q1 01 D2 Q2 01 D3 Q3 01 D4 Q4 0

> FF1 > FF2 > FF3 > FF4

CLK

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Parallel-in, Serial-out, Shift register
• The input data will enter in parallel that means at a time to all flip flop and output
will
get serially.

• Then all input are feed the inputs of different 4 number of flip flop. With single clock
pulse all data are enter to all 4 flip flops.

• 4 bit parallel in serial out shift register, A, B, C, and D are the four parallel data input
lines and SHIFT / LOAD (SH / LD) is a control input that allows the four bits of data at
A, B, C, and D inputs to enter into the register in parallel or shift the data in serial.
• if SHIFT / LOAD = 0 then data will be stored and
if SHIFT / LOAD = 1 then data will be shifted.
•
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4 bit Bidirectional shift register
 It is the registers which are capable of shifting the data either right or left depending on the
mode selected.
 If the mode = 1, the data will be shifted towards the right direction
 if the mode = 0, the data will be shifted towards the left direction.
 4- D flip-flops which are connected.
 The input data is connected at two ends of the circuit and depending on the mode selected only
one and gate is in the active state.

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4 bit Bidirectional shift register

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Application of Register
 Temporary data storage i.e. Microprocessor.
 Data transfer and data manipulation .i.e. multiplication and division
by 2.
 Produce time delay to digital circuits.
 Used in communication lines where demultiplexing of a data line into
several parallel line is required.
 Data Converter.
 Ring counter.
 Johnson or Twisted ring counter

https://learn.circuitverse.org/docs/seq-msi/registers.html#serial-in-serial-out

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https://learn.circuitverse.org/docs/seq-msi/counters.html
• Primary purpose is to produce a specified output pattern sequence.
• The total number of states is called its modulus.
•An n-bit counter that counts through all its natural states and does
not skip any of the states has a modulus of 2^n.

• If a counter has m distinct states then it is called a mod-m counter.

•
Asynchronous Counters v/s Synchronous Counters
Asynchronous/Ripple/serial Counters Synchronous/Ring/Johnson/parallel
Counters
FFs are connected in such a way that the There is no connection between the output of
output of the first FF connected to the clock first FF and clock input of next FF and so on.
for the second FF, the output of the second
the clock of the third and so on.
All the FFs are not clocked simultaneously. All the FFs are clocked simultaneously.
Design and implementation is very simple Design and implementation becomes tedious
even for more number of states. and complex as the number of states
increases.
Main drawback of these counters is their low Since clock is applied to all the FFs
speed as the clock is propagated through a simultaneously the total propagation delay is
number of FFs before it reaches the last FF. equal to the propagation delay of only one FF.
Hence they are faster.
the delay is dependent of the size of the counter. the delay is independent of the size of the counter.

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• Group of flip-flops, count a stream of pulses applied to the
counter’s Clock input.
• The output is a binary value whose value is equal to the
number of pulses received at the CK input.

• Mod 4 counter →4 states(0,1,2,3) → 2 bit counter → 2 FF are required.

• Mod 8 counter → 8 states(0,1,2,3,4,5,6,7) → 3 bit counter → 3 FF are required.
• Mod 10 counter(BCD) → 10 states(0,1,2,3,4,5,6,7,8,9) → 4 bit counter → 4 FF are
required.(https://www.youtube.com/watch?v=EVb1cn4QOGM)
• Mod N counter→ N states(0,1,2,3,4………..N-1) → n bit counter → n FF are required.
2-bit Ripple Up-Counter- T FF(MOD-4) Negative Edge-triggered
1 QA 1 QB
Present State Next State
CLK
T1 Q1 T2 Q2 QB QA QB QA
0 0 0 1
CLK > FF1 > FF2 0 1 1 0
1 0 1 1
Q1’ Q2’ 1 1 0 0

CLK

QA 0 1 0 1 0

QB 0 1 0

http://falstad.com/circuit/e-counter.html 25
2-bit Ripple Up-Counter- T FF(MOD-4) Negative Edge-triggered

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2-bit Ripple Up-Counter- T FF(MOD-4) Negative Edge-triggered

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2-bit Ripple Up-Counter using Negative Edge-triggered Flip-Flop
1 Q1 1 Q2

J1 Q1 J2 Q2
Present State Next State
CLK > FF1 > FF2 CLK
Q2 Q1 Q2 Q1

K1 Q1’ K2 Q2’ 0 0 0 1
0 1 1 0
1 0 1 1
CLK 1 1 0 0

Q1 0 1 0 1 0

Q2 0 1 0

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2-bit Ripple down-Counter- T FF(MOD-4) Negative Edge-triggered
1 QA 1 QB

T1 Q1 T2 Q2
CLK > FF1 > FF2

Q1’ Q2’

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2-bit Ripple Down-Counter using Positive Edge-triggered Flip-Flop
1 Q1 1 Q2

J1 Q1 J2 Q2
Present State Next State
CLK > FF1 > FF2 CLK
Q2 Q1 Q2 Q1
0 0 1 1
K1 Q1’ K2 Q2’
1 1 1 0
1 0 0 1

CLK 0 1 0 0

Q1 0 1 0 1 0 1

Q2 0 1 0

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2-bit Ripple up-Counter using Positive Edge-triggered Flip-Flop
1 Q1 1 Q2

J1 Q1 J2 Q2

CLK > FF1 > FF2

K1 Q1’ K2 Q2’

Refer this video link to understand 3 bit and 4 bit negative edge up-counter.
1. https://www.youtube.com/watch?v=ucCtDhYFCJs
2. https://www.youtube.com/watch?v=s1DSZEaCX_g
3. https://www.youtube.com/watch?v=eEeBh8jfDjg

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 Design 4-bit Ripple up -Counter using JK FF. Write its TT and Draw Timing diagram.
 Refer Anil K.Maini page no 431

 ripple counter type number 74293 IC.→ four-bit binary ripple counter

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 Homewor
1.kDesign 3-bit Ripple up -Counter using T/JK FF. Write its TT and Draw Timing
diagram.(http://www.prajval.in/edudetail/284/2413/%3Cp%3E%3Cstrong%3EDesign-3-bit-ripple-up-counter-using-negative-
edge-triggered-JK-flip-flops-Also-draw-the-waveforms%3C-strong%3E%3C-p%3E-).

1. Design-3-bit-ripple-up-counter-using-negative-edge-triggered-JK-flip-flops-
Also-draw-the-waveforms.
2. Design 3-bit Ripple down -Counter using T/JK FF. Write its TT and Draw Timing
diagram.
3. Design 4-bit Ripple down -Counter using T/JK FF. Write its TT and Draw Timing
diagram.

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 Up/Down counter
2 bit up/down ripple counter

Source: https://player.uacdn.net/lesson-raw/CTESRQVKPN4ZGUOGTTJX/pdf/7718910058.pdf 34
Modulus Ripple Counter
 Mod 4 counter → 2 bit counter → 2 FF are required.
 Mod 8 counter → 3 bit counter → 3 FF are required.
 Mod N counter→ n bit counter → n FF are required.
 Modulus counter= Ripple Counter+ Reset Logic(Combinational logic)

https://www.youtube.com/watch?v=5mfN5KdjcQw
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Design Steps:
1. Determine number of flip-flop.
2. Choose the type of flip-flop.
3. Write the truth table of the counter.
4. Make the Kmap and derive the boolean equation.
5. Design counter.
Mod-6 Asynchronous/Ripple Counter

1. Mod -6 , 6 states → 0,1,2,3,4,5

2.Maximum no is 5 ,so 3 bits are required.
3.No. of FF=3
4.Types of flip-flop T.
5.Make a truth table.
6.Boolean equations.
7.Design final counter circuit.

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Mod-6 Asynchronous/Ripple Counter

After State
Reset(R)
pulses Q3 Q2 Q1
0 0 0 0 1 1
1 0 0 1 1
2 0 1 0 1
3 0 1 1 1
4 1 0 0 1
5 1 0 1 1
6 1 1 0 0

R = Q3’ + Q2 ’
R = 1 for 000 to 101
R = 0 for 110
R = x for 111
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Mod-6 Asynchronous Counter

1 Q1 1 Q2 1
Q3

T1 Q1 T2 Q2 T3 Q3
CLK > FF1 > FF2 > FF3

CLR Q1’ CLR Q2’ CLR Q3’

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Section - 4

http://falstad.com/circuit/e-synccounter.html
Design of Synchronous Counters

 Step 1 - Number of flip-flops: Based on the description of the problem, determine the required
number n of the FFs - the smallest value of n is such that the number of states N ≤ 2n and the
desired counting sequence.
 Step 2 - State diagram: Draw the state diagram showing all the possible states.
 Step 3 - Choice of flip-flops and excitation table: Select the type of flip-flops to be used and
write the excitation table.
 Step 4 - Minimal expressions for excitations: K-maps for the excitations of the flip-flops in
terms of the present states and inputs.
 Step 5 - Logic Diagram: Draw the logic diagram based on the minimal expressions.

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Design of Synchronous 3-bit Up Counters
 Step 1 - Number of flip-flops:
A 3-bit up-counter requires 3 flip-flops. The counting sequence is 000, 001, 010, 011, 100, 101,
110, 111, 000 …
 Step 2 - Draw the state diagram:
000
111 001

110 010

101 011
100

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43
Design of Synchronous 3-bit Up Counters
 Step 3 - Select the type of flip-flops and draw the excitation table:
JK flip-flops are selected and the excitation table of a 3-bit up-counter using J-K flip-flops is
drawn as shown below.
PS NS Required excitations J-K FF Excitation Table
Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1 Required
PS NS
0 0 0 0 0 1 0 x 0 x 1 x inputs
0 0 1 0 1 0 0 x 1 x x 1 Qn Qn+1 J K
0 1 0 0 1 1 0 x x 0 1 x 0 0 0 x
0 1 1 1 0 0 1 x x 1 x 1 0 1 1 x
1 0 0 1 0 1 x 0 0 x 1 x 1 0 x 1
1 0 1 1 1 0 x 0 1 x x 1 1 1 x 0
1 1 0 1 1 1 x 0 x 0 1 x
1 1 1 0 0 0 x 1 x 1 x 1

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Design of Synchronous 3-bit Up Counters
 Step 4 - Obtain the minimal expressions:
From excitation table, J1 = K1 = 1.
K – Maps for excitations J3, K3, J2 and K2 and their minimized form are as follows:

Q3Q2 Q3Q2
00 01 11 10 00 01 11 10
Q1 Q1
0 x x 0 x x

1 1 x x 1 x x 1

J3 = Q2Q1 K3 = Q2Q1

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Design of Synchronous 3-bit Up Counters

Q3Q2 Q3Q2
Q1 00 01 11 10 Q1 00 01 11 10

0 x x 0 x x

1 1 x x 1 1 x 1 1 x

J 2 = Q1 K2 = Q1

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Design of Synchronous 3-bit Up Counters
 Step 5 - Draw the logic diagram:

J1 Q1 J2 Q2 J3 Q3

> FF1 > FF2 > FF3

K1 Q1’ K2 Q2’ K3 Q3’

CLK

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Ring Counter- Shift Register Counters

• Ring counter is an application of Shift resister.

•Types of Ring Counter –

1. Straight Ring Counter 2. Twisted Ring Counter

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4-bit Ring counter with 4 D flip-flop.

• Straight Ring Counter: One hot Counter : Last flip-flop is connected to the
input of the first flip-flop.

•Clock pulse (CLK) is applied to all the flip-flop simultaneously. Therefore, it is

a Synchronous Counter.

• No of state = No of bits.

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4-bit Ring counter with 4 D flip-flop.

To write about ring counter refer below link

https://www.geeksforgeeks.org/ring-counter-in-digital-logic/?ref=lbp
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 6-bit Ring counter with 6 D flip-flop.

https://www.researchgate.net/figure/State-diagram-and-implementation-of-a-six-bit-ring-counter-with-D-Flip-flops_fig2_322106955
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4 bit Twisted Ring Counter

• Twisted Ring Counter : switch-tail ring counter, walking ring

counter or Johnson counter.:
• connects the complement of the output of the last FF to the
input of the first FF.
• No state = 2* No of bits.

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 4 bit Twisted Ring Counter

To write about advantage ,dis- advantage ,application and working of this counter refer
below link
https://www.geeksforgeeks.org/n-bit-johnson-counter-in-digital-logic/?ref=lbp
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Decade and BCD Counters
 that goes through 10 unique output combinations and then resets as the clock proceeds
further.
 MOD-10 counter.
 4 flip-flops.
 From 16 states any of the six states by using some kind of feedback is skipped.
 A decade counter does not necessarily count from 0000 to 1001.
 It could even count as 0000, 0001, 0010, 0101, 0110, 1001, 1010, 1100, 1101, 1111, 0000.
 BCD counter is a special case of a decade counter.
 Counts from 0000 to 1001 and then resets.

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Designing Counters with Arbitrary Sequences

ALL BELOW LINK WILL BE USEFUL TO UNDERSTAND THE TOPICSO GO THROUGH ALL VIDEOS.

 https://www.youtube.com/watch?v=Zce6NlHuvfs

 https://www.youtube.com/watch?v=vx4PNd_Hl8U

 https://www.youtube.com/watch?v=ruxiO77HL9k

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