Week: 2

1. Consider following statements about Channel Length Modulation (CLM) and

pick correct statements.
(i) CLM is effect of improper doping concentrations.
(ii) Early voltage is Process dependent parameter.
(iii) CLM is because of deposition of Immobile ions at source.
(iv) CLM is a result of potential variation between Gate and Source.
(v) Ids is directly proportional of Vds and inversely proportional to Early
voltage.
(vi) CLM makes Ids vs Vds characteristics flat after saturation.
(vii) CLM introduces negative slope in Ids vs Vds characteristics after
saturation.
(viii) CLM introduces positive slope in Ids vs Vds characteristics after
saturation.
(ix) CLM increases effective channel length.
(x) The extension of the slope of Ids during saturation intersects the Vds axis,
forming the early voltage.
(xi) CLM decreases effective channel length.
(xii) Ids is independent of Vds and inversely proportional to Early voltage.
(xiii) Ids is inversely proportional of Vds and directly proportional to Early
voltage.
(xiv) CLM is because of deposition of Immobile ions at Drain.

a) iii, xii, v, ix, xiv

b) ii, vi, x, xiii, iv
c) xi, viii, i, xii, iii
d) ii, v, viii, x, xiv
e) xiv, vi, xi, iii, ix
f) i, v, xii, viii
g) vii, x, iii, xi, iv, ix
h) xiii, ii, vi, v, xi

2) In the provided inverter characteristics figure, which parameters should be plotted on

the X and Y axes to represent the observed characteristics, and identify the operating
regions of PMOS and NMOS transistors at Point-4?
 a) Y: Vout, X: Vin, At Point-4: PMOS: Saturation, NMOS: Linear
b) Y: Vin, X: Vout, At Point-4: PMOS: Saturation, NMOS:
Saturation
c) Y: Ids, X: Vin, At Point-4: PMOS: Linear, NMOS:
Saturation
d) Y: Vin, X: Ids, At Point-4: PMOS: Cut-off, NMOS: Linear
e) Y: Vout, X: Ids, At Point-4: PMOS: Saturation, NMOS: Linear
f) Y: Ids, X: Vin, At Point-4: PMOS: Saturation, NMOS: Linear
g) Y: Ids, X: Vout, At Point-4: PMOS: Linear, NMOS:
Saturation
h) Y: Ids, X: Vout, At Point-4: PMOS: Saturation, NMOS: Linear

3) In the provided inverter characteristics figure, which parameters should be plotted on

the X and Y axes to represent the observed characteristics, and identify the operating
regions of PMOS and NMOS transistors at Point-1?

a) Y: Vout, X: Vin, At Point-1: Saturation, NMOS: Linear

b) Y: Vin, X: Vout, At Point-1: PMOS: Saturation, NMOS:
Saturation
c) Y: Ids, X: Vin, At Point-1: PMOS: Cut-off, NMOS: Linear
d) Y: Vin, X: Ids, At Point-1: PMOS: Cut-off, NMOS: Linear
e) Y: Vout, X: Ids, At Point-1: PMOS: Saturation, NMOS: Linear
f) Y: Ids, X: Vin, At Point-1: PMOS: Linear, NMOS: Cut-off
 g) Y: Ids, X: Vout, At Point-1: PMOS: Linear, NMOS:
Saturation
h) Y: Ids, X: Vout, At Point-1: PMOS: Saturation, NMOS: Linear

4) In the provided inverter characteristics figure, which parameters should be plotted on

the X and Y axes to represent the observed characteristics, and identify the operating
regions of PMOS and NMOS transistors at Point-3?

a) Y: Vout, X: Vin, At Point-3: PMOS: Saturation, NMOS:

Saturation
b) Y: Vin, X: Vout, At Point-3: PMOS: Cut-off, NMOS: Cut-off
c) Y: Vout, X: Vin, At Point-3: PMOS: Linear, NMOS: Cut-off
d) Y: Vin, X: Ids, At Point-3: PMOS: Cut-off, NMOS: Linear
e) Y: Vout, X: Ids, At Point-3: PMOS: Saturation, NMOS: Linear
f) Y: Ids, X: Vin, At Point-3: PMOS: Cut-off, NMOS: Linear
g) Y: Vin, X: Vout, At Point-3: PMOS: Saturation, NMOS:
Saturation
h) Y: Vin, X: Vout, At Point-3: PMOS: Saturation, NMOS: Linear

5. For an Inverter of 2:1 size, evaluate the current when an input voltage of 2 V is
applied for a 5V rail voltage. Consider Vt for NMOS, and PMOS as 0.3 V, and -0.3 V
respectively, and Widths of 100 nm, and 200 nm for NMOS and PMOS transistors, with
channel length of 50 nm, and mobility of 80 cm2/v-sec, and 40 cm2/v-sec for NMOS and
PMOS transistors.

a) 128 µA
b) 256 µA
c) 512 µA
d) 760 mA
e) 128 mA
f) 760 µA
g) 1.28 mA
h) 7.60 mA

6. For a skewing ratio of 0.30 for a 65 nm technology node with a rail voltage of 1V as
per the long-channel model, which is the more appropriate statement?
 a) Threshold-voltage of inverter is 0.5 V.
b) Threshold-voltage of inverter is 1 V.
c) Threshold-voltage of inverter is 0 V.
d) Threshold-voltage of inverter falls in between 0.5 and 0 V
e) Threshold-voltage of inverter falls in between 0.5 and 1 V
f) Threshold-voltage of inverter is above 1 V
g) Threshold-voltage of inverter is below 0 V
h) Threshold-voltage of inverter is 0.3 V
7. Employing the short-channel current model, calculate the threshold voltage of an
inverter functioning at a nominal voltage of 1 volt. The system exhibits a PMOS width
to NMOS width ratio of 2:5, a NMOS velocity saturation ratio to PMOS velocity
saturation ratio of 2:4, and possesses threshold voltages of 0.3 volts for both the PMOS
and NMOS transistors.
a) 0.585
b) 0.325
c) 0.174
d) 0.744
e) 0.779
f) 0.4
g) 0.625
h) 0.8

8) Find the value of X considering threshold value of PMOS and NMOS as 0.5 Volts
(Bubbled transistor symbolizes PMOS, whereas a non-bubbled one corresponds to
NMOS.)

a) 0 Volts
b) 0.5 Volts
c) 1.5 Volts
d) 2 Volt
e) 4 Volt
f) 3.5 Volt
g) 5 Volt
h) 2.5 Volt
Solution:
9) In the context of a “Transmission Gate” experiencing a rising step input from 0 to
Vdd, with Vth-p and Vth-n both less than Vdd/2, during the moment when the Output
node reaches Vdd/2, Identify the Operating Regions of the PMOS and NMOS
transistors.

a) NMOS: Saturation, PMOS: Linear

b) NMOS: Linear, PMOS: Saturation
c) NMOS: Cut-off, PMOS: Linear
d) NMOS: Linear, PMOS: Cut-off
e) NMOS: Linear, PMOS: Linear
f) NMOS: Saturation, PMOS: Saturation
g) NMOS: Cut-off, PMOS: Saturation
h) NMOS: Saturation, PMOS: Cut-off
10. Identify correct sentences in the case of Transmission gate (TG).
(i) While TG is experiencing falling step input, NMOS of TG will remain
turned on when output node voltage lies between Vdd to Vdd -Vtn
(ii) While TG is experiencing falling step input, PMOS of TG will remain
turned on when output node voltage lies between Vdd-Vtp to 0
(iii) While TG is experiencing rising step input, NMOS of TG will remain
turned on when output node voltage lies between 0 to Vdd - Vtn
(iv) While TG is experiencing falling step input, PMOS of TG will remain
turned on when output node voltage lies between Vdd to Vtp
(v) While TG is experiencing rising step input, NMOS of TG will remain
turned on when output node voltage lies between Vtn to Vdd
(vi) While TG is experiencing falling step input, NMOS of TG will remain
turned on when output node voltage lies between Vdd to Vtn
(vii) While TG is experiencing rising step input, PMOS of TG will remain
turned on between 0 to Vdd-Vtp
(viii) While TG is experiencing falling step input, NMOS of TG will remain
turned on when output node voltage lies between Vdd to 0
(ix) While TG is experiencing rising step input, NMOS of TG will remain
turned on when output node voltage lies between 0 to Vdd
(x) While TG is experiencing rising step input, PMOS of TG will remain
turned on when output node voltage lies between Vtp to Vdd
(xi) While TG is experiencing falling step input, PMOS of TG will remain
turned on when output node voltage lies between Vdd to 0
(xii) While TG is experiencing rising step input, PMOS of TG will remain
turned on when output node voltage lies between 0 to Vdd

a) iii, iv, viii, x

b) ii, vi, ix, xii
c) iii, iv, viii, xii
d) i, iv, vii, xii
e) iii, v, viii, xi
f) i, iii, vi, x
g) iv, vii, x, xi
h) ii, iv, ix, xii