Digital Electronics

19CSE203
III Semester
B. Tech. CSE
Amrita School of Engineering,
Chennai
Combinational Circuit and Sequential Circuit

Sequential circuits include storage elements that store the values of the previous state of the system.
The contents of the storage elements are said to represent the state of the circuit.
A Simple Memory Element
If we assume that A = 0, then B = 1. The
circuit will maintain these values
indefinitely. If we assume that A = 1, then B
= 0, and the circuit will remain in this
second state indefinitely. Thus, the circuit
has two possible states. This circuit is not
useful, because it lacks some practical
means for changing its state.
A Memory Element with NOR gates

Set Reset Q Remarks

(S) (R)
0 0 Q Previous State
0 1 0 Reset State
1 0 1 Set State
1 1 0 But this is invalid
state which will be
discussed soon
A Latch built with NOR gates
Required: Qa and Qb are complement of each other
An SR Latch built with NAND gates
The next state Q can be written as either Q(n+1) or Q(t+1) or Q+ different authors follow different notations
The next state Q’ can be written as either Q’(n+1) or Q’(t+1) or Q’+
S R S’ R’ Q(t+1) Q’ (t+1) Remarks

0 0 1 1 Q(t) Q’(t) Same

Previous
value
0 1 1 0 0 1 Reset
State
1 0 0 1 1 0 Set State
1 1 0 0 1 1 Not
Allowed

S Q
Symbol of SR Latch
R Q’
 Clock
• A clock is that which continuously
alternates between 0 and 1. i.e. it is
continuous train of pulses
• The time it takes the clock to
change from 1 to 0 and back to 1
(or vice versa) is called the clock
period or clock cycle time.
• i.e. Cycle time of a clock is the sum
of its high duration and its low
duration. The length of the time the
clock is high before changing states
is it high duration and the length of
the time the clock is low before
changing states is it low duration
• The clock frequency is the inverse
of the clock period. The unit of
measurement for frequency is the
Hertz
• Clocks are often used to
synchronize circuits
Gated SR Latch with NAND gates
Clk S R Q(t+1) Q’(t+1) Remarks
0 x x Q(t) Q’(t) No change. Same as that of
the previous state
1 0 0 Q(t) Q’(t) No change. Same as that of
the previous state

1 0 1 0 1 Reset state
1 1 0 1 0 Set state
1 1 1 1 1 Invalid
Gated D (Data) Latch Clk D Q Q’ Remarks
0 x Q Q’ No change. Same as that
of the previous state
1 0 0 1 Q will be same as that
of D input

1 1 1 0 Q will be same as that

of D input
Master Slave D Flip Flop (Negative Edge Triggered D Flip Flop)
Truth Table in a descriptive manner

Clk D Qm Qs = Q Remarks
1 -ve 1 1 Previous At negative edge,
edge on output = Q whatever is value of D
0 Clk x 1 1 data input the same
value will appear on Q

1 -ve 0 0 Previous At negative edge,

edge on output = Q whatever is value of D
0 Clk x 0 0 data input the same
value will appear on Q
Clk
x Qm Q At any other value
other than negative
x edge trigger on the
clock, the same
previous value of Q
will continue on Q
Set Up Time and Hold Time Set Up Time (tsu): The minimum time
that the D signal must be stable prior to
the negative edge (or positive edge
based on what type of flipflop) of the
Clk signal is called the setup time, tsu,
of the flip flop.

Hold Time (th): The minimum time that

the D signal must remain stable after
the negative edge (or positive edge
based on what type of flipflop) of the
Clk signal is called the hold time, th, of
the flip flip.

Typical values for tsu = 3 ns and th = 2

ns.

If Set up time and Hold time are not

adhered then the circuit will enter in
Metastable state.
 Timing Diagram Showing Difference
between D Latch and D Flip Flop Working
Analyze this Waveform: Exercise
Graphic symbols
Positive Edge Triggered D Flip Flop Negative Edge Triggered D Flip Flop

Flip flop is a edge

triggered one bit
storage device.

Positive Level Triggered D Latch Negative Level Triggered D Latch

Latch is a level
triggered one bit
storage device.
Master-Slave D flip-flop with Clear and Preset
Preset Clear D Input Q Output Remarks
0 0 Don’t Care Don’t Care Invalid
0 1 Don’t Care 1 Preset Condition
1 0 Don’t Care 0 Clear or Reset Condition

1 1 Whatever Valid value Q=D Regular or Normal Functionality

on D Input Valid Output on Q of D Flip flop begins

We have assumed Low

Level Active Preset and
Clear here.
* Practically, these may be
Low level or High level
active
Asynchronous Clear • If the Clear Signal is considered to be
Asynchronous signal, then that means the
Clear signal will not wait for clock
(positive edge as per the diagram here),
and Q will made zero (0) immediately
without waiting for the clock’s required
edge. That is Clear signal is not
synchronized with Clock signal.
• If the Clear Signal is considered to be
Synchronous signal, then that means the
Clear signal will wait clock till immediate
positive edge (positive edge as per the
diagram here) occurs on the clock and
then Q will be made zero (0). That is
Clear signal is synchronized with Clock
signal.
Master Slave SR Flip Flop
C = Clock = Clk

C = Clk = Clock S R Q+ Q’+ Remarks

Negative edge on C 0 0 Q Q’ Same as that of the previous value
Negative edge on C 0 1 0 1 Reset state

Negative edge on C 1 0 1 0 Set state

Negative edge on C 1 1 1 1 Invalid or Undefined

Any other value on C other x x Q Q’ Same as that of the previous value

than negative edge on the C
J K Flip-flop (Master Slave)

Clock = C = Clk
• When clk = 1 Mater Latch is active and when clk = 0 Slave latch is active. J K Flip-flop
(Master Slave)
• a) When J = 0 and K = 0, Master Latch input S = R = 0 therefore QM and QM’ will be
same as that of the previous value. Therefore, based on previous value on QM = 0/1 and
QM’ = 1/0, the output QS = 0/1 and QS’ = 1/0.
• b) When J = 0 and K = 1, Master Latch input S = 0 and R can not be defined hence we
assume
• Case i) If we assume at this time Q = 0 and Q’ = 1, then R = 0 hence QM and
QM’ will have the same previous value QM = 0 and QM’ = 1. This causes the
QS and QS’ to be 0 and 1 respectively (same as previous).
• Case ii) If we assume at this time Q = 1 and Q’ = 0, then R = 1 hence QM and
QM’ will have the value as QM = 0 and QM’ = 1. This causes the QS and QS’ to
be 0 and 1 respectively.
• Hence, we conclude that when J = 0 and K = 1, then Q = 0 and Q’ = 1
• c) When J = 1 and K = 0, Master Latch input R = 0 and S can not be defined hence we
assume
• Case i) If we assume at this time Q = 0 and Q’ = 1, then S = 1 hence QM = 1
and QM’ = 0. This causes the QS and QS’ to be 1 and 0 respectively.
• Case ii) If we assume at this time Q = 1 and Q’ = 0, then S = 0 hence QM and
QM’ will have the same previous value QM = 1 and QM’ = 0. This causes the
QS and QS’ to be 1 and 0 respectively (same as previous).
• Hence, we conclude that when J = 1 and K = 0, then Q = 1 and Q’ = 0
d) When J = 1 and K = 1, Master Latch input S and R inputs can not be defined
hence we assume
• Case i) If we assume at this time Q = 0 and Q’ = 1, then S = 1 and R = 0, hence
QM = 1 and QM’ = 0. This causes the QS and QS’ to be 1 and 0 respectively.
• Case ii) If we assume at this time Q = 1 and Q’ = 0, then S = 0 and R = 1, hence
QM = 0 and QM’ = 1. This causes the QS and QS’ to be 0 and 1 respectively.
• Hence, we conclude that when J = 1 and K = 1, then Q and Q’ toggles with
respect to the previous value and hence it is a valid output and removes the
drawback of the Master Slave SR flipflop where for S=R= 1, the output is
invalid as discussed before.
T (Toggle) Flip Flop

C = Clk = Clock T Q+ Q’+ Remarks

Negative edge on C 0 Q Q’ Same as that of the previous value
Negative edge on C 1 Q’ Q Toggles i. e. Invert of the previous value

Any other value on C other x Q Q’ Same as that of the previous value

than negative edge on the C
• Summary of Truth Table of SR, JK, D and T flip flops
• Characteristic Table
• Characteristic Equation • Characteristic
Table = State
• Excitation Table
Table
Function
Table = Truth
Table
D Flip-flop

• As an exercise, derive the state table, K-map, and excitation table for an SR flip-flop from the
characteristic table.
 SR = SR = SR = SR =
00 01 11 10
Q=0 0 0 x 1
Q=1 1 0 x 1

Characteristic Equation for SR ff = Qnext = Q+ = S + R’Q

JK = JK = JK = JK =
00 01 11 10
Q=0 0 0 1 1
Q=1 1 0 0 1

Characteristic Equation for JK ff = Qnext = Q+ = JQ’ + K’Q

D=0 D=1
Characteristic Equation for D ff = Qnext = Q+ = D
Q=0 0 1
Q=1 0 1

T=0 T=1 Characteristic Equation for T ff = Qnext = Q+ = T’Q + TQ’

Q=0 0 1 =T⊕Q
Q=1 1 0
• Characteristic
Table = State
Table
Function
Table = Truth
Table