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DTE Front Pages

The document is a project report submitted by four students on designing a full adder using logic gates. It includes an introduction, certificate, and details of the students and guide.

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26 views2 pages

DTE Front Pages

The document is a project report submitted by four students on designing a full adder using logic gates. It includes an introduction, certificate, and details of the students and guide.

Uploaded by

tapstaps902
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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A

MICRO PROJECT REPORT ON

FULL ADDER USING GATES


SUBMITTED

BY

Ms. Tasmiya Firoj Nadaf 25034


Ms. Vedika Mahesh Nagarkar 25035
Ms. Varsha Sanjay Nimbalkar 25036
Ms. Samedha Adinath Patil 25037

UNDER THE GUIDANCE OF

Ms. S. S. Malame
Lecturer, Computer Engineering Department

DEPARTMENT OF COMPUTER ENGINEERING

Sharad Institute of Technology Polytechnic, Yadrav

Tal – Shirol, Dist. - Kolhapur

Academic Year 2023-2024


DEPARTMENT OF COMPUTER ENGINEERING

Sharad Institute of Technology Polytechnic, Yadrav

CERTIFICATE
This is to certify that the project report entitled
“FULL ADDER USING GATES”
Submitted by

Ms. Tasmiya Firoj Nadaf 25034


Ms. Vedika Mahesh Nagarkar 25035
Ms. Varsha Sanjay Nimbalkar 25036
Ms. Samedha Adinath Patil 25037
This is a bonafide work carried out by him under the supervision of Ms. S. S. Malame and it is
submitted towards the partial fulfilment of the requirement of MSBTE.

Ms. S. S. Malame Mr. R. M. Patil


Project Guide HOD
Department of Computer Department of Computer
Engineering, SITP, Yadrav Engineering, SITP, Yadrav

Mr. B. S. Tashildar
Seal / Stamp of the College Principal
SITP, Yadrav
Place: SITP, Yadrav
Date:

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