INTEGRATED CIRCUIT DESIGN

Lecture 6:

Wires

6: Wires CMOS VLSI Design 4th Ed.

 Syllabus

Digital Circuits Analog Circuits

Introduction and overview Simple CMOS Circuits:
Circuits, fabrication, and layout Switches
CMOS transistor theory Diodes/active resistors
DC and transient response Current mirrors
Logical effort Current sources/current sinks
Interconnect engineering (wire) Current/voltage references
Combinational circuit design Band gap references
Sequential circuit design Simple CMOS amplifiers

6: Wires CMOS VLSI Design 4th Ed. 2

 Outline
 Introduction
 Interconnect Modeling
– Wire Resistance
– Wire Capacitance
 Wire RC Delay
 Crosstalk
 Wire Engineering
 Repeaters

6: Wires CMOS VLSI Design 4th Ed. 3

 Introduction
 Chips are mostly made of wires called interconnect
– In stick diagram, wires set size
– Many layers of wires
 Wires are important with
– Speed
– Power
– Noise
 Alternating layers run orthogonally (trực giao)

6: Wires CMOS VLSI Design 4th Ed. 4

 Wire Geometry
 Pitch = w + s Pitch: bước/khoảng cách

 Aspect ratio: AR = t/w

– Old processes had AR << 1
– Modern processes have AR  2 w s
• Pack in many skinny wires
l
l: length
w: width
t: thickness
t
s: space
h
h: height

6: Wires CMOS VLSI Design 4th Ed. 5

 Layer Stack
 AMI 0.6 mm process has 3 metal layers
– M1 for within-cell routing
– M2 for vertical routing between cells
– M3 for horizontal routing between cells
 Modern processes use 6-10+ metal layers
– M1: thin, narrow (< 3l)
• High density cells
– Mid layers
• Thicker and wider, (density vs. speed)
– Top layers: thickest
• For VDD, GND, clk

6: Wires CMOS VLSI Design 4th Ed. 6

 Example

Intel 90 nm Stack Intel 45 nm Stack

[Thompson02] [Moon08]

6: Wires CMOS VLSI Design 4th Ed. 7

 Example

Intel 45nm metal stack

6: Wires CMOS VLSI Design 4th Ed. 8

Lumped Element Models
 Wires are a distributed system with resistances and
capacitances per unit length.
– Approximate with lumped element models
N segments
R
R/N R/N R/N R/N
C/N C/N C/N C/N C

R R R/2 R/2

C C/2 C/2 C

L-model p-model T-model

 3-segment p-model is accurate to 3% in simulation

 L-model needs a large number of segments for same accuracy!
 T-model is slower to solve by hand or by simulator
 Use single segment p-model for Elmore delay

6: Wires CMOS VLSI Design 4th Ed. 9

 Wire Resistance
 r = resistivity (W*m)
r ll
R R
t w w
 R = sheet resistance (W/)
–  is a dimensionless unit(!)
 Count number of squares
– R = R * (# of squares)

6: Wires CMOS VLSI Design 4th Ed. 10

 Choice of Metals
 Until 180 nm generation, most wires were aluminum
 Contemporary processes normally use copper
– Cu atoms diffuse into silicon and damage FETs
– Must be surrounded by a diffusion barrier
Metal Bulk resistivity (mW • cm)
Silver (Ag) 1.6
Copper (Cu) 1.7
Gold (Au) 2.2
Aluminum (Al) 2.8
Tungsten (W) 5.3
Titanium (Ti) 43.0

6: Wires CMOS VLSI Design 4th Ed. 11

 Contacts Resistance
 Contacts and vias also have 2-20 W depended on
its materials and sizes
 Use many contacts for lower R

6: Wires CMOS VLSI Design 4th Ed. 12

 Copper Issues
 Copper wires diffusion barrier has high resistance
 Copper is also prone to dishing during polishing
 Effective resistance is higher
r l
R
 t  tdish  tbarrier   w  2tbarrier 

Prone: dát mỏng

6: Wires CMOS VLSI Design 4th Ed. 13

 Example
 Compute the sheet resistance of a 0.22 mm thick Cu
wire in a 65 nm process. The resistivity of thin film
Cu is 2.2 x 10-8 W•m. Ignore dishing.
2.2 108 Ω m
R  6
 0.10 W /
0.22 10 m

 Find the total resistance if the wire is 0.125 mm wide

and 1 mm long. Ignore the barrier layer.
1000 m m
R   0.10 Ω/   800 W
0.125 m m

6: Wires CMOS VLSI Design 4th Ed. 14

 Example
 Compute the sheet resistance of a 0.22 mm thick Cu
wire in a 65 nm process. The resistivity of thin film
Cu is 2.2 x 10-8 W•m. Ignore dishing.
2.2 108 Ω m
R  6
 0.10 W /
0.22 10 m

 Find the total resistance if the wire is 0.125 mm wide

and 1 mm long. Ignore the barrier layer.
1000 m m
R   0.10 Ω/   800 W
0.125 m m

6: Wires CMOS VLSI Design 4th Ed. 15

 Wire Capacitance
 Wire has capacitance per unit length
– To neighbors
– To layers above and below
 Ctotal = Ctop + Cbot + 2Cadj
s w

layer n+1

h2 Ctop

t layer n
Cadj
h1 Cbot
layer n-1

6: Wires CMOS VLSI Design 4th Ed. 16

 Capacitance Trends
A = w.l or t.l
 Parallel plate equation: C = eoxA/d d = h or s
– Wires are not parallel plates, but obey trends
– Increasing area (w, t) increases capacitance
– Increasing distance (s, h) decreases capacitance
 Dielectric constant
– eox = ke0
• e0 = 8.85 x 10-14 F/cm
• k = 3.9 for SiO2
 Processes are starting to use low-k dielectrics
– k  3 (or less) as dielectrics use air pockets
6: Wires CMOS VLSI Design 4th Ed. 17
 Capacitance Formula
 Capacitance of a line without neighbors (ignore s)
can be approximated as

w  w
0.25
t 
0.5

Ctot  e ox l   0.77  1.06    1.06   

 h h  h  

 This empirical formula is accurate to 6% for AR < 3.3

– AR: aspect ratios (w/h)

6: Wires CMOS VLSI Design 4th Ed. 18

 Wire RC Delay – Example1

With Rwire = 800W

2x3C

10K/10

6: Wires CMOS VLSI Design 4th Ed. 20

 Wire RC Delay – Example1

With Rwire = 800W

tpd = (1000 W)(100 fF) + (1000 + 800 W)(100 + 0.6 fF) = 281 ps

2x3C

10K/10

6: Wires CMOS VLSI Design 4th Ed. 21

 Wire RC Delay – Example2
 Estimate the delay of a 10x unit-sized inverter
driving a 2x inverter at the end of the 1 mm wire.
Assume wire capacitance is 0.2 fF/mm and that a
unit-sized nMOS transistor has R = 10 KW and
Cgate = Cdiffusion = 0.1 fF. With Rwire = 800W
tpd = (1000 W)(100 fF) + (1000 + 800 W)(100 + 0.6 fF) = 281 ps

10x3C 2x3C

10K/10

6: Wires CMOS VLSI Design 4th Ed. 22

 Wire RC Delay – Example2
 Estimate the delay of a 10x unit-sized inverter
driving a 2x inverter at the end of the 1 mm wire.
Assume wire capacitance is 0.2 fF/mm and that a
unit-sized nMOS transistor has R = 10 KW and
Cgate = Cdiffusion = 0.1 fF. With Rwire = 800W
tpd = (1000 W)(100fF + 3fF) + (1000 + 800 W)(100fF+ 0.6fF) = 284 ps

10x3C 2x3C

10K/10

6: Wires CMOS VLSI Design 4th Ed. 23

 Crosstalk
 A capacitor does not like to change its voltage
instantaneously.
 A wire has high capacitance to its neighbor.
– When the neighbor switches from 1-> 0 or 0->1,
the wire tends to switch too.
– Called capacitive coupling or crosstalk.
 Crosstalk effect is an effect in which a switching wire
will be cause
– a noise on nonswitching wires
– an increase or decrease delay on other
switching wires
6: Wires CMOS VLSI Design 4th Ed. 26
 Crosstalk Delay
 Assume layers above and below on average are quiet
– Second terminal of capacitor can be ignored
– Model as Cgnd = Ctop + Cbot
 Effective Cadj depends on behavior of neighbors
– Miller effect A
C
B
Cgnd adj Cgnd

B DV Ceff(A) MCF
Constant VDD Cgnd + Cadj 1
Switching with A 0 Cgnd 0
Switching opposite A 2VDD Cgnd + 2 Cadj 2

6: Wires CMOS VLSI Design 4th Ed. 27

 Crosstalk Delay
 Assume layers above and below on average are quiet
– Second terminal of capacitor can be ignored
– Model as Cgnd = Ctop + Cbot
 Effective Cadj depends on behavior of neighbors
– Miller effect A
C
B
C C gnd
adj
gnd
MCF (Miller Coupling Factor)
B DV Ceff(A) MCF
Constant VDD Cgnd + Cadj 1
Switching with A 0 Cgnd 0
Switching opposite A 2VDD Cgnd + 2 Cadj 2

6: Wires CMOS VLSI Design 4th Ed. 28

 Crosstalk - example

Example 6.8 (page 223)

6: Wires CMOS VLSI Design 4th Ed.

 Crosstalk Noise
 Crosstalk causes noise on nonswitching wires
 If victim is floating:
– model as capacitive voltage divider
Cadj
DVvictim  DVaggressor
C gnd v  Cadj
Aggressor

DVaggressor
Cadj
Victim
Cgnd-v DVvictim

6: Wires CMOS VLSI Design 4th Ed. 30

 Driven Victims
 Usually victim is driven by a gate that fights noise
– Noise depends on relative resistances
– Victim driver is in linear region, agg. in saturation
– If sizes are same, Raggressor = 2-4 x Rvictim
Cadj 1
DVvictim  DVaggressor Raggressor
Cgnd v  Cadj 1 k
Aggressor
Cgnd-a
DVaggressor
Cadj
Rvictim

 aggressor Raggressor  Cgnd a  Cadj 

Victim
Cgnd-v DVvictim

k 
 victim Rvictim  Cgnd v  Cadj 

6: Wires CMOS VLSI Design 4th Ed. 31

 Coupling Waveforms
 Simulated coupling for Cadj = Cvictim

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 Noise Implications
 So what if we have noise?
 If the noise is less than the noise margin, nothing
happens
 Static CMOS logic will eventually settle to correct
output even if disturbed by large noise spikes
– But glitches cause extra delay
– Also cause extra power from false transitions
 Dynamic logic never recovers from glitches
 Memories and other sensitive circuits also can
produce the wrong answer

6: Wires CMOS VLSI Design 4th Ed. 33

 Wire Engineering
 Goal: achieve delay, area, power goals with
acceptable noise
 Degrees of freedom:
2.0 0.8

– Width 1.8 0.7

Coupling:2Cadj / (2C adj+Cgnd)

1.6
0.6
WireSpacing
– Spacing
1.4
(nm)
Delay (ns):RC/2

0.5
1.2
320
1.0 0.4 480

– Layer
640
0.8 0.3
0.6
0.2
0.4
– Shielding 0.2
0
0.1
0
0 500 1000 1500 2000 0 500 1000 1500 2000
Pitch (nm) Pitch (nm)

vdd a0 a1 gnd a2 a3 vdd vdd a0 gnd a1 vdd a2 gnd a0 b0 a1 b1 a2 b2

6: Wires CMOS VLSI Design 4th Ed. 34

 Repeaters
 R and C are proportional to l (length)
 RC delay is proportional to l2
– Unacceptably great for long wires
 Break long wires into N shorter segments
– Drive each one with an inverter or buffer
Wire Length: l

Driver Receiver

N Segments
Segment
l/N l/N l/N

Driver Repeater Repeater Repeater Receiver

6: Wires CMOS VLSI Design 4th Ed. 35

 Repeater Design
 How many repeaters should we use?
 How large should each one be?
 Equivalent Circuit
– Wire length l/N
• Wire Capacitance Cw*l/N, Resistance Rw*l/N
– Inverter width W (nMOS = W, pMOS = 2W)
• Gate Capacitance C’*W, Resistance R/W
RwlN

R/W
Cwl/2N Cwl/2N C'W

6: Wires CMOS VLSI Design 4th Ed. 36

 Repeater Results
 Write equation for Elmore Delay
– Differentiate with respect to W and N
– Set equal to 0, solve

l 2 RC 

N RwCw

 
t pd ~40 ps/mm
 2 2 RC RwCw
l in 65 nm process
RCw
W
RwC 
6: Wires CMOS VLSI Design 4th Ed. 37
 Repeater Energy
 Energy / length ≈ 1.87CwVDD2
– 87% premium over unrepeated wires
– The extra power is consumed in the large
repeaters
 If the repeaters are downsized for minimum EDP:
– Energy premium is only 30%
– Delay increases by 14% from min delay

6: Wires CMOS VLSI Design 4th Ed. 38