TPS25730

SLVSGP9 – OCTOBER 2023

TPS25730 USB Type-C® and USB PD Controller with Integrated Power Switches
Optimized for Power Applications

1 Features 3 Description
• PD3.1 compatible for sink only applications The TPS25730 is a highly integrated stand-alone
– PD3.1 is the latest Power Delivery specification USB Type-C and Power Delivery (PD) controller
from USB-IF optimized for sink only applications supporting USB-C
– PD2 and PD3 PD Power. The TPS25730 integrates a fully managed
• Fully configurable single port PD controller power path with robust protection for a complete USB-
– Optimized for sink only USB Type-C and USB C PD solution. The TPS25730 also has the ability
PD applications to control an external power path through the use of
– Complete barrel jack replacement solution for internal gate drivers. The TPS25730 is best suited for
switching to USB Type-C sink only applications that may have previously been
– Fully configurable with pin strapping powered by a barrel jack. Using resistor pin strapping,
– Industrial temperature range supported a user can implement a fully featured USB Type-C
– For a more extensive selection guide, please PD port with the TPS25730 on their platform. There
refer to USB Type-C & PD Portfolio and is no need for an external EEPROM, an external
Selecting a USB Type-C & PD Controller microcontroller, or any type of firmware development.
• Fully managed integrated power path The TPS25730 is intended to make setting up a sink
– Integrated overvoltage protection and reverse only USB Type-C application simple yet robust. A user
current protection has all of the benefits of a barrel jack port, while now
• USB Type-C PD Controller taking advantage of the benefits that USB Type-C and
– 6 GPIO set functions USB Type-C PD can bring to their system.
– Cable attach and orientation detection
Package Information
– Integrated dead battery Rd
BODY SIZE (NOM)
– Physical layer and policy engine PART NUMBER PACKAGE(1) (2)
– Integrated VBUS 3.3-V LDO for dead battery
TPS25730D QFN (REF) 4.00 mm x 6.00 mm
– Power supply from 3.3-V or VBUS source
– I2C access for external microcontroller TPS25730S QFN (RSM) 4.00 mm x 4.00 mm

2 Applications (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Power tools, power banks, retail automation and (2) The package size (length × width) is a nominal value and
payment includes pins, where applicable
• Wireless speakers, headphones
• Other personal electronics and industrial
applications
5A
5A
5-20 V 5-20 V

LDO
3.3V PP_EXT
Control
TPS25730D
VBUS LDO
3.3V
SINK_EN
DBG_ACC VBUS
CAP_MIS
PLUG_EVENT
Set GPIO
Functions Type-C Rd & sink state CC1/2 2 CC
SINK_EN
DBG_ACC
TPS25730S
PLUG_FLIP machine, CAP_MIS Set GPIO
FAULT_IN USB PD policy engine, Functions
PLUG_EVENT Type-C Rd & sink state CC1/2 2 CC
protocol and physical PLUG_FLIP machine,
layer, short-to-VBUS FAULT_IN USB PD policy engine,
protection protocol and physical
layer, short-to-VBUS
External GND protection
MCU I2C Target

External GND
Configuration MCU I2C Target
pins
Configuration
pins

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7 Parameter Measurement Information.......................... 20
2 Applications..................................................................... 1 8 Detailed Description......................................................21
3 Description.......................................................................1 8.1 Overview................................................................... 21
4 Device Comparison Table...............................................3 8.2 Functional Block Diagram......................................... 22
5 Pin Configuration and Functions...................................4 8.3 Feature Description...................................................24
6 Specifications.................................................................. 8 8.4 Device Functional Modes..........................................38
6.1 Absolute Maximum Ratings........................................ 8 8.5 Schottky for Current Surge Protection...................... 39
6.2 ESD Ratings............................................................... 9 8.6 Thermal Shutdown....................................................40
6.3 Recommended Operating Conditions.........................9 9 Application and Implementation.................................. 41
6.4 Recommended Capacitance.......................................9 9.1 Application Information............................................. 41
6.5 Thermal Information.................................................. 11 9.2 Typical Application.................................................... 42
6.6 Power Supply Characteristics................................... 12 9.3 Power Supply Recommendations.............................47
6.7 Power Consumption..................................................12 9.4 Layout....................................................................... 48
6.8 PPHV Power Switch Characteristics - TPS25730D..12 10 Device and Documentation Support..........................59
6.9 PP_EXT Power Switch Characteristics - 10.1 Device Support....................................................... 59
TPS25730S................................................................. 13 10.2 Documentation Support.......................................... 59
6.10 Power Path Supervisory......................................... 14 10.3 Receiving Notification of Documentation Updates..59
6.11 CC Cable Detection Parameters.............................15 10.4 Support Resources................................................. 59
6.12 CC PHY Parameters...............................................15 10.5 Trademarks............................................................. 59
6.13 Thermal Shutdown Characteristics......................... 16 10.6 Electrostatic Discharge Caution..............................59
6.14 ADC Characteristics................................................16 10.7 Glossary..................................................................59
6.15 Input/Output (I/O) Characteristics........................... 17 11 Revision History.......................................................... 59
6.16 I2C Requirements and Characteristics................... 17 12 Mechanical, Packaging, and Orderable
6.17 Typical Characteristics ........................................... 19 Information.................................................................... 59

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4 Device Comparison Table

INTEGRATED HIGH VOLTAGE SINK LOAD HIGH VOLTAGE GATE DRIVER FOR EXTERNAL
DEVICE NUMBER
SWITCH (PPHV) SINK PATH (PP_EXT)
TPS25730D Yes No
TPS25730S No Yes

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5 Pin Configuration and Functions

PLUG_EVENT

RESERVED

RESERVED

RESERVED
VIN_3V3

DRAIN
VBUS

VBUS
GND

GND

GND

CC2

CC1
38 37 36 35 34 33 32 31 30 29 28 27 26

LDO_3V3 1 25 VBUS_IN

ADCIN1 2 24 VBUS_IN

ADCIN2 3 23 VBUS_IN
Thermal Pad Thermal Pad
(GND) (DRAIN)
LDO_1V5 4 22 PPHV

ADCIN3 5 21 PPHV

CAP_MIS 6 20 PPHV

7 8 9 10 11 12 13 14 15 16 17 18 19
ADCIN4

I2Ct_SDA

I2Ct_SCL

DBG_ACC

GND

GND

PLUG_FLIP

GND

DRAIN

GND

GND

FAULT_IN

SINK_EN
Not to Scale

Figure 5-1. Top View of the TPS25730D 38-pin QFN Package

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PLUG_EVENT

RESERVED
VIN_3V3

VBUS

VBUS
GND

GND

CC2
32

31

30

29

28

27

26

25
LDO_3V3 1 24 CC1
ADCIN1 2 23 RESERVED
ADCIN2 3 22 RESERVED
LDO_1V5 4 Thermal 21 GATE_VBUS
Pad
ADCIN3 5 (GND) 20 GATE_VSYS
CAP_MIS 6 19 VSYS
ADCIN4 7 18 SINK_EN
I2Ct_SDA 8 17 FAULT_IN
10

12

13

14

15

16
11
9

DBG_ACC

PLUG_FLIP
I2Ct_SCL

GND

GND

GND

GND

GND
Not to Scale

Figure 5-2. Top View of the TPS25730S 32-pin QFN Package

Table 5-1. TPS25730D Pin Functions

PIN
TYPE(1) RESET DESCRIPTION
NAME NO.
ADCIN1 2 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3.
ADCIN2 3 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3.
I/O for USB Type-C. Filter noise with recommended capacitor to GND
CC1 28 I/O Hi-Z
(CCCy).
I/O for USB Type-C. Filter noise with recommended capacitor to GND
CC2 29 I/O Hi-Z
(CCCy).
11, 12, 14, 16,
GND — — Ground. Connect to ground plane.
17, 31, 34, 35
ADCIN3 5 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3.
Open Drain Output, Capability Mismatch indicator. Toggled Output: Capability
CAP_MIS 6 O Hi-Z Mismatch in negotiated PD contract, No Toggled Output: No Capability
Mismatch in negotiated PD contract.
ADCIN4 7 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3.
Open Drain Output, Sink path enabled indicator, may be used to control an
SINK_EN 19 O Hi-Z
external load switch. 0: Sink Path Enabled, 1: Sink Path Disabled
RESERVED 26, 27, 36 I Hi-Z Tie to ground or LDO_3V3
PLUG_EVENT 37 O Hi-Z Open Drain Output, 1: Connection Present 0: No Connection Present
I2C target serial clock input. Tie to pullup voltage through a resistor. May be
I2Ct_SCL 9 I Hi-Z
grounded if unused.
I2C target serial data. Open-drain input/output. Tie to pullup voltage through a
I2Ct_SDA 8 I/O Hi-Z
resistor. May be grounded if unused.
Open Drain Output, Debug Accessory attached Rp/Rp or Rd/Rd. 1: Debug
DBG_ACC 10 O Hi-Z
Accessory Present, 0: No Debug Accessory Present
Open Drain Output, Cable plug orientation indicator. 1: CC2 connected
PLUG_FLIP 13 O Hi-Z
(upside-down), 0: CC1 connected (upside-up)
Fault Input to disconnect from the port. When powered from VBUS this
FAULT_IN 18 I Hi-Z causes the PD controller to lose power when VBUS is removed. 0:
Disconnect from port, 1: Maintain connection - no fault

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Table 5-1. TPS25730D Pin Functions (continued)

PIN
TYPE(1) RESET DESCRIPTION
NAME NO.
Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This
LDO_1V5 4 O —
pin cannot source current to external circuits.
Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with
LDO_3V3 1 O —
capacitance CLDO_3V3 to GND.
DRAIN 15, 30 N/A — Connects to drain of internal FET.
PPHV 20, 21, 22 I/O High-voltage sinking node in the system.
VBUS_IN 23, 24, 25 I/O 5-V to 20-V input.
VBUS 32, 33 O VBUS input to LDO. Bypass with capacitance CVBUS to GND.
VIN_3V3 38 I — Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.

(1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output

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Table 5-2. TPS25730S Pin Functions

PIN
TYPE(1) RESET DESCRIPTION
NAME NO.
ADCIN1 2 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3.
ADCIN2 3 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3.
I/O for USB Type-C. Filter noise with recommended capacitor to GND
CC1 24 I/O Hi-Z
(CCCy).
I/O for USB Type-C. Filter noise with recommended capacitor to GND
CC2 25 I/O Hi-Z
(CCCy).
GATE_VSYS 20 O Hi-Z Connect to the N-ch MOSFET that has source tied to VSYS
GATE_VBUS 21 O Hi-Z Connect to the N-ch MOSFET that has source tied to VBUS
11, 12, 14, 15,
GND — — Ground. Connect to ground plane.
16, 28, 29
ADCIN3 5 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3.
Open Drain Output, Capability Mismatch indicator. Toggled Output: Capability
CAP_MIS 6 O Hi-Z Mismatch in negotiated PD contract, No Toggled Output: No Capability
Mismatch in negotiated PD contract.
ADCIN4 7 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3.
Open Drain Output, Sink path enabled indicator, may be used to control an
SINK_EN 18 O Hi-Z
external load switch. 0: Sink Path Enabled, 1: Sink Path Disabled
RESERVED 22, 23, 30 I Hi-Z Tie to ground or LDO_3V3
PLUG_EVENT 31 O Hi-Z Open Drain Output, 1: Connection Present 0: No Connection Present
I2C target serial clock input. Tie to pullup voltage through a resistor. May be
I2Ct_SCL 9 I Hi-Z
grounded if unused.
I2C target serial data. Open-drain input/output. Tie to pullup voltage through a
I2Ct_SDA 8 I/O Hi-Z
resistor. May be grounded if unused.
Open Drain Output, Debug Accessory attached Rp/Rp or Rd/Rd. 1: Debug
DBG_ACC 10 O Hi-Z
Accessory Present, 0: No Debug Accessory Present
Open Drain Output, Cable plug orientation indicator. 1: CC2 connected
PLUG_FLIP 13 O Hi-Z
(upside-down), 0: CC1 connected (upside-up)
Fault Input to disconnect from the port. When powered from VBUS this
FAULT_IN 17 I Hi-Z causes the PD controller to lose power when VBUS is removed. 0:
Disconnect from port, 1: Maintain connection - no fault
Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This
LDO_1V5 4 O —
pin cannot source current to external circuits.
Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with
LDO_3V3 1 O —
capacitance CLDO_3V3 to GND.
High-voltage sinking node in the system. Used to implement reverse current
VSYS 19 I —
protection (RCP) for the external sink path controlled by GATE_VSYS.
VBUS 26, 27 I/O 5-V to 20-V input. Bypass with capacitance CVBUS to GND.
VIN_3V3 32 I — Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.

(1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output

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6 Specifications
6.1 Absolute Maximum Ratings
6.1.1 TPS25730D and TPS25730S - Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN_3V3 –0.3 4
V
ADCINx –0.3 4
(4)
(2)
VBUS_IN, VBUS –0.3 28
Input voltage range (4)
CC1, CC2 –0.5 26
V
GPIOx –0.3 6.0
I2Ct_SCL, I2Ct_SDA –0.3 4
(3)
(2)
LDO_1V5 –0.3 2
Output voltage range (3)
V
LDO_3V3 –0.3 4
Sink current VBUS internally limited
Source current Positive sink current for I2Ct_SCL, I2Ct_SDA internally limited A
Positive source current for LDO_3V3, LDO_1V5 internally limited
Source current GPIOx 0.005 A
TJ Operating junction temperature –40 175 °C
TSTG Storage temperature –55 150 °C

(1) Operation outside the Absolute Maximum Rating may cause permanent damage to the device. Absolute Maximum Rating do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board.
(3) Do not apply voltage to these pins.
(4) A TVS with a break down voltage falling between the Recommended max and the Abs max value is recommended such as TVS2200.

6.1.2 TPS25730D - Absolute Maximum Ratings

MIN MAX UNIT
(1)
Input voltage range PPHV –0.3 28 V
VPPHV_VBUS_IN Source-to-source voltage 28 V
Sink current Continuous current to/from 7 A
VBUS_IN to PPHV
Pulsed current to/from 10
(2)
VBUS_IN to PPHV
TJ_PPHV Operating
PP_HV switch –40 175 °C
junction temperature

(1) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board.
(2) Pulse duration ≤ 100 µs and duty-cycle ≤ 1%.

6.1.3 TPS25730S - Absolute Maximum Ratings

MIN MAX UNIT
GATE_VBUS,
Output voltage range (1) (2) –0.3 40 V
GATE_VSYS
VGATE_VBUS - VVBUS,
VGS –0.5 12 V
VGATE_SYS - VVSYS

(1) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board.
(2) Do not apply voltage to these pins.

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6.2 ESD Ratings

PARAMETER TEST CONDITIONS VALUE UNIT
Human-body model (HBM), per ANSI/
±1000
ESDA/JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per ANSI/
±500
ESDA/JEDEC JS-002, all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3.1 TPS25730D - Recommended Operating Conditions

(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN_3V3 3.0 3.6
(1) ADCIN1, ADCIN2,VBUS_IN,
VI Input voltage range (2) 4 22 V
VBUS
PPHV 0 22
I2Ct_SDA, I2Ct_SCL, ADCINx 0 3.6
(1)
VIO I/O voltage range GPIOx 0 5.5 V
CC1, CC2 0 5.5
IPP_HV Current from VBUS_IN to PPHV 7 A
IO Output current (from LDO_3V3) GPIOx 1 mA
IO Output current (from VBUS LDO) Current from LDO_3V3 5 mA
IPP_HV ≤ 7 A –40 45
TA Ambient operating temperature °C
IPP_HV ≤ 6 A –40 65
TJ_PPHV Operating junction temperature PP_HV switch –40 150 °C
TJ Operating junction temperature –40 125 °C

(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
(2) All VBUS and VBUS_IN pins be shorted together.

6.3.2 TPS25730S - Recommended Operating Conditions

(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN_3V3 3.0 3.6
(1)
VI Input voltage range VBUS 4 22 V
VSYS 0 22
I2Ct_SDA, I2Ct_SCL, ADCINx 0 3.6
(1)
VIO I/O voltage range GPIOx 0 5.5 V
CC1, CC2 0 5.5
IO Output current (from LDO_3V3) GPIOx 1 mA
sum of current from LDO_3V3 and
IO Output current (from VBUS LDO) 5 mA
GPIOx
TJ Operating junction temperature –40 125 °C

(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.

6.4 Recommended Capacitance

over operating free-air temperature range (unless otherwise noted)
PARAMETER(1) VOLTAGE RATING MIN NOM MAX UNIT
CVIN_3V3 Capacitance on VIN_3V3 6.3 V 5 10 µF

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over operating free-air temperature range (unless otherwise noted)

PARAMETER(1) VOLTAGE RATING MIN NOM MAX UNIT
CLDO_3V3 Capacitance on LDO_3V3 6.3 V 5 10 25 µF
CLDO_1V5 Capacitance on LDO_1V5 4V 4.5 12 µF
(3)
CVBUS Capacitance on VBUS 25 V 1 4.7 10 µF
Capacitance on VSYS Sink from
CVSYS (TPS25730S) 25 V 47 100 µF
VBUS(4)
Capacitance on PPHV Sink from
CPPHV (TPS25730D) 25 V 47 100 µF
VBUS(4)
CCCy Capacitance on CCy pins(2) 6.3 V 200 400 480 pF

(1) Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by
50% at the required operating voltage, then the required external capacitor value is 10 µF.
(2) Capacitance includes all external capacitance to the Type-C receptacle.
(3) The device can be configured to quickly disable the sinking power path upon certain events. When such a configuration is used, a
capacitance on the higher side of the range is recommended.
(4) USB PD specification for cSnkBulkPd (100µF) is the maximum bulk capacitance allowed on a VBUS sink after a PD contract is in
place. The capacitance is sufficient for all power conversion devices deriving power from the PD Controller sink path. For systems
requiring greater than 100uF, VBUS surge current limiting is implemented as described in the USB3.2 specification.

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6.5 Thermal Information

6.5.1 TPS25730D - Thermal Information
TPS25730D
THERMAL METRIC(1) QFN UNIT
38 PINS
Junction-to-ambient thermal resistance
RθJA 57.4 °C/W
(sinking through PP_HV)
Junction-to-case (top) thermal resistance
RθJC (top) 30.5 °C/W
(sinking through PP_HV)
Junction-to-board thermal resistance
RθJB 21.1 °C/W
(sinking through PP_HV)
Junction-to-top characterization parameter
ψJT 18.2 °C/W
(sinking through PP_HV)
Junction-to-board characterization
ψJB 21.1 °C/W
parameter (sinking through PP_HV)
Junction-to-case (bottom GND pad)
RθJC (bot_GND) 1.8 °C/W
thermal resistance
Junction-to-case (bottom DRAIN pad)
RθJC (bot_DRAIN) 4.6 °C/W
thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5.2 TPS25730S - Thermal Information

TPS25730S
THERMAL METRIC(1) QFN UNIT
32 PINS
RθJA Junction-to-ambient thermal resistance 30.5 °C/W
RθJC (top) Junction-to-case (top) thermal resistance 24.5 °C/W
Junction-to-board (bottom) thermal
RθJC 2 °C/W
resistance
RθJB Junction-to-board thermal resistance 9.8 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
Junction-to-board characterization
ψJB 9.7 °C/W
parameter

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.6 Power Supply Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN_3V3, VBUS
rising 3.6 3.9
VVBUS_UVLO VBUS UVLO threshold falling 3.5 3.8 V
hysteresis 0.1
rising, VVBUS = 0 2.56 2.66 2.76
Voltage required on VIN_3V3 for
VVIN3V3_UVLO falling, VVBUS = 0 2.44 2.54 2.64 V
power on
hysteresis 0.12
LDO_3V3, LDO_1V5
VVIN_3V3 = 0 V, 10 µA ≤ ILOAD ≤
VLDO_3V3 Voltage on LDO_3V3 3.0 3.4 3.6 V
18 mA, VBUS ≥ 3.9 V
RLDO_3V3 Rdson of VIN_3V3 to LDO_3V3 ILDO_3V3 = 50 mA 1.4 Ω
up to maximum internal loading
VLDO_1V5 Voltage on LDO_1V5 1.49 1.5 1.65 V
condition

6.7 Power Consumption

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V, no GPIO loading
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVIN_3V3,ActSnk Current into VIN_3V3 Active Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V 3 6 mA
IVIN_3V3,IdlSnk Current into VIN_3V3 Idle Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V 1.0 mA
IVIN_3V3,Sleep Current into VIN_3V3 Sleep mode: VVBUS = 0 V, VVIN_3V3 = 3.3 V 56 µA

6.8 PPHV Power Switch Characteristics - TPS25730D

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ_PPHV = 25°C, IPPHV = 6.5
16 19
A
mΩ
Resistance from VBUS_IN to PPHV TJ_PPHV = 125°C, IPPHV =
RPPHV 24 29
power switch resistance 6.5A
TJ_PPHV = 150°C, IPPHV =
27 32 mΩ
6.5 A
Comparator mode RCP threshold, 4 V ≤ VVBUS ≤ 22 V,
VRCP 2 6 10 mV
VPPHV - VVBUS VVIN_3V3 ≤ 3.63 V
4 V ≤ VVBUS ≤ 22 V,
ILOAD = 100 mA, 500 pF
SS Soft start slew rate for GATE_VSYS < CGATE_VSYS < 16 nF, 2.8 3.3 3.80 V/ms
measure slope from 10% to
90% of final VSYS value
VVBUS = 20 V, VPPHV = 20
Time allowed to disable the internal V (initially), CPPHV< 1 nF,
tPPHV_OFF PPHV switch in normal shutdown IPPHV = 0.1 A, switch is off 400 1000 µs
mode when VVBUS_IN – VPPHV >
1V
OVP: VOVP4RCP = setting
57, VVBUS = 20 V
Time allowed to disable the internal initially, then raised to 23
PPHV switch in fast shutdown mode V in 50 ns, VPPHV =
tPPHV_OVP 2 4 µs
(VOVP4RCP exceeded), this includes VVBUS_IN (initially), CPPHV<
the response time of the comparator 1 nF, IPPHV = 0.1 A, switch
is off when VVBUS_IN –
VPPHV > 0.1 V

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6.8 PPHV Power Switch Characteristics - TPS25730D (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RCP: VRCP= setting 0,
VVBUS = 5 V, VVSYS = 5
Time allowed to disable the internal V initially, then raised to
PPHV switch in fast shutdown mode 6 V with dV/dt = 0.1 V/
tPPHV_RCP 1 2 µs
(VRCP exceeded), this includes the µs, CVBUS=10 µF, measure
response time of the comparator time from VVSYS > VBUS +
VRCP to the time of peak
voltage on VBUS
VPPHV = 20 V (initially),
VVBUS=20 V then raised
Time allowed to disable the internal
to 23 V in 50 ns, rOVP =
tPPHV_FSD PPHV switch in fast shutdown mode 0.25 20 μs
1, CPPHV < 1 nF, IPPHV =
(OVP)
0.1 A, switch is off when
VVBUS_IN – VPPHV > 0.5 V
VVBUS_IN = 5 V, CPPHV
= 0, IPPHV = 0, measure
Time to enable the internal PPHV time from register write
tPPHV_ON 1500 1800 2100 μs
switch to enable PPHV until
VVBUS_IN - VPPHV < 0.1 V,
soft start setting 3

6.9 PP_EXT Power Switch Characteristics - TPS25730S

Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0 ≤ VGATE_VSYS - VVSYS ≤ 6
V, VVSYS ≤ 22 V, VVBUS > 4 8.5 11.5 µA
V, measure IGATE_VSYS
IGATE_ON Gate driver sourcing current
0 ≤ VGATE_VBUS - VVBUS ≤
6 V, 4 V ≤ VVBUS ≤ 22 V, 8.5 11.5 µA
measure IGATE_VBUS
0 ≤ VVSYS ≤ 22 V,
IGATE_VSYS < 4 µA, measure
6 12 V
VGATE_VSYS – VVSYS, VVBUS
>4V
VGATE_ON Sourcing voltage (ON)
4 V ≤ VVBUS ≤ 22
V, IGATE_VBUS < 4 µA,
6 12 V
measure VGATE_VBUS –
VVBUS
Comparator mode RCP threshold, 4 V ≤ VVBUS ≤ 22 V,
VRCP 2 6 10 mV
VVSYS - VVBUS VVIN_3V3 ≤ 3.63 V
Normal turnoff: VVSYS =
5 V, VGATE_VSYS = 6 V, 13 µA
measure IGATE_VSYS
IGATE_OFF Sinking strength
Normal turnoff: VVBUS
= VVSYS = 5 V, VGATE_VBUS 13 µA
= 6 V, measure IGATE_VBUS
Fast turnoff: VVSYS = 5 V,
VGATE_VSYS = 6 V, assert
85 Ω
PPHV1_FAST_DISABLE,
measure RGATE_VSYS
RGATE_FSD Sinking strength Fast turnoff: VVBUS
= VVSYS = 5 V,
VGATE_VBUS = 6 V, assert 85 Ω
PPHV1_FAST_DISABLE,
measure RGATE_VBUS

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6.9 PP_EXT Power Switch Characteristics - TPS25730S (continued)

Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVIN_3V3 = 0 V, VVBUS =
3.0 V, VGATE_VSYS = 0.1
RGATE_OFF_UVLO Sinking strength in UVLO (safety) 1.5 MΩ
V, measure resistance
from GATE_VSYS to GND
4 V ≤ VVBUS ≤ 22 V,
ILOAD = 100 mA, 500 pF
SS Soft start slew rate for GATE_VSYS < CGATE_VSYS < 16 nF, 2.8 3.3 3.80 V/ms
measure slope from 10% to
90% of final VSYS value
VVBUS = 20 V, QG of
Time allowed to disable the external external FET = 40 nC or
tGATE_VBUS_OFF FET via GATE_VBUS in normal CGATE_VBUS < 3 nF, gate 450 4000 µs
shutdown mode.(1) is off when VGATE_VBUS –
VVBUS < 1 V
OVP: VOVP4RCP = setting
Time allowed to disable the 57, VVBUS = 20 V initially,
external FET via GATE_VBUS in then raised to 23 V in 50
tGATE_VBUS_OVP fast shutdown mode (VOVP4RCP ns, QG of external FET 3 5 µs
exceeded), this includes the = 40 nC or CGATE_VBUS
response time of the comparator(1) < 3 nF, gate is off when
VGATE_VBUS – VVBUS < 1 V
RCP: VRCP = setting 0,
Time allowed to disable the external VVBUS = 5 V, VVSYS = 5 V
FET via GATE_VBUS in fast initially, then raised to 5.5
tGATE_VBUS_RCP shutdown mode (VRCP exceeded), V in 50 ns, QG of external 1 2 µs
this includes the response time of the FET = 40 nC or CGATE_VBUS
comparator(1) < 3 nF, gate is off when
VGATE_VBUS – VVBUS < 1 V
VVSYS= 20 V, QG of
Time allowed to disable the external external FET = 40 nC or
tGATE_VSYS_OFF FET via GATE_VSYS in normal CGATE_VBUS < 3 nF, gate 450 4000 µs
shutdown mode(1) is off when VGATE_VSYS –
VVSYS < 1 V
VVBUS = 20 V initially, then
raised to 23 V in 50 ns,
Time allowed to disable the external
QG of external FET = 40
tGATE_VSYS_FSD FET via GATE_VSYS in fast 0.25 20 μs
nC or CGATE_VBUS < 3 nF,
shutdown mode (OVP)(1)
gate is off when VGATE_VSYS
– VVSYS < 1 V, rOVP = 1
Measure time from when
VGS = 0 V until VGS >3 V,
tGATE_VBUS_ON Time to enable GATE_VBUS (1) 0.25 2 ms
where VGS = VGATE_VBUS –
VVBUS

(1) These values depend upon the characteristics of the external N-ch MOSFET. The typical values were measured when
Px_GATE_VSYS and Px_GATE_VBUS were used to drive two CSD17571Q2 in common drain back-to-back configuration.

6.10 Power Path Supervisory

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBUS overvoltage protection for RCP OVP detected when VVBUS >
VOVP4RCP 5.0 24 V
programmable range VOVP4RCP
VOVP4RCPH Hysteresis 1.75 2 2.25 %
Ratio of OVP4RCP input used
rOVP for OVP4VSYS comparator. rOVP × 1 V/V
VOVP4VSYS = VOVP4RCP
VBUS overvoltage protection range for OVP detected when rOVP ×
VOVP4VSYS 5 27.5 V
VSYS protection VVBUS > VOVP4RCP

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Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBUS falling, % of
VOVP4VSYS Hysteresis 2 2.3 2.6 %
VOVP4VSYS, rOVP
VVBUS = 22 V, measure
IDSCH VBUS discharge current 4 15 mA
IVBUS

6.11 CC Cable Detection Parameters

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Type-C Sink (Rd pull-down)
Open/Default detection threshold
rising 0.2 0.24 V
when Rd applied to Px_CCy
VSNK1 Open/Default detection threshold
falling 0.16 0.20 V
when Rd applied to Px_CCy
hysteresis 0.04 V
Default/1.5A detection threshold falling 0.62 0.68 V
VSNK2 Default/1.5A detection threshold rising 0.63 0.66 0.69 V
hysteresis 0.01 V
1.5A/3.0A detection threshold
falling 1.17 1.25 V
when Rd applied to Px_CCy
VSNK3 1.5A/3.0A detection threshold
rising 1.22 1.3 V
when Rd applied to Px_CCy
hysteresis 0.05 V
0.25 V ≤ VPx_CCy ≤ 2.1 V, measure
RSNK Rd pulldown resistance 4.1 6.1 kΩ
resistance on Px_CCy
VVIN_3V3=0V, 64 µA < IPx_CCy<96
0.25 1.32
µA
VVIN_3V3=0V, 166 µA <
VCLAMP Dead battery Rd clamp 0.65 1.32 V
IPx_CCy<194 µA
VVIN_3V3=0V, 304 µA < IPx_CCy<
1.20 2.18
356 µA
VPx_VBUS = 0, VVIN_3V3=3.3V,
VPx_CCy=5 V, measure resistance 500 kΩ
resistance from Px_CCy to GND on Px_CCy
ROpen
when configured as open. VPx_VBUS = 5V, VVIN_3V3 = 0,
VPx_CCy=5 V, measure resistance 500 kΩ
on Px_CCy
Common Sink
deglitch time for comparators on
tCC 3.2 ms
Px_CCy

6.12 CC PHY Parameters

Operating under these conditions unless otherwise noted: and ( 3.0 V ≤ VVIN_3V3 ≤ 3.6 V or VVBUS ≥ 3.9 V )
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Transmitter
VTXHI Transmit high voltage on CCy Standard External load 1.05 1.125 1.2 V
VTXLO Transmit low voltage on CCy Standard External load –75 75 mV
Transmit output impedance while
ZDRIVER measured at 750 kHz 33 54 75 Ω
driving the CC line using CCy

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Operating under these conditions unless otherwise noted: and ( 3.0 V ≤ VVIN_3V3 ≤ 3.6 V or VVBUS ≥ 3.9 V )
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Rise time. 10 % to 90 % amplitude
points on CCy, minimum is under
tRise CCCy = 520 pF 300 ns
an unloaded condition. Maximum
set by TX mask
Fall time. 90 % to 10 % amplitude
points on CCy, minimum is under
tFall CCCy = 520 pF 300 ns
an unloaded condition. Maximum
set by TX mask
0 ≤ VVIN_3V3 ≤ 3.6 V, VVBUS ≥ 4 V.
OVP detection threshold for USB
VPHY_OVP Initially VCC1 ≤ 5.5 V and VCC2 ≤ 5.5 8.5 V
PD PHY
5.5 V, then VCCx rises
Receiver
Does not include pullup or
ZBMCRX Receiver input impedance on CCy pulldown resistance from cable 1 MΩ
detect. Transmitter is Hi-Z
Capacitance looking into the CC
CCC Receiver capacitance on CCy(1) 120 pF
pin when in receiver mode
Rising threshold on CCy for
VRX_SNK_R Sink mode (rising) 499 525 551 mV
receiver comparator
Rising threshold on CCy for
VRX_SRC_R Source mode (rising) 784 825 866 mV
receiver comparator
Falling threshold on CCy for
VRX_SNK_F Sink mode (falling) 230 250 270 mV
receiver comparator
Falling threshold on CCy for
VRX_SRC_F Source mode (falling) 523 550 578 mV
receiver comparator

(1) CCC includes only the internal capacitance on a CCy pin when the pin is configured to be receiving BMC data. External capacitance
is needed to meet the required minimum capacitance per the USB-PD Specifications (cReceiver). Therefore, TI recommends
adding CCCy externally.

6.13 Thermal Shutdown Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Temperature rising 145 160 175 °C
TSD_MAIN Temperature shutdown threshold
hysteresis 20 °C

6.14 ADC Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3.6-V max scaling, voltage
14 mV
divider of 3
LSB Least significant bit 25.2-V max scaling, voltage
98 mV
divider of 21
4.07-A max scaling 16.5 mA
0.05 V ≤ VADCINx ≤ 3.6
V, VADCINx ≤ VLDO_3V3
–2.7 2.7
0.05 V ≤ VGPIOx ≤ 3.6 V, VGPIOx
≤ VLDO_3V3
GAIN_ERR Gain error %
2.7 V ≤ VLDO_3V3 ≤ 3.6 V –2.4 2.4
0.6 V ≤ VVBUS ≤ 22 V –2.1 2.1
1 A ≤ IVBUS ≤ 3 A –2.1 2.1

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Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.05 V ≤ VADCINx ≤ 3.6
V, VADCINx ≤ VLDO_3V3
–4.1 4.1
0.05 V ≤ VGPIOx ≤ 3.6 V, VGPIOx
(1) ≤ VLDO_3V3 mV
VOS_ERR Offset error
2.7 V ≤ VLDO_3V3 ≤ 3.6 V –4.5 4.5
0.6 V ≤ VVBUS ≤ 22 V –4.1 4.1
1 A ≤ IVBUS ≤ 3 A –4.5 4.5 mA

(1) The offset error is specified after the voltage divider.

6.15 Input/Output (I/O) Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GPIO_VIH GPIOx high-Level input voltage VLDO_3V3 = 3.3V 1.3 V
GPIO_VIL GPIOx low-level input voltage VLDO_3V3 = 3.3V 0.54 V
GPIO_HYS GPIOx input hysteresis voltage VLDO_3V3 = 3.3V 0.09 V
GPIO_ILKG GPIOx leakage current VGPIOx = 3.45 V –1 1 µA
GPIO_DG GPIOx input deglitch 20 ns
GPIO0-9 (Outputs)
GPIO_VOH GPIOx output high voltage VLDO_3V3 = 3.3V, IGPIOx= -2mA 2.9 V
GPIO_VOL GPIOx output low voltage VLDO_3V3 = 3.3V, IGPIOx=2mA 0.4 V
ADCINx
ADCIN_ILKG ADCINx leakage current VADCINx ≤ VLDO_3V3 –1 1 µA
time from LDO_3V3 going
tBOOT high until ADCINx is read for 10 ms
configuration

6.16 I2C Requirements and Characteristics

994
Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SDA and SCL Common Characteristics Target)
VIL Input low signal VLDO_3V3=3.3V, 0.54 V
VIH Input high signal VLDO_3V3=3.3V, 1.3 V
VHYS Input hysteresis VLDO_3V3=3.3V 0.165 V
VOL Output low voltage IOL=3 mA 0.36 V
ILEAK Input leakage current Voltage on pin = VLDO_3V3 –3 3 µA
IOL Max output low current VOL=0.4 V 15 mA
IOL Max output low current VOL=0.6 V 20 mA
tf Fall time from 0.7*VDD to 0.3*VDD VDD = 1.8V, 10 pF ≤ Cb ≤ 400 pF 12 80 ns
tf Fall time from 0.7*VDD to 0.3*VDD VDD = 3.3V, 10 pF ≤ Cb ≤ 400 pF 12 150 ns
tSP I2C pulse width suppressed 50 ns
CI pin capacitance (internal) 10 pF
Capacitive load for each bus line
Cb 400 pF
(external)
SDA and SCL Standard Mode Characteristics (Target)
fSCLS Clock frequency for target VDD = 1.8V or 3.3V 100 kHz

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Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Transmitting Data, VDD = 1.8V or
tVD;DAT Valid data time 3.45 µs
3.3V, SCL low to SDA output valid
Transmitting Data, VDD = 1.8V or
tVD;ACK Valid data time of ACK condition 3.3V, ACK signal from SCL low to 3.45 µs
SDA (out) low
SDA and SCL Fast Mode Characteristics (Target)
fSCLS Clock frequency for target VDD = 1.8V or 3.3V 100 400 kHz
Transmitting data, VDD = 1.8V,
tVD;DAT Valid data time SCL 0.9 µs
low to SDA output valid
Transmitting data, VDD = 1.8V or
3.3V, ACK
tVD;ACK Valid data time of ACK condition 0.9 µs
signal from SCL low to SDA (out)
low
Clock frequency for Fast Mode
fSCLS VDD = 1.8V or 3.3V 400 800 kHz
Plus
Transmitting data, VDD = 1.8V or
tVD;DAT Valid data time 3.3V, SCL 0.55 µs
low to SDA output valid
Transmitting data, VDD = 1.8V or
3.3V, ACK
tVD;ACK Valid data time of ACK condition 0.55 µs
signal from SCL low to SDA (out)
low

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6.17 Typical Characteristics

7.5 5.8

VPx_VBUS = 4V
VPx_VBUS = 22V 5.78
7

VOVP4RCP (mV)
6.5 5.76
VRCP (mV)

6 5.74

5.5 5.72

5 5.7
-60 -30 0 30 60 90 120 150 -50 0 50 100 150
TJ (oC) TJ (oC) TypG
TypG

Figure 6-1. VRCP vs. Temperature Figure 6-2. VOVP4RCP (Setting 2) vs. Temperature

28 100
70 Single Pulse Duration
50 100 ms
10 ms
26 30 1 ms

Source-to-Source Current (A)

100 Ps
20
10 Ps
24
10
RPP_HV (m:)

7
22 5

20 2

1
18 0.7
0.5

0.3
16
0.2

14 0.1
0.1 0.2 0.3 0.5 0.7 1 2 3 4 5 6 7 8 10 20 30 40 50
-20 0 20 40 60 80 100 120 140 160 Source-to-Source Voltage (V)
TJ (oC)
SOAf
TypG
Figure 6-4. Safe-Operating-Area (SOA) of PPHV for TPS25730D
Figure 6-3. RPPHV vs. Temperature for TPS25730D
9.4 10.2
IGATE_VBUS
9.2 10.15 IGATE_VSYS

9 10.1
GATE_VSYS: VSYS= 0 V
IGATE_ON (PA)

8.8 GATE_VSYS: VSYS= 22 V

VGATE (V)

10.05
GATE_VBUS
8.6
10
8.4
9.95
8.2
9.9
8
9.85
7.8 -20 0 20 40 60 80 100 120 140
-40 -20 0 20 40 60 80 100 120 140 TJ (oC)
TJ (oC) TypG
TypG

Figure 6-6. VGATE_VSYS_ON vs. Temperature for TPS25730S

Figure 6-5. VGATE_VBUS_ON vs. Temperature for TPS25730S

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7 Parameter Measurement Information

tf tr tSU;DAT

70 % 70 %
SDA
30 % 30 % cont.
tHD;DAT tVD;DAT
tf
tHIGH
tr
70 % 70 % 70 % 70 %
SCL 30 % 30 %
30 % 30 % cont.
tHD;STA tLOW
9th clock
S 1 / fSCL
1st clock cycle

tBUF

SDA

tVD;ACK
tSU;STA tHD;STA tSP tSU;STO

70 %
SCL 30 %
Sr P S
9th clock 002aac938

Figure 7-1. I2C Target Interface Timing

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8 Detailed Description
8.1 Overview
The TPS25730 is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug and
orientation detection for USB Type-C and PD receptacles. The TPS25730 communicates with the other USB
Type-C and PD port partner at the opposite end of the cable. The device also enables integrates a high current
port power switch for sinking.
The TPS25730 is divided into several main sections:
• USB-PD controller
• Cable plug and orientation detection circuitry
• Port power switch
• Power management circuitry
• Digital core
The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD
data is output through either the CC1 pin or the CC2 pin, depending on the orientation of the reversible USB
Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features, and
more detailed circuitry, see USB-PD Physical Layer.
The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug
insertion the cable orientation. For a high-level block diagram of cable plug and orientation detection, a
description of its features, and more detailed circuitry, see Cable Plug and Orientation Detection.
For a high-level block diagram of the port power switch, a description of its features, and more detailed circuitry,
see Power Paths.
The power management circuitry receives and provides power to the TPS25730 internal circuitry and LDO_3V3
output. See Power Management for more information.
The digital core provides the engine for receiving, processing, and sending all USB-PD packets as well as
handling control of all other TPS25730 functionality. For a high-level block diagram of the digital core, a
description of its features, and more detailed circuitry, see Digital Core.
The TPS25730 also integrates a thermal shutdown mechanism and runs off of accurate clocks provided by the
integrated oscillator.

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8.2 Functional Block Diagram

PPHV VBUS_IN

VBUS

LDO_3V3

LDO_1V5
VIN_3V3 Power Supervisor
GND

ADCINx

I2Ct_SDA/SCL
Core & Other Digital
GPIO
CC1

Cable Detect, Cable Power, & USB PD PHY CC2

Figure 8-1. TPS25730D

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GATE_VBUS
GATE_VSYS
VBUS

LDO_3V3

VSYS
LDO_1V5
VIN_3V3 Power Supervisor

GND

ADCINx
I2Ct_SDA/SCL
Core & Other Digital
GPIO
CC1

Cable Detect, Cable Power, & USB PD PHY CC2

Figure 8-2. TPS25730S

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8.3 Feature Description

8.3.1 USB-PD Physical Layer
Figure 8-3 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and
orientation detection block.

RSNK

CC1
Digital USB-PD PHY
Core (Rx/Tx)

LDO_3V3 CC2

RSNK

Figure 8-3. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry

USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output
on the same pin (CC1 or CC2) that is DC biased due to the Rp (or Rd) cable attach mechanism.
8.3.1.1 USB-PD Encoding and Signaling
Figure 8-4 illustrates the high-level block diagram of the baseband USB-PD transmitter. Figure 8-5 illustrates the
high-level block diagram of the baseband USB-PD receiver.

4b5b BMC
Data to PD_TX
Encoder Encoder

CRC

Figure 8-4. USB-PD Baseband Transmitter Block Diagram

BMC SOP 4b5b Data

from PD_RX
Decoder Detect Decoder

CRC

Figure 8-5. USB-PD Baseband Receiver Block Diagram

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8.3.1.2 USB-PD Bi-Phase Marked Coding

The USB-PD physical layer implemented in the TPS25730 is compliant to the USB-PD Specifications. The
encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark
Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in
the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity
(limited to 1/2 bit over an arbitrary packet, so a very low DC level). Figure 8-6 illustrates Biphase Mark Coding.
0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1
Data in

BMC

Figure 8-6. Biphase Mark Coding Example

The USB PD baseband signal is driven onto the CC1 or CC2 pin with a tri-state driver. The tri-state driver is slew
rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When sending the
USB-PD preamble, the transmitter starts by transmitting a low level. The receiver at the other end tolerates the
loss of the first edge. The transmitter terminates the final bit by an edge to ensure the receiver clocks the final bit
of EOP.
8.3.1.3 USB-PD BMC Transmitter
The TPS25730 transmits and receives USB-PD data over one of the CCy pins for a given CC pin pair (one
pair per USB Type-C port). The CCy pins are also used to determine the cable orientation and maintain the
cable/device attach detection. Thus, a DC bias exists on the CCy pins. The transmitter driver overdrives the CCy
DC bias while transmitting, but returns to a Hi-Z state, allowing the DC voltage to return to the CCy pin when it is
not transmitting. While either CC1 or CC2 can be used for transmitting and receiving, during a given connection
only, the one that mates with the CC pin of the plug is used, so there is no dynamic switching between CC1 and
CC2. Figure 8-7 shows the USB-PD BMC TX and RX driver block diagram.

LDO_3V3

PD_TX Level Shifter Driver

CC1

PD_RX Level Shifter CC2

Digitally
Adjustable
VREF (VRXHI, VRXLO)
USB-PD Modem

Figure 8-7. USB-PD BMC TX/Rx Block Diagram

Figure 8-8 shows the transmission of the BMC data on top of the DC bias. Note that the DC bias can be
anywhere between the minimum and maximum threshold for detecting a Sink attach. This note means that the
DC bias can be above or below the VOH of the transmitter driver.

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VOH

DC Bias DC Bias

VOL

DC Bias VOH DC Bias

VOL

Figure 8-8. TX Driver Transmission with DC Bias

The transmitter drives a digital signal onto the CCy lines. The signal peak, VTXHI, is set to meet the TX masks
defined in the USB-PD Specifications. Note that the TX mask is measured at the far-end of the cable.
When driving the line, the transmitter driver has an output impedance of ZDRIVER. ZDRIVER is determined by the
driver resistance and the shunt capacitance of the source and is frequency dependent. ZDRIVER impacts the
noise ingression in the cable.
Figure 8-9 shows the simplified circuit determining ZDRIVER. It is specified such that noise at the receiver is
bounded.

RDRIVER ZDRIVER
Driver
CDRIVER

Figure 8-9. ZDRIVER Circuit

8.3.1.4 USB-PD BMC Receiver

The receiver block of the TPS25730 receives a signal that follows the allowed Rx masks defined in the USB PD
specification. The receive thresholds and hysteresis come from this mask.
Figure 8-10 shows an example of a multi-drop USB-PD connection (only the CC wire). This connection has
the typical Sink (device) to Source (host) connection, but also includes cable USB-PD Tx/Rx blocks. Only one
system can be transmitting at a time. All other systems are Hi-Z (ZBMCRX). The USB-PD Specification also
specifies the capacitance that can exist on the wire as well as a typical DC bias setting circuit for attach
detection.

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Source Sink
System Pullup for System
Attach
Connector Cable Connector
Detection
CC wire
Tx Tx

CRECEIVER
CRECEIVER

Rx Rx

CCablePlug_CC CCablePlug_CC

RD for
Attach
Detection

Rx Rx
Tx Tx

623¶ 3' 623¶¶ 3'

communication only communication only
(eMarker #1) (eMarker #2)

Figure 8-10. Example USB-PD Multi-Drop Configuration

8.3.1.5 Squelch Receiver

The TPS25730 has a squelch receiver to monitor for the bus idle condition as defined by the USB PD
specification.
8.3.2 Power Management
The TPS25730 power management block receives power and generates voltages to provide power to the
TPS25730 internal circuitry. These generated power rails are LDO_3V3 and LDO_1V5. LDO_3V3 can also be
used as a low power output for external EEPROM memory. The power supply path is shown in Figure 8-11.

RLDO_3V3

VIN_3V3 VBUS

VREF

LDO_3V3 LDO

VREF

LDO_1V5 LDO

Figure 8-11. Power Supplies

The TPS25730 is powered from either VIN_3V3 or VBUS. The normal power supply input is VIN_3V3. When
powering from VIN_3V3, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3-V circuitry and I/Os. A
second LDO steps the voltage down from LDO_3V3 to LDO_1V5 to power the 1.5-V core digital circuitry. When
VIN_3V3 power is unavailable and power is available on VBUS, it is referred to as the dead-battery start-up
condition. In a dead-battery start-up condition, the TPS25730 opens the VIN_3V3 switch until the host clears

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the dead-battery flag through I2C. Therefore, the TPS25730 is powered from the VBUS input with the higher
voltage during the dead-battery start-up condition and until the dead-battery flag is cleared. When powering from
a VBUS input, the voltage on VBUS is stepped down through an LDO to LDO_3V3.
8.3.2.1 Power-On And Supervisory Functions
A power-on reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a
good supply is present.
8.3.2.2 VBUS LDO
The TPS25730 contains an internal high-voltage LDO which is capable of converting VBUS to 3.3 V for powering
internal device circuitry. The VBUS LDO is only used when VIN_3V3 is low (the dead-battery condition). The
VBUS LDO is powered from VBUS.
8.3.3 Power Paths
TPS25730D has a integrated high voltage load switch for sinking power path: PPHV. TPS25730S has a high
voltage gate driver for sink path control: PP_EXT. Each power path is described in detail in this section.
8.3.3.1 TPS25730D Internal Sink Path
The TPS25730D has internal controls for internal FETs (GATE_VSYS and GATE_VBUS as shown in Figure
8-12) that require that VBUS_IN be above VVBUS_UVLO before being able to enable the sink path. Figure 8-12
shows a diagram of the sink path. When a sink path is enabled, the circuitry includes a slew rate control loop
to ensure that external switches do not turn on too quickly (SS). The TPS25730D senses the PPHV and VBUS
voltages to control the gate voltages to enable or disable the FETs.
The sink-path control includes overvoltage protection (OVP) and reverse current protection (RCP).

PP_HV

PPHV VBUS
GATE_VBUS
GATE_VSYS

Gate Control and Sense

Copyright © 2018, Texas Instruments Incorporated

Figure 8-12. Internal Sink Path

8.3.3.2 TPS25730S - External Sink Path Control PP_EXT

The TPS25730S has two N-ch gate drivers designed to control a sinking path from VBUS to VSYS. The charge
pump for these gate drivers requires VBUS to be above VVBUS_UVLO. When a sink path is enabled, the
circuitry includes a slew rate control loop to ensure that external switches do not turn on too quickly (SS). The
TPS25730S senses the VSYS and VBUS voltages to control the gate voltages to enable or disable the external
FETs.
The sink-path control includes overvoltage protection (OVP), and reverse current protection (RCP). Adding
resistance in series with a GATE pin of the TPS25730S and the gate pin of the N-ch MOSFET slows down the
turnoff time when OVP or RCP occurs. Any such resistance must be minimized, and not allowed to exceed 3 Ω.

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PP_EXT

GATE_VBUS
GATE_VSYS
VSYS

VBUS
PP_EXT Gate Control and
Sense

Copyright © 2018, Texas Instruments Incorporated

Figure 8-13. PP_EXT External Sink Path Control

Figure 8-14 shows the GATE_VSYS gate driver in more detail.

VSYS
GATE_VSYS

switch enabled when

gate driver is disabled and
VVIN_3V3 < VVIN_3V3_UVLO
VGATE_ON

RGATE_FSD
Regular enable/
disable
Fast
disable
IGATE_OFF IGATE_ON
Charge VBUS
RGATE_OFF_UVLO Pump
GND

Figure 8-14. Details of the VSYS Gate Driver

8.3.4 Cable Plug and Orientation Detection

Figure 8-15 shows the plug and orientation detection block at each CCy pin (CC1, CC2). Each pin has identical
detection circuitry.

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VREF1

CCy

VREF2

VREF3 RSNK

Figure 8-15. Plug and Orientation Detection Block

8.3.5 Overvoltage Protection (CC1, CC2)

The TPS25730 detects when the voltage on the CC1 or CC2 pin is too high and takes action to protect the
system. The protective action is to disable the USB PD transmitter.

CC1

VPHY_OVP
Control Logic
Disable and USB
PD PHY Tx
CC2

VPHY_OVP

Figure 8-16. Overvoltage and Reverse Current Protection for CC1 and CC2

8.3.6 Default Behavior Configuration (ADCIN1, ADCIN2)

Note
This functionality is firmware controlled and subject to change.

The ADCINx inputs to the internal ADC control the behavior of the TPS25730 in response to VBUS being
supplied when VIN_3V3 is low (that is the dead-battery scenario). The ADCINx pins must be externally tied to
the LDO_3V3 pin via a resistive divider as shown in the following figure. At power-up the ADC converts the
ADCINx voltage and the digital core uses these two values to determine start-up behavior. The available start-up
configurations include options for I2C target address of I2Ct_SCL/SDA, sink path control in dead-battery, and
default configuration.

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LDO_3V3

Mux an d
ADC
Divi ders

ADCINx

Figure 8-17. ADCINx Resistor Divider

The device behavior is determined in several ways depending upon the decoded value of the ADCINx pins. The
following table shows the decoded values for different resistor divider ratios. See I2C Address Setting for details
on how ADCINx decoded values affects default I2C target address.
Table 8-1. Decoding of ADCIN1 and ADCIN2 Pins
DIV = RDOWN / (RUP + RDOWN)(1) Without Using RUP
ADCINx Decoded Value
MIN Target MAX or RDOWN

0 0.0114 0.0228 tie to GND 0

0.0229 0.0475 0.0722 N/A 1
0.0723 0.1074 0.1425 N/A 2
0.1425 0.1899 0.2372 N/A 3
0.2373 0.3022 0.3671 N/A 4
0.3672 0.5368 0.7064 tie to LDO_1V5 5
0.7065 0.8062 0.9060 N/A 6
0.9061 0.9530 1.0 tie to LDO_3V3 7

(1) See I2C Address Setting to see the exact meaning of I2C Address Index.

8.3.7 ADC
The TPS25730 ADC is shown in Figure 8-18. The ADC is an 8-bit successive approximation ADC. The input to
the ADC is an analog input mux that supports multiple inputs from various voltages and currents in the device.
The output from the ADC is available to be read and used by application firmware.

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Voltage
VBUS
Divider 2

LDO_3V3 Voltage 8 bits

Divider 1 Input ADC
Mux
GPIO Buffers &
Voltage
ADCINx Divider 1

Figure 8-18. SAR ADC

8.3.8 Digital Interfaces

The TPS25730 contains several different digital interfaces which can be used for communicating with other
devices. The available interfaces include an I2C target and preconfigured GPIO.
8.3.9 Digital Core
Figure 8-19 shows a simplified block diagram of the digital core.

GPIO

ADCINx CBL_DET
USB PD Phy
Bias CTL
and USB-PD

I2Ct_SDA Digital Core

I2C
I2C to Port 1
System Control (target)
I2Ct_SCL

OSC
ADC Read

Thermal Temp
Shutdown Sense ADC

Figure 8-19. Digital Core Block Diagram

8.3.10 I2C Interface

The TPS25730 has one I2C target interface ports: I2Ct. I2C port I2Ct is comprised of the I2Ct_SDA and
I2Ct_SCL pins. This interface provide general status information about the TPS25730, as well as the ability to
control the TPS25730 behavior, supporting communications to/from a connected device and/or cable supporting
BMC USB-PD, and providing information about connections detected at the USB-C receptacle.
When the TPS25730 is in 'APP ' mode TI recommends to use standard mode or Fast mode (that is a clock
speed no higher than 400 kHz).

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Table 8-2. I2C Summary

I2C BUS TYPE TYPICAL USAGE
Optionally can be connected to an external MCU. Also used to load the patch and application
I2Ct Target
configuration.

8.3.10.1 I2C Interface Description

The TPS25730 supports Standard and Fast mode I2C interfaces. The bidirectional I2C bus consists of the serial
clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pullup resistor. Data
transfer can be initiated only when the bus is not busy.
A controller sending a Start condition, a high-to-low transition on the SDA input and output, while the SCL input
is high initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit
(MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred
during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period
as changes in the data line at this time are interpreted as control commands (Start or Stop). The controller sends
a Stop condition, a low-to-high transition on the SDA input and output while the SCL input is high.
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
target receiver is addressed, it must generate an ACK after each byte is received. Similarly, the controller must
generate an ACK after each byte that it receives from the target transmitter. Setup and hold times must be met to
ensure proper operation.
A controller receiver signals an end of data to the target transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the target. The controller receiver holding the SDA line high does this.
In this event, the transmitter must release the data line to enable the controller to generate a Stop condition.
Figure 8-20 shows the start and stop conditions of the transfer. Figure 8-21 shows the SDA and SCL signals for
transferring a bit. Figure 8-22 shows a data transfer sequence with the ACK or NACK at the last clock pulse.

SDA

SCL

S P
Start Condition Stop Condition

Figure 8-20. I2C Definition of Start and Stop Conditions

SDA

SCL

Data Line Change

Figure 8-21. I2C Bit Transfer

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SCL from
Controller

Figure 8-22. I2C Acknowledgment

8.3.10.1.1 I2C Clock Stretching

The TPS25730 features clock stretching for the I2C protocol. The TPS25730 target I2C port can hold the clock
line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The
controller communicating with the target must not finish the transmission of the current bit and must wait until the
clock line actually goes high. When the target is clock stretching, the clock line remains low.
The controller must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs
for standard 100-kbps I2C) before pulling the clock low again.
Any clock pulse can be stretched but typically it is the interval before or after the acknowledgment bit.
8.3.10.1.2 Unique Address Interface
The Unique Address Interface allows for complex interaction between an I2C controller and a single TPS25730.
The I2C target sub-address is used to receive or respond to Host Interface protocol commands. Figure 8-23 and
Figure 8-24 show the write and read protocol for the I2C target interface, and a key is included in Figure 8-25
to explain the terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated
here in part.
1 7 1 1 8 1 8 1 8 1

S Unique Address Wr A Register Number A Byte Count = N A Data Byte 1 A

8 1 8 1

Data Byte 2 A Data Byte N A P

Figure 8-23. I2C Unique Address Write Register Protocol

1 7 1 1 8 1 1 7 1 1 8 1

S Unique Address Wr A Register Number A Sr Unique Address Rd A Byte Count = N A

8 1 8 1 8 1

Data Byte 1 A Data Byte 2 A Data Byte N A P

Figure 8-24. I2C Unique Address Read Register Protocol

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1 7 1 1 8 1 1
S Target Address Wr A Data Byte A P
x x
S Start condition
SR Repeated start condition
Rd Read (bit value of 1)
Wr Write (bit value of 0
X Field is required to have the value x
A Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK)
P Stop condition

Controller-to-target

Target-to-controller

Continuation of protocol

Figure 8-25. I2C Read/Write Protocol Key

8.3.10.1.3 Pin Strapping to Configure Default Behavior

During the boot procedure, the device reads the ADCINx pins and sets the I2C address and configuration based
on the table below.
Table 8-3. Device Configuration using ADCIN1 and ADCIN2
ADCIN1 DECODED ADCIN2 DECODED
VALUE (MIN VALUE (MAX I2C ADDRESS DEAD BATTERY CONFIGURATION
VOLTAGE) (1) VOLTAGE) (1)
0 (5V) 7 (20V) 0x20
1 (9V) 7 (20V) 0x21
2 (12V) 7 (20V) 0x20
3 (15V) 7 (20V) 0x21
4 (20V) 7 (20V) 0x20
0 (5V) 5 (15V) 0x20
1 (9V) 5 (15V) 0x21 AlwaysEnableSink: The device always enables the sink path
regardless of the amount of current the attached source is
2 (12V) 5 (15V) 0x20 offering. USB PD is disabled until configuration is loaded.
3 (15V) 5 (15V) 0x21
0 (5V) 3 (12V) 0x20
1 (9V) 3 (12V) 0x21
2 (12V) 3 (12V) 0x20
0 (5V) 1 (9V) 0x20
1 (9V) 1 (9V) 0x21

(1) See Section 8.3.6 for how to configure a given ADCINx decoded value.

8.3.11 Minimum Voltage Configuration

The minimum voltage for the USB Power Delivery Sink Capabilities can be set according to the table below.
When the received USB PD Source Capabilities do not meet the minimum and maximum voltage range the
Capabilities Mismatch bit is set on the USB PD request. When the Minimum Voltage is set greater than 5 V the
Higher Capability bit is set in the Sink Capabilities.

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Table 8-4. Minimum Voltage Configuration for Sink Capabilities - ADCIN1 Decoded
ADCIN1 Decoded Value Minimum Voltage Configuration

0 5V

1 9V

2 12 V

3 15 V

4 20 V

5 Reserved

6 Reserved

7 Reserved

8.3.12 Maximum Voltage Configuration

The maximum voltage for the USB Power Delivery Sink Capabilities is set according to the table below.
When the received USB PD Source Capabilities do not meet the minimum and maximum voltage range the
Capabilities Mismatch bit is set on the USB PD request.
Table 8-5. Maximum Voltage Configuration for Sink Capabilities - ADCIN2 Decoded
ADCIN2 Decoded Value Maximum Voltage Configuration

1 9V

3 12 V

5 15 V

7 20 V

8.3.13 Sink Current Configuration

The sink current is configured according to the table below. The configuration sets Operating and Maximum
Current in the USB PD request message. The Operating Current is defined as the the current required for the
sink to be functional. The Maximum Current is defined as the maximum current the sink may use. The Operating
and Maximum Current can be the same if the Operational Current is the maximum current required for the sink
to be functional. The Capabilities Mismatch bit is set when the PD Source Capabilities do not meet the Operating
Current. When the Operating Current is set to 0 A the Capability Mismatch bit is not set.
Table 8-6. ADCIN3 & ADCIN4 Sink Current Configuration
ADCIN3 ADCIN4 Operating Current Maximum Current

0 0 0 1.5 A

0 1 0 3A

0 2 0 4A

0 3 0 5A

0 4 0.5 A 1.5 A

0 5 0.5 A 3A

0 6 0.5 A 4A

0 7 0.5 A 5A

1 0 1A 1.5 A

1 1 1A 3A

1 2 1A 4A

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Table 8-6. ADCIN3 & ADCIN4 Sink Current Configuration (continued)

ADCIN3 ADCIN4 Operating Current Maximum Current

1 3 1A 5A

1 4 1.5 A 1.5 A

1 5 1.5 A 3A

1 6 1.5 A 4A

1 7 1.5 A 5A

2 1 2A 3A

2 2 2A 4A

2 3 2A 5A

2 5 2.5 A 3A

2 6 2.5 A 4A

2 7 2.5 A 5A

3 1 3A 3A

3 2 3A 4A

3 3 3A 5A

3 6 3.5 A 4A

3 7 3.5 A 5A

4 2 4A 4A

4 3 4A 5A

4 7 4.5 A 5A

5 3 5A 5A

8.3.14 Autonegotiate Sink Minimum Power

The minimum power required is determined by the Operating Current configuration multiplied by the Minimum
Voltage configuration. When the received PD Source Capabilities power do not meet the Autonegotiate Sink
Minimum Power the Capability Mismatch bit is set in the PD Request message.
Table 8-7. Autonegotiate Sink Minimum Power Example
ADCIN1 ADCIN2 Minimum Maximum ADCIN3 ADCIN4 Operating Maximum Minimum
Voltage Voltage Current Current Power

0 4 5V 15 V 3 1 3A 3A 15 W

0 6 5V 20 V 5 3 5A 5A 25 W

8.3.15 Extended Sink Capabilities Power Delivery Power

The Extend Sink Capabilities Power Delivery Power for Minimum, Operational, and Maximum PDP are
determined by the configured Maximum/Minimum Voltage Configuration and the Current Configuration.
Table 8-8. Extended Sink Capabilities Power Delivery Power Example
Power Delivery Power ADCIN3/4 = 3/3 ADCIN1/2 = 0/6

Minimum PDP = 25W Maximum Current = 5 A Minimum Voltage = 5 V

Operational PDP = 100W Maximum Current = 5 A Maximum Voltage = 20 V

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Table 8-8. Extended Sink Capabilities Power Delivery Power Example (continued)
Power Delivery Power ADCIN3/4 = 3/3 ADCIN1/2 = 0/6

Maximum PDP = 100W Maximum Current = 5 A Maximum Voltage = 20 V

8.4 Device Functional Modes

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8.4.1 Power States

The TPS25730 can operate in one of three different power states: Active, Idle, or Sleep. The Modern Standby
mode is a special case of the Idle mode. The functionality available in each state is summarized in Table
8-9. The device automatically transitions between the three power states based on the circuits that are active
and required. See Figure 8-26. In the Sleep state, the TPS25730 detects a Type-C connection. Transitioning
between the Active mode to Idle mode requires a period of time (T) without any of the following activity:
• Incoming USB PD message
• Change in CC status
• GPIO input event
• I2C transactions
• Voltage alert
• Fault alert

Sleep State
New No CC connection
activity
CC detached & No activity for T

New activity
Idle State
Active State
CC connected
CC attached &
No new activity for T

Figure 8-26. Flow Diagram for Power States

Table 8-9. Power Consumption States

MODERN STANDBY
ACTIVE SINK MODE(3) IDLE SINK MODE SLEEP MODE(1)
SINK MODE(2)
PP_HV (TPS25730D) enabled enabled disabled disabled
PP_EXT (TPS25730S) enabled enabled disabled disabled
external CC1 termination Rp 3.0A Rp 3.0A open open
external CC2 termination open open open open

(1) This mode is used for: IVIN_3V3,Sleep

(2) This mode is used for: PMstbySnk
(3) This mode is used for: IVIN_3V3,ActSnk

8.5 Schottky for Current Surge Protection

To prevent the possibility of large ground currents into the TPS25730 during sudden disconnects due to inductive
effects in a cable, TI recommends that a Schottky diode be placed from VBUS to ground.

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PPHV VBUS_IN

VBUS

GND

Figure 8-27. TPS25730D Schottky for Current Surge Protection

VBUS

GND

Figure 8-28. TPS25730S Schottky for Current Surge Protection

8.6 Thermal Shutdown

The TPS25730 features a central thermal shutdown as well as independent thermal sensors for each internal
power path. The central thermal shutdown monitors the overall temperature of the die and disables all functions
except for supervisory circuitry when die temperature goes above a rising temperature of TSD_MAIN. The
temperature shutdown has a hysteresis of TSDH_MAIN and when the temperature falls back below this value,
the device resumes normal operation.

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The TPS25730 is a stand-alone Type-C PD controller for sink power only USB-PD applications. The PD
controller is configured from with resistor pin strapping to set the appropriate voltage and current requirements.
There is no need for an external EEPROM, external microcontroller, or firmware development for a rapid barrel
jack to Type-C replacement
9.1.1 Supported Sink Power Configurations
The ADCINx pin configurations on the TPS25730 lets the user select the supported voltage and current range.
The following shows two sink configurations for the TPS25730.

System Input
Power 5V – 20V

Type C
Receptacle
VIN_3V3 System 3.3V (Optional)
VBUS

TPS25730S I2Ct External MCU

CC1/2 CC1/2
I/O ADINCx & Indicators

Figure 9-1. TPS25730S Sink Configuration

Type C
Receptacle
System Input
VBUS
Power 5V – 20V

CC1/2 CC1/2 TPS25730D VIN_3V3 System 3.3V (Optional)

I2Ct External MCU

I/O ADINCx & Indicators

Figure 9-2. TPS25730D Sink Configuration

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9.2 Typical Application Re vis ion His tory

9.2.1 Design Requirements Rev ECN # Approved Da te Approved by

N/A N/A N/A N/A

For barrel jack replacements applications, the TPS25730 is configured to negotiate a PD contract according to
the voltage required by the system. The TPS25730 supports 5V, 9V, 12V, 15V, and 20V up to 5A to replace a
barrel jack. Power is provided to the system through the power path on the PD controller.
9.2.2 Detailed Design Procedure
The ADCINx pin configurations on the TPS25730 lets the user select the supported voltage and current range.
The following shows an example schematic for the TPS25730 configured for 20 V at 3 A.
U1

38 10
VIN_3V3 VIN_3V3 DBG_ACC DBG_ACC
32-33 19
VBUS VBUS SINK_EN S INK_EN
C1 C2 C3 C4 C5
4.7uF 0.01uF 0.01uF 0.01uF 0.01uF 23-24-25 2
VBUS_IN ADCIN1 ADCIN1
3
ADCIN2 ADCIN2
5
ADCIN3 ADCIN3
7
ADCIN4 ADCIN4
GND
20-21-22
P P HV PPHV
28
C6 C7 C8 CC1 C_CC1
1 29
LDO_3V3 LDO_3V3 CC2 C_CC2
22uF 22uF 10uF 4
LDO_1V5 LDO_1V5
6 C9 C10
CAP_MIS CAP _MIS
330pF 330pF
GND 13
P LUG_FLIP PLUG_FLIP
37 15 DRAIN
P LUG_EVENT PLUG_EVENT DRAIN
30
DRAIN
18 40 GND
FAULT_IN FAULT_IN DRAIN_PAD
36
Res e rve d_36 Reserved
11
GND
9 12
I2Ct_S CL I2Ct_SCL GND
8 14
I2Ct_S DA I2Ct_SDA GND
16
GND
17
R1 R2 GND
31
3.3k 3.3k GND
26 34-35
Res e rve d_26 Reserved GND
27 39
Res e rve d_27 Reserved GND_PAD
LDO_3V3
TP S 25730D

GND

LDO_3V3 LDO_3V3 LDO_3V3 LDO_3V3

R5 R6 R7 R8
198.2k 9.4k 162k 190k
VIN_3V3 LDO_3V3 LDO_1V5

Res e rve d_26 Res e rve d_27 Res e rve d_36 ADCIN1 ADCIN2 ADCIN3 ADCIN4
C11 C12 C13
10uF 10uF 4.7uF R9 R10 R? R11 R12 R13 R14
10k 10k 10k 2.28k 191k 38k 9.5k

GND GND GND GND GND GND GND GND GND GND

Figure 9-3. TPS25730D Sink Example Schematic

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Product Folder Links: TPS25730

 N/A N/A N/A N/A

TPS25730
www.ti.com SLVSGP9 – OCTOBER 2023

P P HV A1 Q1 CS D87501L A2
VBUS
B1 B2
D1 D2
E1 E2

C1

C2
GATE_VS YS GATE_VBUS

U1

32 21 GATE_VBUS
VIN_3V3 VIN_3V3 GATE_VBUS
20 GATE_VS YS
GATE_VSYS
26
VBUS VBUS
27
C1 C2 C3 C4 C5 VBUS
10
DBG_ACC DBG_ACC
4.7uF 0.01uF 0.01uF 0.01uF 0.01uF P P HV 19
VSYS
18
SINK_EN S INK_EN
1
LDO_3V3 LDO_3V3
4
LDO_1V5 LDO_1V5
GND 2
ADCIN1 ADCIN1
3
ADCIN2 ADCIN2
13 5
P LUG_FLIP PLUG_FLIP ADCIN3 ADCIN3
31 7
P LUG_EVENT PLUG_EVENT ADCIN4 ADCIN4
17
FAULT_IN FAULT_IN
24
CC1 C_CC1
30 25
Res e rve d_30 Reserved CC2 C_CC2
9
I2Ct_S CL I2Ct_SCL C6 C7
8 6
I2Ct_S DA I2Ct_SDA CAP_MIS CAP _MIS
330pF 330pF
12
GND
11 14
GND GND
15
GND
16 GND
R1 R2 GND
GND 28
3.3k 3.3k GND
22 29
Res e rve d_22 Reserved GND
23 33
Res e rve d_23 Reserved GND
TP S 25730S
LDO_3V3

GND

LDO_3V3 LDO_3V3 LDO_3V3 LDO_3V3

R5 R6 R7 R8
198.2k 9.4k 162k 191k
VIN_3V3 LDO_3V3 LDO_1V5

Res e rve d_22 Res e rve d_23 Res e rve d_30 ADCIN1 ADCIN2 ADCIN3 ADCIN4
C8 C9 C10
10uF 10uF 4.7uF R9 R10 R3 R11 R12 R13 R14
10k 10k 10k 2.28k 191k 38k 9.5k

GND GND GND GND GND GND GND GND GND GND

Figure 9-4. TPS25730S Sink Example Schematic

9.2.3 Application Curves

The following figures show the GPIO, VBUS, CC1, CC2 and PPHV behavior for various conditions.

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Figure 9-5. PLUG_EVENT, PLUG_FLIP, DBG_ACC, and SINK_EN - CC1 Normal Orientation

Figure 9-6. PLUG_EVENT, PLUG_FLIP, DBG_ACC, and SINK_EN - CC2 Flipped Orientation

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Figure 9-7. PLUG_EVENT, PLUG_FLIP, DBG_ACC, and SINK_EN - Debug Accessory Detection

Figure 9-8. PLUG_EVENT, PLUG_FLIP, CAP_MIS, and SINK_EN - PD Contract w/ Capabilities Mismatch

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Figure 9-9. PLUG_EVENT, PLUG_FLIP, FAULT_IN, and SINK_EN - FAULT_IN Input

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Figure 9-10. 20V PD Contract VBUS & PPHV (1-VBUS, 2-CC1, 3-CC2, 4-PPHV)

9.3 Power Supply Recommendations

9.3.1 3.3-V Power
9.3.1.1 VIN_3V3 Input Switch
The VIN_3V3 input is the main supply of the TPS25730 device. The VIN_3V3 switch (see Power Management)
is a uni-directional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from LDO_3V3
to VIN_3V3. This switch is on when the 3.3-V supply is available and the dead-battery flag is cleared. The
recommended capacitance CVIN_3V3 (see Recommended Capacitance) must be connected from the VIN_3V3
pin to the GND pin).
9.3.2 1.5-V Power
The internal circuitry is powered from 1.5 V. The 1.5-V LDO steps the voltage down from LDO_3V3 to 1.5 V. The
1.5-V LDO provides power to all internal low-voltage digital circuits which includes the digital core, and memory.
The 1.5-V LDO also provides power to all internal low-voltage analog circuits. Connect the recommended
capacitance CLDO_1V5 (see Recommended Capacitance) from the LDO_1V5 pin to the GND pin.
9.3.3 Recommended Supply Load Capacitance
Recommended Capacitance lists the recommended board capacitances for the various supplies. The typical
capacitance is the nominally rated capacitance that must be placed on the board as close to the pin as possible.

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The maximum capacitance must not be exceeded on pins for which it is specified. The minimum capacitance is
minimum capacitance allowing for tolerances and voltage derating ensuring proper operation.
9.4 Layout
9.4.1 TPS25730D - Layout
9.4.1.1 Layout Guidelines
Proper routing and placement maintain signal integrity for high speed signals and improve the heat dissipation
from the power paths. The combination of power and high speed data signals are easily routed if the following Re vis ion His tory
guidelines are followed. Best practice is to consult with board manufacturing to verify manufacturing
Rev ECN # capabilities.
Approved Da te Approved by

N/A N/A N/A N/A

9.4.1.1.1 Top Placement and Bottom Component Placement and Layout
When the TPS25730 is placed on top and its components on bottom, the solution size is at its smallest.
9.4.1.2 Layout Example
Follow the differential impedances for Super / High Speed signals defined by their specifications (USB2.0). All
I/O are fanned out to provide an example for routing out all pins, not all designs utilize all of the I/O on the
TPS25730.
U1

38 10
VIN_3V3 VIN_3V3 DBG_ACC DBG_ACC
32-33 19
VBUS VBUS SINK_EN S INK_EN
C1 C2 C3 C4 C5
4.7uF 0.01uF 0.01uF 0.01uF 0.01uF 23-24-25 2
VBUS_IN ADCIN1 ADCIN1
3
ADCIN2 ADCIN2
5
ADCIN3 ADCIN3
7
ADCIN4 ADCIN4
GND
20-21-22
P P HV PPHV
28
C6 C7 C8 CC1 C_CC1
1 29
LDO_3V3 LDO_3V3 CC2 C_CC2
22uF 22uF 10uF 4
LDO_1V5 LDO_1V5
6 C9 C10
CAP_MIS CAP _MIS
330pF 330pF
GND 13
P LUG_FLIP PLUG_FLIP
37 15 DRAIN
P LUG_EVENT PLUG_EVENT DRAIN
30
DRAIN
18 40 GND
FAULT_IN FAULT_IN DRAIN_PAD
36
Res e rve d_36 Reserved
11
GND
9 12
I2Ct_S CL I2Ct_SCL GND
8 14
I2Ct_S DA I2Ct_SDA GND
16
GND
17
R1 R2 GND
31
3.3k 3.3k GND
26 34-35
Res e rve d_26 Reserved GND
27 39
Res e rve d_27 Reserved GND_PAD
LDO_3V3
TP S 25730D

GND

LDO_3V3 LDO_3V3 LDO_3V3 LDO_3V3

R5 R6 R7 R8
198.2k 9.4k 162k 190k
VIN_3V3 LDO_3V3 LDO_1V5

Res e rve d_26 Res e rve d_27 Res e rve d_36 ADCIN1 ADCIN2 ADCIN3 ADCIN4
C11 C12 C13
10uF 10uF 4.7uF R9 R10 R? R11 R12 R13 R14
10k 10k 10k 2.28k 191k 38k 9.5k

GND GND GND GND GND GND GND GND GND GND

Figure 9-11. Example Schematic

9.4.1.3 Component Placement

Top and bottom placement is used for this example to minimize solution size. The TPS25730D is placed on
the top side of the board and the majority of its components are placed on the bottom side. When placing the
components on the bottom side, TI recommends that they are placed directly under the TPS25730D. When
placing the VBUS and PPHV capacitors, it is easiest to place them with the GND terminal of the capacitors to
face outward from the TPS25730D or to the side because the drain connection pads on the bottom layer must
not be connected to anything and left floating. All other components that are for pins on the GND pad side of the
TPS25730D must be placed where the GND terminal is underneath the GND pad.

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The CC capacitors must be placed on the same side as the TPS25730D close to the respective CC1 and CC2
pins. Do NOT via to another layer in between the CC pins to the CC capacitor, placing a via after the CC
capacitor is recommended.
Figure 9-12 through Figure 9-13 show the placement in 2-D and 3-D.

Figure 9-12. Top View Layout Figure 9-13. Bottom View Layout

Figure 9-14. Top View 3-D

Figure 9-15. Bottom View 3-D

9.4.1.4 Routing VBUS, VIN_3V3, LDO_3V3, LDO_1V5

On the top side, create pours for VBUS, VBUS_IN, and PPHV. Connect VBUS from the top layer to the bottom
layer using at least 6 8-mil hole and 16-mil diameter vias. See Figure 9-16 for the recommended via sizing. For
VBUS_IN and PPHV, connect from the top to bottom layer using 15 8-mil hole and 16-mil diameter vias. The via
placement and copper pours are highlighted in Figure 9-17.

Figure 9-16. Recommended Minimum Via Sizing

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Figure 9-17. VBUS, VBUS_IN, and PPHV Copper Pours and Via Placement

Next, VIN_3V3, LDO_3V3, and LDO_1V5 route to their respective decoupling capacitors. Additionally, a copper
pour on the bottom side is added to connect PPHV to their decoupling capacitors located on the bottom of the
PCB. This action is highlighted in Figure 9-18.

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Figure 9-18. VIN_3V3, LDO_3V3, and LDO_1V5 Routing

9.4.1.5 Routing CC and GPIO

Routing the CC lines with a 10-mil trace ensures the needed current for supporting powered Type-C cables
through VCONN. For more information on VCONN refer to the Type-C specification. For capacitor GND pin use
a 16-mil trace if possible.
Most of the GPIO signals can be fanned out on the top or bottom layer using either a 8-mil or 10-mil trace. The
following images highlights how the CC lines and GPIOs are routed out.

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Figure 9-19. Top Layer GPIO Routing

Table 9-1. Routing Widths

ROUTE WIDTH (MIL MINIMUM)
CC1, CC2 8
VIN_3V3, LDO_3V3, LDO_1V8 8
Component GND 10
GPIO 8

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9.4.2 TPS25730S - Layout

9.4.2.1 Layout Guidelines
Proper routing and placement maintain signal integrity for high speed signals and improve the heat dissipation
from the power paths. The combination of power and high speed data signals are easily routed if the following
guidelines are followed. Best practice is to consult with board manufacturing to verify manufacturing capabilities.
Re vis ion His
9.4.2.1.1 Top Placement and Bottom Component Placement and Layout Rev ECN # Approved Da te Approved by

When the TPS25730 is placed on top and its components on bottom, the solution size is at its smallest.
N/A N/A N/A N/A

9.4.2.2 Layout Example

Follow the differential impedances for Super / High Speed signals defined by their specifications (USB2.0). All
I/O are fanned out to provide an example for routing out all pins, not all designs utilize all of the I/O on the
TPS25730S.
P P HV A1 Q1 CS D87501L A2
VBUS
B1 B2
D1 D2
E1 E2
C1

C2

GATE_VS YS GATE_VBUS

U1

32 21 GATE_VBUS
VIN_3V3 VIN_3V3 GATE_VBUS
20 GATE_VS YS
GATE_VSYS
26
VBUS VBUS
27
C1 C2 C3 C4 C5 VBUS
10
DBG_ACC DBG_ACC
4.7uF 0.01uF 0.01uF 0.01uF 0.01uF P P HV 19
VSYS
18
SINK_EN S INK_EN
1
LDO_3V3 LDO_3V3
4
LDO_1V5 LDO_1V5
GND 2
ADCIN1 ADCIN1
3
ADCIN2 ADCIN2
13 5
P LUG_FLIP PLUG_FLIP ADCIN3 ADCIN3
31 7
P LUG_EVENT PLUG_EVENT ADCIN4 ADCIN4
17
FAULT_IN FAULT_IN
24
CC1 C_CC1
30 25
Res e rve d_30 Reserved CC2 C_CC2
9
I2Ct_S CL I2Ct_SCL C6 C7
8 6
I2Ct_S DA I2Ct_SDA CAP_MIS CAP _MIS
330pF 330pF
12
GND
11 14
GND GND
15
GND
16 GND
R1 R2 GND
GND 28
3.3k 3.3k GND
22 29
Res e rve d_22 Reserved GND
23 33
Res e rve d_23 Reserved GND
TP S 25730S
LDO_3V3

GND

LDO_3V3 LDO_3V3 LDO_3V3 LDO_3V3

R5 R6 R7 R8
198.2k 9.4k 162k 191k
VIN_3V3 LDO_3V3 LDO_1V5

Res e rve d_22 Res e rve d_23 Res e rve d_30 ADCIN1 ADCIN2 ADCIN3 ADCIN4
C8 C9 C10
10uF 10uF 4.7uF R9 R10 R3 R11 R12 R13 R14
10k 10k 10k 2.28k 191k 38k 9.5k

GND GND GND GND GND GND GND GND GND GND

Figure 9-20. Example Schematic

9.4.2.3 Component Placement

Top and bottom placement is used for this example to minimize solution size. The TPS25730S is placed on
the top side of the board and the majority of its components are placed on the bottom side. When placing the
components on the bottom side, TI recommends that they are placed directly under the TPS25730S. All other
components that are for pins on the GND pad side of the TPS25730S must be placed where the GND terminal is
underneath the GND pad.

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The CC capacitors must be placed on the same side as the TPS25730S close to the respective CC1 and CC2
pins. Do NOT via to another layer in between the CC pins to the CC capacitor, placing a via after the CC
capacitor is recommended.
Figure 9-21 through Figure 9-22 show the placement in 2-D and 3-D.

Figure 9-21. Top View Layout Figure 9-22. Bottom View Layout

Figure 9-24. Bottom View 3-D

Figure 9-23. Top View 3-D

9.4.2.4 Routing VBUS, PPHV, VIN_3V3, LDO_3V3, LDO_1V5

On the top side, create pours for VBUS, and PPHV. Connect PPHV from the top layer to the bottom layer
using at least 12, 8-mil hole and 16-mil diameter vias. See Figure 9-25 for the recommended via sizing. The via
placement and copper pours are highlighted in Figure 9-26.

Figure 9-25. Recommended Minimum Via Sizing

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Figure 9-26. VBUS Copper Pours and Via Placement

Next, VIN_3V3, LDO_3V3, and LDO_1V5 are routed to their respective decoupling capacitors. This action is
highlighted in Figure 9-27.

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Figure 9-27. VIN_3V3, LDO_3V3, and LDO_1V5 Routing

Figure 9-28 and Figure 9-29 show how to properly connect VSYS and the SYS_Gate control signals for the
external N-FETs. The control signals can be routed on an internal layer using a 12-mil trace, and the trace going
to VSYS must be as short as possible to minimize impedance, so placing a via directly on the high-voltage
power path is ideal.

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Figure 9-29. Bottom Polygon Pours

Figure 9-28. Top Polygon Pours

9.4.2.5 Routing CC and GPIO

Routing the CC lines with a 10-mil trace ensures the needed current for supporting powered Type-C cables
through VCONN. For more information on VCONN refer to the Type-C specification. For capacitor GND pin use
a 16-mil trace if possible.
Most of the GPIO signals can be fanned out on the top or bottom layer using either a 8-mil trace or a 10-mil
trace. The following images highlight how the CC lines and GPIOs are routed out.

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Figure 9-30. Top Layer GPIO Routing

Table 9-2. Routing Widths

ROUTE WIDTH (MIL MINIMUM)
PA_CC1, PA_CC2, PB_CC1, PB_CC2 8
VIN_3V3, LDO_3V3, LDO_1V8 6
Component GND 10
GPIO 4

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10 Device and Documentation Support

10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.2 Documentation Support
10.2.1 Related Documentation
• USB-PD Specifications
• USB Power Delivery Specification
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
10.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
October 2023 * Initial Release

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 59

Product Folder Links: TPS25730
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Nov-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS25730DREFR ACTIVE WQFN REF 38 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 25730D Samples
BH
TPS25730SRSMR ACTIVE VQFN RSM 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 25730S Samples
BH

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Nov-2023

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Dec-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS25730DREFR WQFN REF 38 3000 330.0 12.4 4.3 6.3 1.1 8.0 12.0 Q2
TPS25730SRSMR VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS25730DREFR WQFN REF 38 3000 367.0 367.0 35.0
TPS25730SRSMR VQFN RSM 32 3000 367.0 367.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RSM 32 VQFN - 1 mm max height
4 x 4, 0.4 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224982/A

www.ti.com
 PACKAGE OUTLINE
RSM0032B SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4.1 B
A 0.45
3.9
0.25

0.25
0.15
PIN 1 INDEX AREA DETAIL
OPTIONAL TERMINAL
4.1 TYPICAL
3.9

(0.1)

SIDE WALL DETAIL

OPTIONAL METAL THICKNESS
1 MAX C

SEATING PLANE
0.05
0.08 C
0.00 2.8 0.05

2X 2.8
(0.2) TYP
4X (0.45)
9 16
28X 0.4
8 SEE SIDE WALL
17 DETAIL

EXPOSED
THERMAL PAD

2X SYMM
33
2.8

24 0.25
1 32X
SEE TERMINAL 0.15
DETAIL 0.1 C A B
PIN 1 ID 32 25 0.05
SYMM
(OPTIONAL) 0.45
32X
0.25

4219108/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RSM0032B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 2.8)

SYMM
32 25

32X (0.55)

1
32X (0.2) 24

( 0.2) TYP (1.15)

VIA

SYMM 33
(3.85)

28X (0.4)

8 17

(R0.05)
TYP

9 16
(1.15)

(3.85)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

METAL SOLDER MASK

EXPOSED METAL OPENING
EXPOSED METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK

NON SOLDER MASK

DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

4219108/B 08/2019
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RSM0032B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(0.715)
4X ( 1.23)
32 25 (R0.05) TYP

32X (0.55)

1
32X (0.2) 24

(0.715)
SYMM 33
(3.85)

28X (0.4)

8 17

METAL
TYP 9 16
SYMM

(3.85)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 33:

77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4219108/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
REF0038A SCALE 2.800
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

6.1 B
A
5.9

0.45
4.1 0.25
PIN 1 INDEX AREA
3.9

0.25
0.15

DETAIL A
TYPICAL

0.8
0.7
C

SEATING PLANE
0.05
0.00 0.08 C

2X 4.8
2.82 1.63
2.62 1.43 (0.2)
7 19 TYP
EXPOSED
THERMAL PAD
30X 0.4 20
6

4X 0.45
2 SYMM 2.2
39 40
2.75
2X
2.55

1
SEE DETAIL A 25
0.25
38X
0.15
38 26 0.07 C A B
PIN 1 ID 4X 0.965 1.56
(0.2) 0.05
(45 X 0.3) 0.45
38X
0.25
PKG

4226763/C 11/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
REF0038A WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(2.72)

SOLDER MASK
OPENING (1.53)
38 26

30X (0.55) 4X (0.2)

1 25

38X (0.2) 2X
39 40 (1.075)
SYMM 2X (3.85)
(2.65)

4X
(0.45)
30X (0.4)
6
20

(R0.05) TYP

( 0.2) TYP
VIA
METAL UNDER
7 19 SOLDER MASK
(0.965) (0.145) 2X (0.55)
(2.075) (1.56)
(2.925) (3.2)

PKG

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL
EXPOSED METAL OPENING

EXPOSED METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
PADS 20-25 & 32-35

SOLDER MASK DETAILS

NOT TO SCALE
4226763/C 11/2021

NOTES: (continued)

4. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
REF0038A WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

METAL UNDER
SOLDER MASK

PKG
4X (1.19) 2X (1.4)
(R0.05) TYP 38 26

30X (0.55) 4X (0.2)

1
25

38X 6X
(0.2) 39 40 (1.17)
4X
(0.45)
SYMM

(3.85)
6X
(0.69)
30X
(0.4)
6 20

2X (0.55)
METAL
TYP

7 19
2X (0.27)
2X (1.66) 2X (1.56)

(2.925) (3.2)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PADS 39
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

EXPOSED PADS 40
80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4226763/C 11/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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