Digital Control IC
for Interleaved PFCs
Rosario Attanasio
Applications Manager
STMicroelectronics
Presentation Outline 2
• PFC Basics
• Interleaved PFC Concept
• Analog Vs Digital Control
• The STNRGPF01 Digital Controller
• Main Functions
• Edesign suite GUI
• Application Example:
• 3kW Three channel Interleaved PFC
• Performance Evaluation
• Conclusions
Power Factor Correction 5
A PFC is the input stage of an AC/DC converter connected to the AC mains to
address the need to limit energy consumption
A PFC pre-regulator placed between the bridge and the bulk capacitor draws a
quasi-sinusoidal current from the mains, in-phase with the line voltage
Harmonic current emission is regulated by IEC 61000-3-2.
Lighting requirements > 25W, SMPS & chargers > 75W
Maximize the energy delivery to load means to reduce the Total Harmonic
Distortion (THD) and therefore maximize the Power Factor
Introduction to PFC 4
Kd= Distortion Factor
Kϴ= Displacement Factor
Passive vs Active PFC 5
EMI Main
Rectifier PFC Load
Filter Converter
SMPS Structure
• PFC stage can be “Passive” or “Active”.
• Passive: bulky capacitors and inductors
• Active: high frequency topologies
Passive PFC Topologies 6
AC side inductor PR Bandstop filter
DC side inductor Harmonic Trap filter
SR Bandpass filter LCD Rectifier
Active PFC Topologies 7
• Main topologies for PFC stage:
• Boost (most used because it’s stepping-up the voltage)
• Buck
• Flyback
• Cuk
• Sepic
• Operation modes:
• Continuous Conduction Mode (CCM) > 350W
• Transition Mode (TM) <350W
• Discontinuous Conduction Mode (DCM)
PFC – Control Technique 8
Type Strengths Weakness
Average current control Low distortion on input current Two control loops
Peak Current control Fast current correction High distortion on input current
Fast current correction
Hysteresis Current control Need two comparators
Low distortion on input current
PFC – Interleaved Concept 9
I1
L1
DC/DC
Load
M1
+ or
PFC
controller
Ic DC/AC
Phase1
In
LN
Mn
Phase n
Example: 3kW iPFC 10
Switching frequency 100kHz
Single Channel
Interleaved 3 Channels
Core: EE70 Core: PQ3230
L= 150µH L= 120µH
Size: h=70mm, W=66mm, D=31mm Size: h=30mm, W=32mm, D=27mm
Volume=8.72 in3 Volume=1.58 in3
Total Volume=4.74 in3
45% Less!
Output Capacitor Ripple Current Reduction 11
RMS Current Reduction
Single Channel
I 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁𝑁 Double Channel
0.5
Triple Channel
0
0 0.5 1
%D
Capacitors with higher ESR can be used Lower cost
Digital vs Analog PFC Control 12
• Full digital control of PFC is • Availability of ICs for PFCs from
already state of the art. many manufacturers
• More PFC topologies can be implemented • Cycle by cycle control loop
• High bandwidth
• More sophisticated control algorithms
• Low Cost
Digital Control Analog Control
The STNRGPF01: Overview 13
• TSSOP38 Package
• Mixed Signal Control
• Configurable By GUI
The STNRGPF01: Overview 14
• Semi-digital control
• Analog current controller
• Voltage controller, feed-forward compensation, multiplier, PWM clock generator and non-
time critical protection functions are implemented digitally.
• Interleaved boost PFC
• Up to 3 interleaved channels
• CCM, fixed frequency
• Average current control, cycle-by-cycle
• Inrush current control
• Burst mode support
• OCP, OVP and thermal protection
• Soft start-up
• Flexible phase-shedding strategy
STRNGPF01: Application Block Diagram 15
STNRGPF01: Voltage Loop 16
• Output Voltage Sensing Internal control block scheme
• Input Voltage Sensing
• Output Current Sensing
• ZVD Sensing
STNRGPF01: Current Loop 17
Analog Current OP-Amp PI Internal control block scheme
Itot_ref
Itot_fb
STNRGPF01: Driving and Interleaving 18
Interleaving operation (internal) Internal control block scheme
STNRGPF01 GUI: eDesign Suite Tool 19
BoM + SCHEMATIC
Binary file generation Build
eDesignSuite smart configurator for STNRGPF01
3kW Three Channels Interleaved PFC 20
The device performance have been evaluated developing a 3kW Three channels PFC.
• Pout = 3kW @ Vin = 230Vac; 1.5kW @ Vin = 110Vac • Load feed forward
• Vout = 400V • Working frequency = 111kHz per channel
• PF > 0.98 @ 20% load • Thermal protection set at 120°C
• THD < 5% @ 20% load • Current protection set at 33A
• CCM with analog current control loop • Direct fan driving
(cycle by cycle regulation) • Current reference realized by internal map (200 pt)
• Input Voltage feed forward
High Power Density
52W/in3!
Key Products
• STNRGPF01 (Digital controller for PFC)
• PM8834D (Double Channel low side driver)
• ALTAIR05-800 (Off-line primary-sens. switch. reg.)
• STW40N60M2 (MDmesh II Plus low Qg )
• STPSC1206 Schottky silicon carbide diode
• TSV911 (High speed OP)
• LMV358 (Standard OP)
• M74HC132 (Quad NAND Gate)
L=24,5 cm; W=11 cm; H=3,5 cm (including heatsink area)
Experimental Results: Steady State 21
Inductors current Duty cycle
PWM master
Experimental Results: Load Feed Forward 22
Load step : 0W - 2kW
DC Bus voltage
Input current
The load feed forward when load step is applied reduces the over and
under voltage of the output dc bus voltage!
Experimental Results: Load Feed Forward 23
Load step sequence: 0.4kW - 2kW - 0.4kW
DC Bus voltage
Input current
The load feed forward when load step is applied reduces the over and
under voltage of the output dc bus voltage!
Experimental Results: Load Feed Forward 24
Load step sequence: 0W - 2kW - 0W
DC Bus voltage
Input current
The PFC interrupts the Burst Mode to meet the load requirement and
when load is disconnected it returns in Burst Mode.
Experimental Results 25
Efficiency and ITHD%
Conclusions 26
• Interleaved PFC benefits include: the use of smaller
components, better thermal performance, low current ripple
• The STNRGPF01 is a controller for CCM interleaved PFCs
• It supports up to three independent channels
• Cycle by Cycle current control allows fast dynamic response
• The STNRGPF01 can be easily and quickly configured using
the eDesign Suite GUI resulting in reduced development
time, lower development cost and faster time-to-market
27
Thank You!
