Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-1

LECTURE 30 – LOW VOLTAGE OP AMPS

LECTURE ORGANIZATION
Outline
• Introduction
• Low voltage input stages
• Low voltage gain stages
• Low voltage bias circuits
• Low voltage op amps
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
Pages 419-436

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Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-2

INTRODUCTION
Implications of Low-Voltage, Strong-Inversion Operation
• Reduced power supply means decreased dynamic range
• Nonlinearity will increase because the transistor is working close to VDS(sat)
• Large values of  because the transistor is working close to VDS(sat)
• Increased drain-bulk and source-bulk capacitances because they are less reverse biased.
• Large values of currents and W/L ratios to get high transconductance
• Small values of currents and large values of W/L will give small VDS(sat)
• Severely reduced input common mode range
• Switches will require charge pumps

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-3

What are the Limits of Power Supply?

The limit comes when there is no signal range left when the dc drops are subtracted from
VDD. VDD
Minimum power supply (no signal swing range): + +
VPB1 M2 M3
VON
VT+VON
- -
VDD(min.) = VT + 2VON + V +
NB1
VON VT+VON
M1 - M4 -
For differential amplifiers, the minimum power 060802-01

supply is:
VDD
VDD(min.) = 3VON M3 M4 +
However, to have any input common mode range, the VPB1 VON
-
effective minimum power supply is, M1 + M2
VDD(min.) = VT + 2VON VON
+ +
VT+VON - VT+VON
- -
M5 +
VNB1 VON
-
060802-02

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Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-4

Minimum Power Supply Limit – Continued

The previous consideration of the differential amplifier did not consider getting the
signal out of the amplifier. This will add another VON.
VDD
M3 M4 +
VPB1 VON VPB1 M9
-
M1 +M2 V M6 +
PB2
VON VON
+ + -
VT+VON - VT+VON
- -
M5 + + VT
VNB1 VON VT+VON
- - M7
M8
060802-03

Therefore,
VDD(min.) = VT + 3VON
This could be reduced to 3VON with the floating battery but its implementation probably
requires more than 3VON of power supply.
Note the output signal swing is VT + VON while the input common range is VON.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-5

LOW VOLTAGE INPUT STAGES

Input Common Mode Voltage Range
Minimum power supply (ICMR = 0): VDD
+
VBias
VDD(min) = VSD3(sat)-VT1+VGS1+VDS5(sat) V (sat) -
SD3
= VSD3(sat)+VDS1(sat)+VDS5(sat) M3 M4

-VT1
Input common-mode range: vicm M1 M2
Vicm(upper) = VDD - VSD3(sat) + VT1 VGS1
Vicm(lower) = VDS5(sat) + VGS1
VDS5(sat) +
VBias M5
-
Fig. 7.6-3
If the threshold magnitudes are 0.7V, VDD =
1.5V and the saturation voltages are 0.3V, then
Vicm(upper) = 1.5 - 0.3 + 0.7 = 1.9V
and
Vicm(lower) = 0.3 + 1.0 = 1.3V
giving an ICMR of 0.6V.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-6

Increasing ICMR using Parallel Input Stages VDD

Turn-on voltage for the n-channel input: M6 MN3 MP5

MN4

Vonn = VDSN5(sat) + VGSN1

Turn-on voltage for the p-channel input: IBias
Vicm
MP1 MP2
Vicm

Vonp = VDD - VSDP5(sat) - VSGP1 MN1 MN2

The sum of Vonn and Vonp equals the minimum

M7 MP4
power supply. MP3 MN5
Regions of operation: Fig. 7.6-4

VDD > Vicm > Vonp: (n-channel on and p-channel off) gm(eq) = gmN
Vonp  Vicm  Vonn: (n-channel on and p-channel on) gm(eq) = gmN + gmP
Vonn > Vicm > 0 : (n-channel off and p-channel on) gm(eq) = gmP
where gm(eq) is the equivalent input transconductance of the above input stage, gmN is
the input transconductance for the n-channel input and gmP is the input trans-
conductance for the p-channel input.
gm(eff)
gmN+gmP

gmP gmN
n-channel off Vonn n-channel on Vonp n-channel on
p-channel on p-channel on p-channel off
Vicm
0 VSDP5(sat)+VGSN1 VDD-VSDP5(sat)+VGSN1 VDD Fig. 7.6-5
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-7

Removing the Nonlinearity in Transconductances as a Function of ICMR

Increase the bias current in the differential VDD
3:1
amplifier that is on when the other differential Ib
amplifier is off.
Three regions of operation depending on the Inn Ip
VB2 Vicm MP1 MP2 Vicm VB1
value of Vicm:
MB2 MB1
1.) Vicm < Vonn: n-channel diff. amp. off MN1 MN2

and p-channel on with Ip = 4Ib: In Ipp

KP’WP
gm(eff) = LP 2 Ib Ib
1:3
Fig. 7.6-6
2.) Vonn < Vicm < Vonp: both on with
In = Ip = Ib
KN’WN KP’WP
gm(eff) = Ib + Ib
LN LP
3.) Vicm > Vonp: p-channel diff. amp. off and n-channel on with In = 4Ib:
KN’WN
gm(eff) = LN 2 Ib
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-8

How Does the Current Compensation Work?

Set VB1 = Vonn and VB2 = Vonp.
VDD
If vicm <Vonp then Ip = Ib and Inn=0
Ib
vicm vicm If vicm >Vonp then Ip = 0 and Inn=Ib
MB1
Inn Ip
MN1 MN2
Vonn
In Ipp vicm MP1 MP2 v
icm
MB2
If vicm >Vonn then In = Ib and Ipp=0
Ib Vonp
If vicm <Vonn then In = 0 and Ipp=Ib
Fig. 7.6-6A
Result: gm(eff)

gmN=gmP

0 Vicm
0 Vonn Vonp VDD Fig. 7.6-7

The above techniques and many similar ones are good for power supply values down to
about 1.5V. Below that, different techniques must be used or the technology must be
modified (natural devices).
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-9

Natural Transistors
Natural or native NMOS transistors normally have a threshold voltage around 0.1V
before the threshold is increased by increasing the p concentration in the channel.
If these transistors are characterized, then they provide a means of achieving low voltage
operation.
Minimum power supply (ICMR = 0):
VDD(min) = 3VON
Input common mode range:
Vicm(upper) = VDD – VON + VT(natural)
Vicm(lower) = 2VON + VT(natural)
If VT(natural) ≈ VON = 0.1V, then
Vicm(upper) = VDD
Vicm(lower) = 3VON = 0.3V
Therefore,
ICMR = VDD - 3VON = VDD – 0.3V  VDD(min) ≈ 1V
Matching tends to be better (less doping and magnitude is smaller).
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-10

Bulk-Driven MOSFET
A depletion device would permit large ICMR even with very small power supply
voltages because VGS is zero or negative.
When a MOSFET is driven from the bulk with the gate held constant, it acts like a
depletion transistor.
Cross-section of an n-channel vBS VDS VGS VDD
bulk-driven MOSFET: Bulk Drain Gate Source Substrate

Channel
p+ n+ n+ n+
QP
Depletion p-well
Region QV

n substrate
Large signal equation: Fig. 7.6-8

KN’W
iD = 2L VGS - VT0 -  2|F| - vBS +  2|F|2
Small-signal transconductance:
 (2KN’W/L)ID
gmbs =
2 2|F| - VBS
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-11

Bulk-Driven MOSFET - Continued

Transconductance characteristics: 2000
Bulk-source driven

Drain Current (mA)

1500

1000
Saturation: VDS > VBS – VP gives,
VBS = VP + VON 500
IDSS
Gate-source
 VBS2
iD = IDSS 1 - V  driven
 P 0
-3 -2 -1 0 1 2 3
Comments: Gate-Source or Bulk-Source Voltage (Volts)
Fig. 7.6-9

• gm (bulk) > gm(gate) if VBS > 0 (forward biased )

• Noise of both configurations are the same (any differences comes from the gate versus
bulk noise)
• Bulk-driven MOSFET tends to be more linear at lower currents than the gate-driven
MOSFET
• Very useful for generation of IDSS floating current sources.

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Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-12

Bulk-Driven, n-channel Differential Amplifier

What is the ICMR?
Vicm(min) = VSS + VDS5(sat) + VBS1 = VSS + VDS5(sat) - |VP1| + VDS1(sat)
Note that Vicm can be less than VSS if |VP1| > VDS5(sat) + VDS1(sat)
Vicm(max) = ?
VDD
As Vicm increases, the current through M3 M4
M1 and M2 is constant so the source M7
increases. However, the gate voltage stays
constant so that VGS1 decreases. Since the vi1 vi2
current must remain constant through M1 IBias + + +
V
VBS1 M1 GS V
and M2 because of M5, the bulk-source - - M2 -BS2
voltage becomes less negative causing VTN1
M6 M5
to decrease and maintain the currents
through M1 and M2 constant. If Vicm is
VSS Fig. 7.6-10
increased sufficiently, the bulk-source
voltage will become positive. However, current does not start to flow until VBS is
greater than 0.3 volts so the effective Vicm(max) is
Vicm(max)  VDD - VSD3(sat) - VDS1(sat) + VBS1.
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Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-13

Illustration of the ICMR of the Bulk-Driven, Differential Amplifier

250nA

200nA

Bulk-Source Current
150nA

100nA

50nA

-50nA
-0.50V -0.25V 0.00V 0.25V 0.50V
Input Common-Mode Voltage Fig. 7.6-10A
Comments:
• Effective ICMR is from VSS to VDD -0.3V
• The transconductance of the input stage can vary as much as 100% over the ICMR
which makes it very difficult to compensate
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-14

Reduction of VT through Forward Biasing the Bulk-Source

The bulk can be used to reduce the threshold sufficiently to permit low voltage
applications. The key is to control the amount of forward bias of the bulk-source.
Current-Driven Bulk Technique†:
S S Gate
IE p+ p+
B B
G G
n+
D ICD ICS
D Source Drain
IBB IBB
n-well
p- substrate
Reduced Threshold MOSFET Parasitic BJT Layout Fig. 7.6-19
Problem:
Want to limit the BJT current to some value called, Imax.
Therefore,
Imax
IBB =
CS + CD + 1

†T. Lehmann and M. Cassia, “1V Power Supply CMOS Cascode Amplifier,” IEEE J. of Solid-State Circuits, Vol. 36, No. 7, 2001.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-15

VDD
Current-Driven Bulk Technique
Bias circuit for keeping Imax defined VBias1
M7
independent of BJT betas. M3
IS,E =1.3ID
Note:
ID,C = ICD + ID M6 ID IE IR

IS,E = ID + IE + IR R
IBB M1 M2
The circuit feedback causes a bulk bias ID,C =1.1ID ICD M5
M4
current IBB and hence a bias voltage VBIAS M8 +
such that VBias
IR =
IS,E = ID + IBB(1+CS + CD) + IR VBias2
0.1ID
-
Use VBias1 and VBias2 to set ID,C  1.1ID, VSS
130418-01

IS,E  1.3ID and IR  0.1ID which sets IBB at 0.1ID assuming we can neglect ICS with
respect to ICD. This is illustrated as follows,
IS,E ≈ ID + IBB(1+CD) + IR = ID + IBB + ICD + IR = ID + IBB + 0.1ID + 0.1ID = 1.3ID
For this circuit to work, the following conditions must be satisfied:
VBE < VTN + IRR and |VTP| + VDS(sat) < VTN + IRR
If |VTP| > VTN, then the level shifter IRR can be eliminated.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-16

LOW VOLTAGE GAIN STAGES

Cascade Stages
Simple cascade of inverters:
VDD
VPB1 M2 M3
VPB1 M5 M7

-gm1 -gm2 -gm3 -gm4

VNB1 VNB1
R1 R2 R3 R4
M1 M4 M6 M8
060803-01

The problem with this approach is the number of poles that occur (one per stage) if the
amplifier is to be used in a closed loop application. Instability or poor transient response
will result.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-17

Nested Miller Compensation

Cm3
Principle: Use Miller compensation
to split the poles within a feedback Cm2 Cm1
loop.
p1 p2 p3 p4 vout
Compensating Results: vin -g m1 -gm2 -gm3 -gm4
1) Cm1 pushes p4 to higher R1 R2 R3 RL CL
frequencies and p3 down to lower
060812-01
frequencies
2) Cm2 pushes p2 to higher frequencies and p1 down to lower frequencies
3) Cm3 pushes p3 to higher frequencies (feedback path) & pulls p1 further to lower
frequencies
Equations:
GB  gm1/C m3 p2  gm2/Cm3 p3  gm3Cm3/(Cm1Cm2) p4  gm4/CL
The objective is to get all poles larger than GB:
GB < p2, p3, p4

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Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-18

Illustration of the Nested Miller Compensation Technique

This approach is complicated by the feedforward paths which create RHP zeros.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-19

Elimination of the RHP Zeros

The following are least three ways in which the RHP zeros can be eliminated.
1.) Nulling resistor. 2.) Feedback only – buffer. 3.) Feedback only – gain.

VDD VDD VDD VDD VDD

VPB1 VPB1 VPB1 M3

M2 M2 M2
Cc1
Cc1 VPB2
Cc1
M3 M4
Rz1
M1 M1 VNB1 M1
VPN1 M5
060803-02
060803-04
060803-03

1 Increases the minimum power Increases the pole and

z1 =
Cc1(1/gm1 − Rz1) supply by VON. increases the minimum
power supply by VON.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-20

Use of LHP Zeros to Compensate Cascaded Amplifiers

Principle: Feedforward around a noninverting stage creates a LHP zero or inverting
feedforward around an inverting stage also creates a LHP zero.
Example of Multipath, Nested Miller Compensation†:
CM2 VDD
CM1 VPB1M5 M6 M11 M14

Vin Vout Vout

+gm1 +gm2 -gm3 CM1
CM2
R1 R3 C3 M13 C3
Vin
M9 M10
M1 M3 VRef2
+gm4 M4 M2
VRef1
VNB1
R2,4 M12
060803-05 M7 M8

Unfortunately, the analysis becomes quite complex - for the details refer to the reference
below.

† R. Hogervorst and J. H. Huijsing, Design of Low-Voltage, Low-Power Operational Amplifier Cells, Kluwer Academic Publishers, 1996, pp. 127-
131.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-21

LOW VOLTAGE BIAS CIRCUITS

A Low-Voltage Current Mirror with Wide Input and Output Swings
The current mirror below requires a power supply of VT+3VON and has a Vin(min) =
VON and a Vout(min) = 2VON (less for the regulated cascode output mirror).

VDD VDD

I1-IB IB IB I2 I1 IB1 IB2 IB1 I2

iin iout iin iout

M7
M3 M4 M7 M3 M4
or
M6 M6 M5

M1 M2 M1
M5 IB2 M2

Fig. 7.6-13A

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Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-22

Low-Voltage Current Mirrors using the Bulk-Driven MOSFET

The biggest problem with current mirrors is the large minimum input voltage required
for previously examined current mirrors.
If the bulk-driven MOSFET is biased with a current that exceeds IDSS then it is
enhancement and can be used as a current
mirror.
VDD VDD

iin iin iout

M4
iout M3
+ + +
VGS3 VBS3 VGS4
- -M2
M1 M2 - M1
+ + + + + +
VGS V BS VGS VGS1 VBS1 VGS2
- - - - - -
Simple bulk-driven Cascodebulk-driven
current mirror current mirror. Fig.7.6-11
The cascode current mirror gives a minimum input voltage of less than 0.5V for currents
less than 100µA
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-23

Bandgap Topologies Compatible with Low Voltage Power Supply

VDD VDD VDD VDD
VDD VDD VDD
IPTAT IVBE
IVBE INL IPTAT
VRef VRef
VRef R2
VPTAT IPTAT
INL R3
VBE

R1

Voltage-mode bandgap topology. Current-mode bandgap topology. Voltage-current mode bandgap topology.
Fig. 7.6-14

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Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-24

Technique for Canceling the Bandgap Curvature

VDD
1:K2 1:K3
M2 active M2 sat.
M1 M2 M3 M4 M3 off M3 on

Current
K2IVBE K1IPTAT
I2 INL K3INL

INL
IVBE K1IPTAT
Temperature
Circuit to generate nonlinear correction term, INL. Illustration of the various currents.
Fig. 7.6-16
 0 , K2IVBE > K1IPTAT
INL = 
 K1IPTAT - K2IVBE , K2IVBE < K1IPTAT

The combination of the above concept with the previous slide yielded a curvature-
corrected bandgap reference of 0.596V with a TC of 20ppm/C° from -15C° to 90C°
using a 1.1V power supply.† In addition, the line regulation was 408 ppm/V for
1.2VDD10V and 2000 ppm/V for 1.1VDD10V. The quiescent current was 14µA.

† G.A. Rincon-Mora and P.E. Allen, “A 1.1-V Current-Mode and Piecewise-Linear Curvature-Corrected Bandgap Reference,” J. of Solid-State
Circuits, vol. 33, no. 10, October 1998, pp. 1551-1554.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-25

LOW VOLTAGE OP AMPS

A Low Voltage Op Amp using Normal Technology
VDD(min) = 3VON + VT (ICMR = VON):
VDD
VPB1 M3 M4
M11

VPB2 vOUT
Cc
+ M1 M2
vIN M6 M7
-
VNB1
M5 M8 M9 M10

060804-01

Performance:
Gain ≈ gm2rds2
Miller compensated
Output swing is VDD -2VON
Max. CM input = VDD
Min. CM input = 2VON + VT
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-26

A Low-Voltage, Wide ICMR Op Amp

VDD(min) = 4VON + 2VT (ICMR = VDD):

Performance:
Gain ≈ gm2rds2, self compensated, and output swing is VDD -4VON

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-27

An Alternate Low-Voltage, Wide ICMR Op Amp

VDD(min) = 4VON + 2VT (ICMR = VDD):
VDD
VPB1 3:1

VPB2 VPB2
+ - vOUT
VNB2 VNB2

VNB1
1:3
060804-02

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Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-28

A 1-Volt, Two-Stage Op Amp

Uses a bulk-driven differential input amplifier.

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Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-29

Performance of the 1-Volt, Two-Stage Op Amp

Specification (VDD=0.5V, VSS=-0.5V) Measured Performance (CL = 22pF)
DC open-loop gain 49dB (Vicm mid range)
Power supply current 300µA
Unity-gainbandwidth (GB) 1.3MHz (Vicm mid range)
Phase margin 57° (Vicm mid range)
Input offset voltage ±3mV
Input common mode voltage range -0.475V to 0.450V
Output swing -0.475V to 0.491V
Positive slew rate +0.7V/µsec
Negative slew rate -1.6V/µsec
THD, closed loop gain of -1V/V -60dB (0.75Vp-p, 1kHz sinewave)
-59dB (0.75Vp-p, 10kHz sinewave)
THD, closed loop gain of +1V/V -59dB (0.75Vp-p, 1kHz sinewave)
-57dB (0.75Vp-p, 10kHz sinewave)
Spectral noise voltage density 367nV/ Hz @ 1kHz
181nV/ Hz @ 10kHz,
81nV/ Hz @ 100kHz
444nV/ Hz @ 1MHz
Positive Power Supply Rejection 61dB at 10kHz, 55dB at 100kHz, 22dB at 1MHz
Negative Power Supply Rejection 45dB at 10kHz, 27dB at 100kHz, 5dB at 1MHz
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-30

A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique

VDD
VBiasP M11 M12

M6 M13
Cx M9 M10
M17
+
vin M1 M2 vout
-
CL
M7 M8

VBiasN M3 M5 M4 M14
M15
M16

VSS Fig. 7.6-21

Transistors with forward-biased bulks are in a shaded box.

For large common mode input changes, Cx, is necessary to avoid slewing in the input
stage.
To get more voltage headroom at the output, the transistors of the cascode mirror have
their bulks current driven.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-31

A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique -

Continued
Experimental results:
0.5µm CMOS, 40µA total bias current (Cx = 10pF)
Supply Voltage 1.0V 0.8V 0.7V
Common-mode input 0.0V-0.65V 0.0V-0.4V 0.0V-0.3V
range
High gain output range 0.35V-0.75V 0.25V-0.5V 0.2V-0.4V
Output saturation limits 0.1V-0.9V 0.15V-0.65V 0.1V-0.6V
DC gain 62dB-69dB 46dB-53dB 33dB-36dB
Gain-Bandwidth 2.0MHz 0.8MHz 1.3MHz
Slew-Rate (CL=20pF) 0.5V/µs 0.4V/µs 0.1V/µs
Phase margin 57° 54° 48°
(CL=20pF)
The nominal value of bulk current is 10nA gives a 10% increase in differential pair
quiescent current assuming a BJT  of 100.

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Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-32

SUMMARY
• Integrated circuit power supplies are rapidly decreasing (today 2-3Volts)
• Classical analog circuit design techniques begin to deteriorate at 1.5-2 Volts
• Approaches for lower voltage circuits:
- Use natural NMOS transistors (VT  0.1V)
- Drive the bulk terminal
- Forward bias the bulk
- Use depeletion devices
• The dynamic range will be compressed if the noise is not also reduced
• Fortunately, the threshold reduction continues to allow the techniques of this section to
be used in today’s technology

CMOS Analog Circuit Design © P.E. Allen - 2016