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2023 Midterm Papers

The document appears to be a collection of exam questions for multiple subjects related to electrical engineering and communications. It includes questions about optical fiber communication systems, VLSI testing and testability, digital communication systems, digital CMOS integrated circuits. The questions cover topics such as optical fiber properties, fault modeling, digital modulation techniques, CMOS inverter design, logic gate implementation.
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0% found this document useful (0 votes)
73 views5 pages

2023 Midterm Papers

The document appears to be a collection of exam questions for multiple subjects related to electrical engineering and communications. It includes questions about optical fiber communication systems, VLSI testing and testability, digital communication systems, digital CMOS integrated circuits. The questions cover topics such as optical fiber properties, fault modeling, digital modulation techniques, CMOS inverter design, logic gate implementation.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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202) UECI64

Malaviya National Institute of Technology, Jaipur


Department of Electronics and Communication Engineering
Mid Term Examination
ECT305: Optical Communication Systems B.Tech., V Sem.
Duration: 90 minutes, Full Marks: 30 22-09-2023, 2 to 3:30 PM
Answer allQuestions. Make suitable assunptions if required.
1. How are optical fibers useful in the current telecommunication scenario? (4|
2. Calculate the numerical aperture of a step-index fiber having core dianeter of 15uTn, nË = 1.46 and
n2 = 1.42. Find the maximum entrance angle for this fiber if the outer mediun is (i) air and (ii) a
medium with refractive index 2. Which wavelengths can be trastnitted through this fiber? Identify a
wavelength at which two nodes can propagate in this fiber Discussthe relationship between normalized
cut-off frequency and the cut-off wavelength? |1+2+2+2+t3)
3. Discuss the principle of working and application of dispersion shifted fibers. (4)
4. List the steps invloved in the preparation of an optical fiber cable. (4
b. Describe misalignment losses in optical connectioI.s and ways to reduce the sane. [8)
Department of Electronics and Conmmunication Engineering MNIT Jaipur
UG-B.Tech- 5th Sem ECE; ECT306: VLSI Testing and Testability
Time 2:00 pm to 3:30 pm Date: 23-09-2023 MM: 30

1. What are different types of fault models. exDlain in brief? A )With respect to presence o
fault versus time b) Device physical faults 5
2
How many totalsingle stuck at fauit are there in the below circuit. Write check point
theorem and verify the same for the below XOR gate circuit. 5

A Xor B =A'B + AB'


3. Name different fault simulation algorithms fxpla1n parallel and deductve algorithm
assuming stuck at 1 faults at the outputs of inverters in the abc.e diagram. 6

4 What are different methods to generate combinational circuit test patterns, explain any
three with example
5 Calculate Comb1national controllabilities and observabal1tjes for the logic diagram given
below. Assume all inputs have CCs(1, 1) and SCs(0,0] and outputshave CO and SO both "o"
(Note CLK is level trigger)
Jruener

J D
CLK
K

COURSE OUTCOMES

CO1: To able to grasp core concept of digitalsystem testing and testability. (Knowledge,
Understanding)
cO2 Tounderstand how a faulty circuit may cause disasters and affect the nature as well as sOCiety.
(Affective, Analyze)
cO3 To understand fault detection using different fault simulation techniques. (Skill, Evaluate)
co4 To develop ability to design algorithms for automatic test generation fo: combinational circuits,
sequential circuits, PLAS and memory. (Skili/Affective. Create)
cO5 To apply probabilistic approaches for random test generation. (Skill, Apply)
cO6 To apply different redundancy based fault telerance techniques to increase circuit reliability.
(Skil/Affective, Analyze)
CO7 To design BIST for aCUT iin Verilog (HDL) and implement ATPG algorithmsin C/C++/MATLAS
(Skill, Create)
V Sem. (ECE) Mid Term Test
Subject: Digital Communication System (ECT303)
Time - 2 PM- 3.30 PM
Date of Examination: 20/09/2023 Max Marks - 30

Attempt all questions in sequence

1. Explain briefly?
from the two degradation types,
a) The error performanceof a digital signalling suffers primarily
irreducible bit error probability. How
loss in signal to noise ratio and distortion resulting in an
do they differ?.
mechanism with a diagram.
b Drawa regenerative repecater and explain its timing extraction
from the eye
c Select the four parameters observed from an eye pattern. How can you judge
diagram that the binary symbol is received faithfully.

d) Using the binary data sequence 111001010 represent it in BASK , BPSK and BFSK digital
modulation signals with proper time diagram.

Draw the bipolar HDB3 NRZ-AMI line coding waveform for the binary data sequence given
as 1110000101101000000001.
/) Data at arate of 6 kbit/sec is to be transmitted over a leased line of band width 4 kHz using
Nvguist criterion pulses. Determine the maximum value of the roll off factor that can be used.
2.5 x 6

Xsketch theUnipolar RZ, AMI NRZ and Manchester signal formats for transmission of binary data
101100010 with proper timing diagram and expiain briefly their merits and demerits.

3. Derive the error probability expression for polar signal line code. ()
4. Derive the expressions of Power Spectral Density (PSD) for On-Off signalling and plot them for a
randomn binary sequence. 4

5. A digital communication system uses 4-level PAM along with a raised cosine roll off filter
Characteristics. The system has afrequencyresponse of 3.2 kHz. If the binary data is transmitted
at 9600 bits per sec data rate then what would be the symbol rate and roll off factor r of the
transmitted pulse shape for zero ISI ?.
Malaviya National Institute of Technology Jaipur
Department of ECE
MID Semester Examination (Date: 21I/09/2023)

Digital CMOS IC (ECT 304) Total Marks: 30


All the Questions are Compulsory Time: 1hrs. and 30 minutes
1. Show schematically the operation of MOSFET
under accumulation, depletion, CO1 5
and inversion modes. Draw the
2.
corresponding energy band diagrams.
Derive the drain current equations of n-MOSFET in linear and
saturation regions CO1
for a long channel device.
3. Explain the operation of CMOS inverter and draw its voltage transfer C03 4+1
characteristics by indicating different regions. Define the terms VoOH, VoL, VIL,
VIH.
4. Write a short note on Junction Capacitance and Constant Electric Field Scaling. CO2 2.5+2.5

5. Design the CMOS circuit for the following: CO3

(a) F=(A+D+C)(B+E)
(b) The output of a two input logic gate is at logic high value only when both
the inputs are different.

6. faDraw the stick diagram and layout of 4 input CMOS NOR gate. CO3+CO1 3+2

tb The drain and gate terminal of N-MOSFET is shorted such that gate to source
voltage (Ves) is equal to drain to source voltage (Vás) and threshold voltage (V,) =
0.5 V. The drain current () is 0.5 mA at Vgs =1V. Estimate the value of Ia for
Vgs = 1.5 V.

:Axe
7
when
(m)= (2)
al<|. Asme fer
-n
i)
dnetomsfm z- fnd 3
(fnnthe
dime
3 -2, 2, § a)
n) ad 9} 3,
onvolusn linn (otn yoaet mai
sijlad follsiy lonvlaton
f theExtes
andhs-k) hontk) 8(n)=
teany in 6)
3o
Maulg: Mar
2023-2Y MTE E¬, t Deþt JA\eUR, MNIT

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