Micro Controllers

Refer programs taken in practicals and skills also for theory paper

1. memory block data transfer ( eg 40 H to 50 H)

2. addition of 5 numbers saved at consecutive memory location 40 H
3. different logics for running light one led at a time
4. running light Two led at a time
5. LED interfacing
6. Seven segment interfacing
7. skill 6 Three switches relay and LED interfacing
8. LCD interfacing
9. Triangular wave generator
Micro Controllers
• A microcontroller is a small and low-cost microcomputer, which is
designed to perform the specific tasks of embedded systems like
displaying microwave’s information, receiving remote signals, etc.
• The general microcontroller consists of the processor, the memory
(RAM, ROM, EPROM), Serial ports, peripherals (timers, counters), etc.
System bus
Comparison microcontrollers and microprocessors
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Harvard Von Nuemann
Harvard architecture has physically separate Von Nuemann architecture has single physical memory
program and data memory and separate buses to for program and data as well as single bus to access
access the same. the same

With Harvard architecture processor can access In Von Nuemann architecture either program or data
program and data memory at the same time which can be accessed at a time.
can help to perform faster program execution

With Harvard architecture it is possible to have With Von Nuemann architecture since only single bus is
different address and data bus width for program available, bus characteristics are same for program and
and data memory data.

HW design of this architecture is complex and HW design for this architecture is simple and cost
expensive. efficient.

Since program and data are different programs are Since program and data share the same memory, a
prone to crash caused by program error itself. program error can rewrite the instruction and result into
undesirable behaviour or crash.

Microchip based PIC microcontroller Pentium, Motorola 68HC11

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Van-Neuman Architecture:

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• It does not differentiate the data and program memory.
• Uses single data and address bus to fetch the code and data.
• Execution of data or code occurs in sequential fashion.
• It limits the operating bandwidth.
• Advantage: Simple construction , simple bus structure.
• Disadvantage: Both data and code can not be accessed simultaneously.

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S.No. Paameter Complex Instruction Set Computer Reduced Instruction Set Computer (RISC)
(CISC)
01 Clock Operates at 33-50 MHz Operates at 50-150 MHz
02 Number of Instruction 120-350 Less than 100

03 Instruction Cycles Complex Instruction taking multiple Simple Instruction taking 1 cycle
cycles
04 Design Feature- Designed around Instruction set (no Designed around pipeline
Pipeline pipeline)

05 Instruction Formats Variable format Instruction Fixed format Instruction

06 Instruction Execution Instruction interpreted by micro program Instruction executed by Hardware

07 Addressing modes Many Instruction and addressing modes Few Instruction and addressing modes (3-5)
(12-14)
08 Complexity Complexity in the micro program Complexity in the compiler

09 Instruction set Single register set Multiple register sets

10 Memory accress Only LOADs, STOREs access memory Any Instruction may access memory

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Microcontroller classification
Types of Microcontrollers (Bit based)
Microcontrollers are divided into various categories based on memory, architecture,
bits and instruction sets. Following is the list of their types −
Bit
Based on bit configuration, the microcontroller is further divided into three
categories.
• 8-bit microcontroller − This type of microcontroller is used to execute arithmetic
and logical operations like addition, subtraction, multiplication division, etc. For
example, Intel 8031 and 8051 are 8 bits microcontroller.
• 16-bit microcontroller − This type of microcontroller is used to perform arithmetic
and logical operations where higher accuracy and performance is required. For
example, Intel 8096 is a 16-bit microcontroller.
• 32-bit microcontroller − This type of microcontroller is generally used in
automatically controlled appliances like automatic operational machines, medical
appliances, etc.
Types of Micro Controller – Instruction set
based
Based on the instruction set configuration, the microcontroller is
further divided into two categories.
• CISC − CISC stands for complex instruction set Architecture. It allows
the user to insert a single instruction as an alternative to many simple
instructions.
• RISC − RISC stands for Reduced Instruction Set Architecture. It
reduces the operational time by shortening the clock cycle per
instruction.
Overview of 8051 Micro Controller
• 8051 microcontroller is designed by Intel in 1981. It is an 8-bit
microcontroller. It is built with 40 pins DIP (dual inline package), 4kb of
ROM storage and 128 bytes of RAM storage, 2 16-bit timers. It consists of
are four parallel 8-bit ports, which are programmable as well as
addressable as per the requirement. An on-chip crystal oscillator is
integrated in the microcontroller having crystal frequency of 12 MHz.
• Let us now discuss the architecture of 8051 Microcontroller.
• In the following diagram, the system bus connects all the support devices to
the CPU. The system bus consists of an 8-bit data bus, a 16-bit address bus
and bus control signals. All other devices like program memory, ports, data
memory, serial interface, interrupt control, timers, and the CPU are all
interfaced together through the system bus.
• May have external data and code memory
Pins and Architecture
Memory Maps
Register Banks: 00h to 1Fh. The 8051 uses 8 general-purpose registers R0 through R7 (R0, R1, R2, R3, R4, R5, R6, and R7).
There are four such register banks. Selection of register bank can be done through RS1,RS0 bits of PSW. On reset, the
default Register Bank 0 will be selected.
Bit Addressable RAM: 20h to 2Fh . The 8051 supports a special feature which allows access to bit variables. This is where
individual memory bits in Internal RAM can be set or cleared. In all there are 128 bits numbered 00h to 7Fh. Being bit
variables any one variable can have a value 0 or 1. A bit variable can be set with a command such as SETB and cleared with
a command such as CLR. Example instructions are:
SETB 25h ; sets the bit 25h (becomes 1) CLR 25h ; clears bit 25h (becomes 0)
Note, bit 25h is actually bit 5 of Internal RAM location 24h.
The Bit Addressable area of the RAM is just 16 bytes of Internal RAM located between 20h and 2Fh.

General Purpose RAM: 30h to 7Fh. Even if 80 bytes of Internal RAM memory are available for general-purpose data
storage, user should take care while using the memory location from 00 -2Fh

since these locations are also the default register space, stack space, and bit addressable space. It is a good practice to use
general purpose memory from 30 – 7Fh. The general purpose RAM can be accessed using direct or indirect addressing
modes.
SFR List
Port 1

Port 1 occupies a total of 8 pins (pins 1 through 8) . It can be used as input or output. In
contrast to Port 0 , this port does not need any pull-up resistors since it already has
pull-up resistors internally. Upon reset port 1 is configured as an output port. To make
Port 1 an input port it must be programmed as such by writing 1 to all its bits.
Port 2

Port 2 occupies a total of 8 pins ( pins 21 through 28). It can be

used as input or output. Just like P1, port 2 does not need any
pull-up resistors since it already has pull-up resistors internally.
Upon reset, port 2 is configured as an output port. To make port 2
as input, it must programmed. as such by writing 1 to all its bits.
The dual role of port 2 is also accomplished by providing higher
byte address through A8-A15 to access the external memory.
Port 3

Port 3 occupies a total of 8 pins, pin 10 through 17. It can be used as input or output. P3 does not need any pull-up
resistors , the same as P1 and P2. Although Port 3 is configured as an output port upon reset, Port 3 has additional
function of providing some extremely important signals such as interrupts. Table depicts the alternate functions of port
2. P3.0 and P3.1 are used for the RxD and TxD serial communication signals. P3.2 and P3.3 are used for external
interrupts. Bits P3.4 and P3.5 are used for timers 0 and 1. Bits P3.6 and P3.7 are used to provide WR and RD signals for
external memories in 8051 based system.
Addressing Modes
What is an Addressing Mode?
An Addressing Mode is a way to locate a target Data, which is also
called as Operand. The 8051 Family of Microcontrollers allows five
types of Addressing Modes for addressing the Operands. They are:
• Immediate Addressing
• Register Addressing
• Direct Addressing
• Register – Indirect Addressing
• Indexed Addressing
 Programming model:
The CPU registers are used to store the data temporarily. The information may be data to be processed or address
pointing the data to be fetched. The majority of registers are 8 bits. The 8-bit registers are shown in the diagram from
MSB (most significant bit) D7 to the LSB (least significant bit) D0. The most widely used registers of 8051 are A
(accumulator), B, R0, R1, R2, R3, R4, R5, R6, R7, DPTR (data pointer), and PC (program counter). All these registers are
8 bits except DPTR and the program counter. The accumulator is used to hold one operand before execution and hold
the result after execution. The program counter points to the address of next instruction to be fetched. It is a auto
increment register. As the size of program counter is 16 bit. 8051 can access the program addresses from
0000H-FFFFH. When 8051 is powered-up the program counter contents will be 0000H. This means that it expects the
first opcode to be stored at ROM address 0000H. For this reason in the 8051 system, the first opcode must be burned
memory location 0000H of program ROM since this is where it looks for the first instruction when it is booted.
 PSW : Programm Status Word
It is 8 bit register. Its address is D0H and It is bit and byte accessible. It has 4 conditional flags or math flags which sets or
resets according to condition of result. It has 3 control flags, by setting or resetting bit required operation or function can
be achieved.
1. Carry Flag(CY): During addition and subtraction any carry or borrow is generated then carry flag is set otherwise carry
flag resets. It is used in arithmetic, logical, jump, rotate and Boolean operations.
2. Auxiliary carry flag(AC): If during addition and subtraction any carry or borrow is generated from lower 4 bit to higher
4 bit then AC sets else it resets. It is used in BCD arithmetic operations.
3. Overflow flag(OV): If in signed arithmetic operations result exceeds more than 7 bit than OV flag sets else resets.It is
used in signed arithmetic operations only.
4. Parity flag(P): If in result, even no. Of ones "1" are present than it is called even parity and parity flag sets. In result
odd no. Of ones "1"are present than it is called odd parity and parity flag resets.
ii. CONTROL FLAGS:
1. FO: It is user defined flag. The user defines the function of this flag. The user can set ,test n clear this flag through
software.
2. RS1 and RS0: These flags are used to select bank of register by resetting those flags which are as shown in table :
• The 128 bytes of RAM inside the 8051 are assigned the
address 00 to 7FH. They can be accessed directly as
memory locations and are divided into three different
groups as follows −
• 32 bytes from 00H to 1FH locations are set aside for
register banks and the stack.
• 16 bytes from 20H to 2FH locations are set aside for
bit-addressable read/write memory.
• 80 bytes from 30H to 7FH locations are used for read
and write storage; it is called as scratch pad. These 80
locations RAM are widely used for the purpose of
storing data and parameters by 8051 programmers.
 • Instruction Timings
The 8051 internal operations and external read/write operations are controlled by the oscillator clock.
T-state, Machine cycle and Instruction cycle are terms used in instruction timings.
T-state is defined as one subdivision of the operation performed in one clock period. The terms 'Tstate' and 'clock
period' are often used synonymously.
Machine cycle is defined as 12 oscillator periods. A machine cycle consists of six states and each state lasts for two
oscillator periods. An instruction takes one to four machine cycles to execute an
instruction.
Instruction cycle is defined as the time required for completing the execution of an instruction. The 8051 instruction
cycle consists of one to four machine cycles.
Eg. If 8051 microcontroller is operated with 12 MHz oscillator, find the execution time for the
following four instructions.
1. ADD A, 45H
2. SUBB A, #55H
3. MOV DPTR, #2000H
4. MUL AB
Since the oscillator frequency is 12 MHz, the clock period is, Clock period = 1/12 MHz = 0.08333 µS.
Time for 1 machine cycle = 0.08333 µS x 12 =1 µS.
Instruction No. of machine cycles Execution time
• 1. ADD A, 45H 1 1 µ
• Instruction pipelining is mechanism used in CPU to increase overall instruction
execution throughput.
• For a general four stage pipelining each instruction is divided into four stages as below

• Fetch = Fetch instruction from program memory

• Decode = Decode the instruction opcode
• Execute = Perform operation
• Write Back = Write operated data to data memory/registers.

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Stack pointer (SP): It is 8-bit register. It is byte addressable. Its address is 81H. It is used to hold the
internal RAM memory location addresses which are used as stack memory. When the data is to be
placed on stack by push instruction, the content of stack pointer is incremented by 1, and when data
is retrieved from stack, content of stack of stack pointer is decremented by 1.
• All registers except PC are memory mapped. For example SP (stack pointer) is byte wide register at
address 0x81 in RAM.
• the stack is a section of a RAM, there are registers inside the CPU to point to it. The register used
to access the stack is known as the stack pointer register. The stack pointer in the 8051 is 8-bits
wide, and it can take a value of 00 to FFH. When the 8051 is initialized, the SP register contains
the value 07H. This means that the RAM location 08 is the first location used for the stack. The
storing operation of a CPU register in the stack is known as a PUSH, and getting the contents from
the stack back into a CPU register is called a POP.
• A stack is sometimes referred to as a Last-In-First-Out (LIFO) or First-In-Last-Out (FILO) structure
• . In 8051 internal RAM space can be used as stack. The address of the stack is contained in a
register called stack pointer. Instructions PUSH and POP are used for stack operations. When a
data is to be placed on the stack, the stack pointer increments before storing the data
• Show the stack and SP for the following.
• [SP]=07 //CONTENT OF SP IS 07 (DEFAULT VALUE)
• MOV R6, #25H [R6]=25H //CONTENT OF R6 IS 25H
• MOV R1, #12H [R1]=12H //CONTENT OF R1 IS 12H
• MOV R4, #0F3H [R4]=F3H //CONTENT OF R4 IS F3H
• PUSH 6 [SP]=08 [08]=[06]=25H //CONTENT OF 08 IS 25H
• PUSH 1 [SP]=09 [09]=[01]=12H //CONTENT OF 09 IS 12H
• PUSH 4 [SP]=0A [0A]=[04]=F3H //CONTENT OF 0A IS F3H
• POP 6 [06]=[0A]=F3H [SP]=09 //CONTENT OF 06 IS F3H
• POP 1 [01]=[09]=12H [SP]=08 //CONTENT OF 01 IS 12H
• POP 4 [04]=[08]=25H [SP]=07 //CONTENT OF 04 IS 25H
Data Transfer Instruction: Three types of the data transfer can
be done by move instruction.
• First type is transfer within the internal RAM and SFRs,
• second type is transfer using code memory area (CODE) and
• Third is using the external data memory X-DATA).
Instruction Action Addressing Length in cycles
(Mnemonic) bytes
MOV A, Rn Move Rn into A Register 1 1

MOV Rn, A Move into Rn from A Register 1 1

MOV A, #data Move immediate 8-bit data into A Immediate 2 1

MOV Rn, #data Move into Rn the data. immediate 2 1

MOV A, direct Move byte at the direct address into A Direct 2 1

MOV Rn, direct Move from direct address into Rn Direct 2 2

MOV direct, A Move byte to the direct address form A Direct 2 1

MOV direct, Rn Move a byte to the direct address from Rn Direct 2 2

M OV direct, direct Move byte to the direct address from the direct address Direct 3 2

MOV direct, #data Move immediate data byte to the direct address Immediate 3 2

MOV a,@Ri Move into A the byte from the address pointed by Ri Indirect 2 2

MOV @Ri, A Move A into address pointed by Ri Indirect 1 1

MOV direct, @Ri Move into direct address from address pointed by Ri indirect 1 1

MOV @Ri, direct Move from the direct address to the address poined by ri Indirect 2 2

MOV @Ri, #data Move data ino address pointed by Ri immediate 2 2

MOV DPTR, data16 Mov e16 bit dat immediate 3 2

Instruction Action Addressing Length in cycles

(Mnemonic) bytes
MOVC Instructions for transfer from the program memory area address code or constant to
accumulator in 8051

Instruction Action Addressing Length Cycles

in bytes
MOVC A, @A+DPTR Moves the code or constant into A the byte Indirect 1 2
from the program memory address pointed
by hypothetical addition of DPTR with the A
itself.

MOVC A, @A+PC Move the code or constant into A the byte Indirect 1 2
from the program memory address
pointed by hypothetical addition of PC
with the A
itself
 MOX-type Instructions

A MOVX instruction means move (copy) the 8-bit data into A

and from A using the external data memory address using DPTR
or Ri as the pointer

Instruction Action Addressing Length in bytes Cycles

MOVX A, @DPTR Move the external data byte (X-DATA) Indirect 1 2

into A from the data memory address
pointed
by DPTR

MOVX @DPTR,A Move into the external data Indirect 1 2

memory from A to the address pointed
by DPTR

MOVX A,@Ri Move the external data byte into a from Indirect 1 2
the memory
address pointed by Ri

MOVX @Ri, A Move into the external data memory Indirect 1 2

from A to the memory address pointed by
Ri
 PUSH and POP instructions for using the Stack Area
employing SP

Instruction Action Addressing Length in Cycles

bytes

PUSH direct Move byte from a direct Direct 2 2

internal RAM or SFR into the
stack after first incrementing
the stack pointer by 1

POP direct Move byte to a direct internal Direct 2 2

RAM or SFR into the stack
and then decrement the stack
pointer by 1.
XCH-type instructions

An XCH instruction is for exchanging the A register with a source using the register (direct or
indirect addresing0 mode.

Instruction Action Addressing Length in cycles

bytes

XCH A@Ri Exchange byte at A with the Indirect 1 2

address pointed by Ri

XCH A,Rn Exchange byte at A with the Register 1 2

register Rn

XCH A, direct Exchange byte at A with the byte Direct 1 1

at a direct address.
Instruction Action Addressing Flags Length Cycles
affected (bytes)
ADD A,Rn Add Rn into A Register C,AC,OV 1 1
ADD A, direct Add the byte at the direct address Direct C,AC,OV 2 1
into A
ADD A, @Ri Add the byte from the address pointed by the Ri into A Indirect C,AC,OV 1 1

ADD A, #data Add immediate data byte to the A Immediate C,AC,OV 2 1

ADDC A, Rn Add CF(carry) bit and Rn into A Register C,AC,OV 1 1
ADDC A, direct Add CF bit and byte at the direct Direct C,AC,OV 2 1
address ito A
ADDC A @Ri Add CF bit and the byte from the address pointed by the Ri Indirect C,AC,OV 1 1

ADDC A, #data Add CF bit and immediate data Immediate C,AC,OV 2 1

byte to the A
SBBB A,Rn Subtract borrow at CF bit and Rn Rgister C,AC,OV 1 1
into A
SBBB A, direct Subtract borrow at CF bit and byte at the direct address into A Direct C,AC,OV 2 1

SBBB A, @Ri Subtract borrow at C bit and byte at Indirect C,AC,OV 1 1

the byte from the address pointed
 by the Ri into A
SBBB A, #data Subtract borrow at CF bit and Immediate C,AC,OV 2 1
immediate data byte into A

INC A Increment Register None 1 1

INC Rn Increment Rn Register None 1 1
INC direct Increment byte at the direct address Direct None 2 1
INC @Ri Increment the byte at the address Indirect None 1 1
pointed by Ri

DEC A Decrement A Register None 1 1

DEC Rn Decrement Rn Register None 1 1
DEC direct Decrement byte at the direct Direct None 2 1
address

DEC @Ri Decrement the byte at the address Indirect None 1 1

pointed by the Ri

MUL AB Multiply A and B Result MSB in B and LSB Register OV 1 4

in A

DIV AB Divide A (Numerator) and B( Register OV 1 4

denominator) Remainder in B Quotient in
A

DAA Decimal adjust accumulator Register C 1 1

 Logical Instruction

Table gives features of 8-bit AND, OR and XOR instruction. These instructions have 4 addressing modes such as
register, immediate, direct and indirect.

Instruction Action Addressing Length in bytes Cycles

ANL A, Rn AND Rn into A Register 1 1

ANL A, direct AND byte at the direct address Direct 2 1
into A
ANL A, @Ri AND into the byte from the Indirect 1 1
address pointed by the Ri
ANL A, #data AND immediate data byte into A immediate 2 1
ANL direct, A AND A into byte at the direct Direct 2 1
address
ANL direct, #data AND immediate byte into byte at Direct 3 2
the direct address
ORL A, Rn OR Rn into A Register 1 1
ORL A, direct OR byte at the direct address into Direct 2 1
A
ORL A, @Ri OR into the byte from the address Indirect 1 1
pointed by Ri
ORL A, #data OR immediate data byte to the A immediate 2 1
ORL direct, A OR A into byte at the direct Direct 2 1
address
ORL direct,#data OR immediate byte into byte at the Direct 3 2
 direct address

XRL A, Rn XOR Rn into A Register 1 1

XRL A, direct XOR byte at the direct address Direct 2 1

into A

XRL A, @Ri XOR the byte at the address Indirect 1 1

pointed by Ri into A

XRL A, #data XOR immediate data byte to the A immediate 2 1

XRL direct, A XOR A into byte at the direct Direct 2 1

address

XRL direct, #data XOR immediate byte into byte at Direct 3 2

the direct address
 Boolean Variable manipulation Instructions These are also called as Boolean processing instruction.

Instruction Action Addressing Length Cycles

(bytes)
MOV C, bit Move bit into CF Direct bit addressing 2 1
MOV bit, C Move CF into the bit Direct bit addressing 2 2
CLR C Clear CF PSW Register CF bit 1 1
addressing
CLR bit Clear bit Direct bit addressing 2 1
CPL C Complement CF PSW Register CF bit 1 1
addressing
CPL bit Complement bit Direct bit addressing 2 1
SETB C Set CF=1 PSW Register CF bit 1 1
addressing
SETB bit Set bit =1 Direct bit addressing 2 1
ANL C,bit AND between CF and bit, place the Direct bit addressing 2 2
result in CF
AND between CF and , place the Direct bit addressing 2 2
ANL C, bit result in C
ORL C,bit OR between CF and bit, place the result in C Direct bit addressing 2 2

Direct bit addressing 2 2

ORL C, bit OR between CF and bit , place the result in C
Instruction Action Addressing Length Cycles
(bytes)
MOV C, bit Move bit into CF Direct bit addressing 2 1
MOV bit, C Move CF into the bit Direct bit addressing 2 2
CLR C Clear CF PSW Register CF bit 1 1
addressing
CLR bit Clear bit Direct bit addressing 2 1
CPL C Complement CF PSW Register CF bit 1 1
addressing
CPL bit Complement bit Direct bit addressing 2 1
SETB C Set CF=1 PSW Register CF bit 1 1
addressing
SETB bit Set bit =1 Direct bit addressing 2 1
ANL C,bit AND between CF and bit, place the Direct bit addressing 2 2
result in CF
ANL C, bit AND between CF and , place the Direct bit addressing 2 2
result in C
ORL C,bit OR between CF and bit, place the result in C Direct bit addressing 2 2

ORL C, bit OR between CF and bit , place the result in C Direct bit addressing 2 2
Relative Addressing.
Relative addressing is used only with conditional jump instructions. The relative address, (offset), is an 8 bit
signed number, which is automatically added to the PC to make the address of the next instruction. The 8 bit
signed offset value gives an address range of +127 to —128 locations.
The jump destination is usually specified using a label and the assembler calculates the jump offset
accordingly. The advantage of relative addressing is that the program code is easy to relocate and
the address is relative to position in the memory.
Eg. SJMP LOOP1
Absolute addressing
Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL (Absolute Call) instructions.
These are 2 bytes instructions. The absolute addressing mode specifies the lowest 11
bit of the memory address as part of the instruction. The upper 5 bit of the destination address arethe upper 5 bit
of the current program counter. Hence, absolute addressing allows branching only within the current 2 Kbyte
page of the program memory.
Eg. AJMP LOOP1
ACALL LOOP2
• Long Addressing
• The long addressing mode is used with the instructions LJMP and LCALL. These are 3 byte
• instructions. The address specifies a full 16 bit destination address so that a jump or a call can be
• made to a location within a 64 Kbyte code memory space.
• Eg. LJMP FINISH
• LCALL DELAY
8051 has three jump instructions: Long- it jumps to 16-bit address, Absolute- it jumps within 2 K bytes and Short- it jumps
to address within 128 bytes above or below the present address.
Long, absolute and short jump instructions

Instruction Action Addressing Length Cycles

in
bytes
LJMP addr16 Jump to the next address given Direct 16 3 2
by bit
two bytes in the instruction address

AJMP addr11 Jump to the next address Direct 11-bit 2 2

address
2 2
SJMP rel Direct 8-bit
Jump in the range between -128
and +127 from the address of
next instruction

JMP @A+DPTR Jump in the next address given Indirect

by
addition of 8-bits of A with 16- 16-bit relative
bits of DPTR addreess
Conditional Short Relative Jumps

Instruction Action Addressing Length Cycles

in bytes

Jump to a relative address if a is Relative(offset) 2 2

JNZ rel not zero

Jump to a relative address if A is Relative(offset) 2 2

JZ rel zero

Jump to a relative address if CF is Relative(offset) 2 2

JNC rel not 1

Jump to a relative address if CF=1 Relative(offset) 2 2

JC rel
Jump to a relative address if Relative(offset) 2 2
JB bit, rel addressed bit 1 (bit not set)

Jump to a relative address if Relative(offset) 2 2

JNB bit,rel addressed bit 0 (bit not set)

Jump to a relative address if Relative(offset) 2 2

JBC bit, rel addressed bit 1(bit set) and reset
carry ( make CF=0)
 Decrement and Conditional jump on Zero

Instruction Action Addressing Length Cycles

in bytes

DJNZ Rn, Rel Decrement Rn and jump if Rn is Relative (offset) 2 2

still not zero.

2 2
DJNZ direct, Rel Decrement byte at the direct and Relative (offset)
jump if byte is still not zero
 Jump after comparison

Instruction Action Addressing Flag Length Cycles

affected in bytes
Compare A and Relative C 3 2
CJNE A, #data, rel immediate data and (offset)
jump if both are not equal.

Compare Rn and immediate Relative C 3 2

CJNE Rn, #data, rel data and jump if both are (offset
not
equal.

Compare the bytes at A and Relative C 3 2

direct and jump if both are (offset
CJNE A, direct, rel
not
equal

Compare byte from the Relative C 3 2

address pointed by Ri and (offset)
CJNE @Ri, #data, rel
immediate data and jump if
both are not equal
 Call to a Routine

Instruction Action Addressing Length in Cycles

bytes

Direct 16- 3 2
LCALL addr16 Call to the next address given by two bit address
bytes in the instruction

Direct 11 2 2
ACALL addr11 Call the next address given by 11 bits in
the instruction.

Stack 1 2
RET Return to PC the saved PCL and PCH address
from the stack.
 Interrupt Control Flow (RETI instruction)

Instructio Action Addressing Length cycles

n In bytes
1 2
RETI Return into PC the Stack adddress
saved PCL and