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100001-Verilog MASS Question January 2023

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19 views4 pages

100001-Verilog MASS Question January 2023

Uploaded by

Shadrach Beats
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Verilog_MASS_Question_January 2023

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VLSI Training Services
Setting standards in VLSI Design

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Setting standards in VLSI Design

1. Write RTL code for a BCD counter that displays time in a 24hr format
as shown here HH:MM:SS with the following specification details:
I. Input Clock Frequency is 1Hz
II. Inputs: clock (posedge ), reset(Active high synchronous)
III. Outputs: ms_hr<3:0>, ls_hr<3:0>, ms_min<3:0>, ls_min<3:0>,
ms_sec<3:0>, ls_sec<3:0>

Solution:
RTL code
module timecount(input clk,rst, output reg [3:0]ms_hr, ls_hr, ms_min,
ls_min, ms_sec, ls_sec);

always @(posedge clk)


begin
if(rst)
begin
{ms_hr,ls_hr,ms_min,ls_min,ms_sec,ls_sec}=0;
end
else
begin
ls_sec<=ls_sec+1;
if(ls_sec==4'd9)
begin
ls_sec<=4'd0;
ms_sec<=ms_sec+1;
if(ms_sec==4'd5)
begin
if(ls_sec==4'd9)
begin
ls_sec<=4'd0;
ms_sec<=4'd0;
ls_min<=ls_min+1;
if(ls_min==4'd9)
begin
ls_min<=4'd0;
ms_min<=ms_min+1;
if(ms_min==4'd5)
begin
if(ls_min==4'd9)
begin
ls_min<=4'd0;
ms_min<=4'd0;
ls_sec<=4'd0;
ms_sec<=4'd0;
ls_hr<=ls_hr+1;
if(ls_hr==4'd9)
begin
ls_hr<=4'd0;
ms_hr<=ms_hr+1;
end
if(ms_hr==4'd2)

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VLSI Training Services
Setting standards in VLSI Design

begin
if(ls_hr>=4'd3)
begin
{ms_hr,ls_hr,ms_min,ls_min,ms_sec,ls_sec}<=0;
end
end
end
end
end
end
end
end
end
end
endmodule

Testbench:
`timescale 1s/100ms;
module timecount_tb;
reg clk,rst;
wire [3:0]ms_hr,ls_hr,ms_min,ls_min,ms_sec,ls_sec;
//integer hand;
timecount DUT(clk,rst,ms_hr,ls_hr,ms_min,ls_min,ms_sec,ls_sec);

task rst_dut;
begin
@(negedge clk);
rst=1;
@(negedge clk);
rst=0;
end
endtask

initial
begin
clk=0;
forever
#0.5 clk=~clk;
end

initial
begin
rst_dut;
#(25*60*60);
$finish;
end

initial
begin
$monitor("Clock Counter Value Time = %d%d :%d%d :%d%d
",ms_hr,ls_hr,ms_min,ls_min,ms_sec,ls_sec);
end
endmodule

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