PROGRAMMABLE LOGIC

DEVICES (PLD)

DR. FATMA ELFOULY

 PROBLEMS BY USING BASIC GATES

Many components on PCB:

As no. of components rise, nodes interconnection complexity
grow exponentially
Growth in interconnection will cause increase in interference,
PCB size, PCB design cost, and manufacturing time
PLDC

• The purpose of a PLD device is to permit elaborate digital logic

designs to be implemented by the user in a single device.
• Can be erased electrically and reprogrammed with a new design,
making them very well suited for academic and prototyping
• Types of Programmable Logic Devices
• SPLDs (Simple Programmable Logic Devices)
• PLA (Programmable Logic Array)
• PAL (Programmable Array Logic)
• GAL (Generic Array Logic)
• CPLD (Complex Programmable Logic Device)
• FPGA (Field-Programmable Gate Array)
PLD

 3 categories of PLDs:
1. SPLD (Simple Programmable Logic Device)
 PLA (Programmable Logic Array)
 PAL (Programmable Array Logic)
 Registered PAL
2. CPLD (Complex Programmable Logic Device)
3. FPGA (Field Programmable Gate Array)
ARCHITECTURE OF PLDS

P[0]
in[0] out[0]
nxp P[1] pxm
in[1] out[1]
AND Array : OR Array
: :
:
: (Programmable) (Programmable) :
P[p-1]
in[n-1] out[p-1]

n inputs m outputs
p product terms
fromed from inputs

Generic Architecture of PLDs

PROGRAMMABLE LOGIC ARRAY (PLA)
x1 x2 xn

 The connections in
the AND plane are
programmable Input buffers
and
inverters

 The connections in x1 x1 xn xn
the OR plane are
programmable P1

AND plane OR plane

Pk

f1 fm
 Inputs
PLA Programmable
OR Plane

Programmable
AND Plane

Programmable Element Outputs

(e.g. Metallic Fuse, UV
EPROM Cell)

The PLA Architecture

  Gate Level Version of PLA
x1 x2 x3

f1 = x1x2+x1x3'+x1'x2'x3 Programmable
connections

f2 = x1x2+x1'x2'x3+x1x3 P1
OR plane

P2

P3

P4

AND plane
f1 f2
 Programmable Array Logic (PAL)

x1 x2 xn
 The connections in
the AND plane are
programmable
Input buffers fixed connections
and
 The connections in inverters

the OR plane are x1 x1 xn xn

NOT programmable
P1

AND plane OR plane

Pk

f1 fm
PAL Inputs

Fixed OR Plane

Outputs
Programmable Programmable Element
AND Plane (e.g. Metallic Fuse, UV EPROM Cell)
The PAL Architecture
PAL
A B C
Programmable switch or fuse

f1  A  B  C  A  B  C

f2  A  B  A  B  C

AND plane
PAL
Inputs

Fixed OR Plane D or T
Programmable AND Plane Flip-flops

D Q

CLK

D Q

CLK

Clock
The Registered PAL Architecture
CPLD STRUCTURE
Integration of several PLD blocks with a
programmable interconnect on a single chip

I/O Block

I/O Block
• PLD PLD •
• Block Block •
• •

Interconnection Matrix
I/O Block

I/O Block
• PLD PLD •
• Block Block •
• •
 PLD - MACROCELL

Can implement combinational or sequential logic

Select
A B C Enable

f1

Flip-flop
MUX
D Q

Clock

AND plane
FPGA
ARCHITECTURE

15
 FPGA - GENERIC STRUCTURE
FPGA BUILDING BLOCKS:
Logic block Interconnection switches

I/O

PROGRAMMABLE LOGIC PROGRAMMABLE

BLOCKS INTERCONNECT
IMPLEMENT WIRES TO CONNECT
COMBINATORIAL AND INPUTS AND OUTPUTS
SEQUENTIAL LOGIC TO LOGIC BLOCKS

I/O

I/O
PROGRAMMABLE I/O
BLOCKS
SPECIAL LOGIC BLOCKS
AT THE PERIPHERY OF
I/O 16

DEVICE FOR EXTERNAL

CONNECTIONS
 Clock distribution

OTHER
FPGA Embedded memory blocks
BUILDING
BLOCKS DSP blocks:

Special purpose •Hardware multipliers, adders

and registers
Embedded
blocks: microprocessors/microcontrollers
High-speed serial transceivers

17
FPGA – BASIC LOGIC ELEMENT

• LUT to implement combinatorial logic

• Register for sequential circuits
• Additional logic (not shown):
• Carry logic for arithmetic functions
• Expansion logic for functions requiring more than 4 inputs

Select

Out

A
B
C
LUT D Q

Clock 18
 LOOK-UP TABLES (LUT)

• Look-up table with N-inputs can be used to implement any

combinatorial function of N inputs
• LUT is programmed with the truth-table

A
A B C D Z B
0 0 0 0 0 C LUT Z
0 0 0 1 1
D
0 0 1 0 1
0 0 1 1 1
0
0
1
1
0
0
0
1
0
1
LUT implementation
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0 A
1 0 0 1 1
B
1 0 1 0 1
1 0 1 1 1 Z
1 1 0 0 0
1 1 0 1 0 C
1 1 1 0 0
D

Truth-table Gate implementation 19

 LUT IMPLEMENTATION

X1
• Example: 3-input LUT X2
0/1
• Based on multiplexers 0/1

(pass transistors) Configuration memory

cells
0/1
0/1
• LUT entries stored in 0/1
F

configuration memory 0/1

cells
0/1
0/1

20
X3
PROGRAMMABLE INTERCONNECT

• Interconnect hierarchy (not shown)

• Fast local interconnect
• Horizontal and vertical lines of various lengths

LE LE LE

Switch Switch
Matrix Matrix

LE LE LE
21
SWITCH MATRIX OPERATION
Before Programming After Programming

• 6 pass transistors per switch matrix

interconnect point
• Pass transistors act as programmable
switches
• Pass transistor gates are driven by
configuration memory cells
22
FPGA VENDORS

Altera
Xilinx
Actel

Lattice
QuickLogic
 Design
Specification Design Entry

Function Simulation

FPGA Synthesis
DESIGN
FLOW
Place & Route

Timing Simulation

Program device & test

 FPGA DESIGN FLOW
Design Specification Design Entry/RTL Coding
Behavioral or Structural Description of Design

RTL Simulation
• Functional Simulation
• Verify Logic Model & Data Flow
(No Timing Delays)

LE Synthesis
• Translate Design into Device Specific Primitives
MEM I/O • Optimization to Meet Required Area & Performance Constraints

Place & Route

• Map Primitives to Specific Locations inside
Target Technology with Reference to Area &
• Performance Constraints
• Specify Routing Resources to Be Used
FPGA DESIGN FLOW
tclk
Timing Analysis
- Verify Performance Specifications Were Met
- Static Timing Analysis

Gate Level Simulation

- Timing Simulation
- Verify Design Will Work in Target Technology

Program & Test

- Program & Test Device on Board