FUNDAMENTAL

VHDL UNITS

Dr. Fatma Elfouly

WHAT IS
VHDL?
VHSIC
Hardware
Description
Language

VHSIC – Very High Speed Integrated Circuit

DIFFERENCE BETWEEN
HARDWARE
DESCRIPTION
LANGUAGE AND
SOFTWARE LANGUAGE
Hardware description language :
It describes hardware in textual form.
It describes hardware behavior and their structure.
Software language :
It is a programming language that allow a software
designer to executable software applications that
will operate on a suitable processor.
 BASIC VHDL
Library CODE
declarations

Basic VHDL Code

 LIBRARY declarations: Contains a list
of all libraries to be used in the design.
Entity For example: ieee, std, work, etc.
 ENTITY: Specifies the I/O pins of the
circuit.
 ARCHITECTURE: Contains the VHDL
code proper, which describes how the
Architecture  circuit should behave (function).
 ENTITIES AND
ARCHITECTURE
Entity Entity
Architecture

Architecture

Entity and Architecture

Entity: interface Architecture: internals
– names, modes (in / out),
types of externally – structure and
visible signals of circuit behaviour of module
 Signal mode: is one of the reserved words to
ENTITY indicate the signal direction:
 in – indicates that the signal is an input
 out – indicates that the signal is an output
of the entity whose value can only be read
by other entities that use it.
 buffer – indicates that the signal is an
output of the entity whose value can be Signal_type:
read inside the entity’s architecture a built-in or user-
 inout – the signal can be an input or an defined signal type.
output. Examples of types are
bit,bit_vector,Boolean,
character, std_logic,
etc.
ENTITY entity_name IS
PORT (
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
… );
END entity_name;
ENTITY
STD_LOGIC is defined in the
library std_logic_1164.This is
a nine valued logic system.
It has 9 values: 'U', 'X', '0', '1',
'Z', 'W', 'L' ,'H' and '-'.

U = uninitialized
BIT has 2 X = unknown
values: '0' 0 = logic 0
entity and_gate is and '1'. 1 = logic 1
entity and_gate is
port (a, b: in bit; port (a, b: in std_logic; Z = high impedance
x: out bit); x: out std_logic); (tri state)
end entity and_gate; end entity and_gate; W = weak unknown
L = weak "0"
H = weak "1"
- = dont care
 ARCHITECTURE

 The architecture body specifies how the

circuit operates and how it is implemented.
 Architecture is described using behavioral
code or structural code
  An entity or circuit can be specified in a variety of
ways, such as behavioral, structural
(interconnected components), or a combination of
the above.
 The behavioral level that describes a system in
terms of what it does (or how it behaves). A
STRUCTURAL behavioral description specifies the relationship
AND between the input and output signals.
 The structural level, on the other hand, describes
BEHAVIORAL a system as a collection of gates and components
that are interconnected to perform a desired
function.
ARCHITECTUR
E
ASSIGNMENT
STATEMENTS
Simple Signal
Assignment

Assignment Statements Concurrent Assignment

Statement.
Selected Signal
Assignment

Conditional Signal
Assignment

If-Then-Else-Statement
Sequential Assignment
Statement
Case Statement
CONCURRENT
ASSIGNMENT
STATEMENT.
SIMPLE
SIGNAL
ASSIGNMENT
 It used for a logic or arithmetic
expression.

Thegeneral
The general form
form is:- is:-
SELECTED SIGNAL ASSIGNMENT

 It used to assign one of several values based on

selection criterion used with keyword.
The general form is:-

With expression select

Signal_name <= expression when constant_value;
 mux

MULTIPLEXER
Multiplexer is a device that selects between several input signals and forwards
it to a single output line.
 Sel 2

a
b y

MUX
4-1
c
Sel y d
0 0 a
Sel 2
0 1 b
MULTIPLEXER 1 0 c
8
a
4-1 1 1 d
8 8 y

MUX
b

4-1
8
c 8
d
Sel 2
Sel y
0 0 a(0)
0 1 a(1) y

MUX
4

4-1
1 0 a(2) a
1 1 a(3)
SELECTED SIGNAL ASSIGNMENT
Multiplexer
library ieee;
use ieee.std_logic_1164.all; Sel 2
use ieee.std_logic_arith.all;
entity mux4_1 is
a
port (sel: in std_logic_vector (1 downto 0);
a, b, c, d: in std_logic; b y

MUX
4-1
y: out std_logic);
c
end entity mux4_1;
architecture rtl of mux4_1 is d
begin
with sel select
y <= a when “00”,
b when “01”,
c when “10”,
d when “11”,
a when others;
End rtl;
SELECTED SIGNAL ASSIGNMENT
Multiplexer

library ieee; Sel 2

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity mux4_1 is a 8
port (sel: in std_logic_vector (1 downto 0); 8 8 y

MUX
b

4-1
a, b, c, d: in std_logic_vector(7 downto 0); 8
y: out std_logic_vector(7 downto 0)); c 8
end entity mux4_1;
d
architecture rtl of mux4_1 is
begin
with sel select
y <= a when “00”,
b when “01”,
c when “10”,
d when “11”,
a when others;
SELECTED SIGNAL ASSIGNMENT
Multiplexer

library ieee; Sel 2

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity mux4_1 is
port (sel: in std_logic_vector (1 downto 0); y

MUX
4

4-1
a: in std_logic_vector(3 downto 0); a
y: out std_logic);
end entity mux4_1;
architecture rtl of mux4_1 is
begin
with sel select
y <= a(0) when “00”,
a(1) when “01”,
a(2) when “10”,
a(3) when others;
End rtl;
CONDITIONAL
SIGNAL
ASSIGNMENT
It used to set a signal to one of several
values.

The general form is:-

Signal_name <= expression when logic_expression else expression
;
CONDITIONAL SIGNAL ASSIGNMENT
Multiplexer

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; Sel 2
entity mux4_1 is
port (sel: in std_logic_vector (1 downto 0);
a, b, c, d: in std_logic; a
y: out std_logic);
b y

MUX
end entity mux4_1;

4-1
architecture rtl of mux4_1 is c
begin
d
y <= a when sel = “00” else
b when sel = “01” else
c when sel = “10” else
d;
end architecture rtl;
SEQUENTIAL
ASSIGNMENT
STATEMENT
 Case Statement
 If-Then-Else-Statement
A process statement is the main construct that allows you to use
sequential statements to describe the behavior of a system over time.
The syntax for a process statement is: [process_label :] process (sensitivity_list)
Variable declarations
Begin
[if-then-else-statement]
[case-ststement]
End process;
 Sel 2
SEQUENTIAL SIGNAL ASSIGNMENT
a
Multiplexer b y

MUX
4-1
c
library ieee; a
use ieee.std_logic_1164.all; d
use ieee.std_logic_arith.all;
entity mux4_1 is
port (sel: in std_logic_vector (1 downto 0);
a, b, c, d: in std_logic; b
y: out std_logic);
end entity mux4_1;
architecture rtl of mux4_1 is
begin c
process (sel)
begin
if (sel = “00”) then
y <= a;
elsif (sel = “01”) then
y <= b;
d
elsif (sel = “10”) then
y <= c;
else Sel 00 01 10 11
y <= d;
end if; y
end process;
end architecture rtl;
 Sel 2
SEQUENTIAL SIGNAL ASSIGNMENT
a
Multiplexer b y

MUX
4-1
library ieee; a c
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; d
entity mux4_1 is
port (sel: in std_logic_vector (1 downto 0);
a, b, c, d: in std_logic; b
y: out std_logic);
end entity mux4_1;
architecture rtl of mux4_1 is
begin c
process (sel, a, b, c, d)
begin
if (sel = “00”) then
y <= a;
elsif (sel = “01”) then
y <= b;
d
elsif (sel = “10”) then
y <= c;
else Sel 00 01 10 11
y <= d;
end if; y
end process;
end architecture rtl;
SOLVED
s0
PROBLEMS a0
2:1
s1
Mux
Design 8-to-1 multiplexer using only a1
2-to-1 multiplexer s0 2:1
Mux
a2 2:1 s2
s y Mux
a3
0 0 0 a0 s0 2:1 y
0 0 1 a1 a4 Mux
2:1 s1
0 1 0 a2
Mux
0 1 1 a3 a5
s0 2:1
1 0 0 a4
a6 Mux
1 0 1 a5 2:1
1 1 0 a6 a7 Mux
1 1 1 a7
SOLVED
PROBLEMS
Design a 32-to-1 multiplexer using
only 8-to-1 multiplexer
 SOLVED
PROBLEMS

Design a 8-to-1 multiplexer using only

2-to-1 multiplexer