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Lecture 5

The document discusses sequential circuit design using VHDL. It describes latches, D-type flip flops, parallel registers, and provides code examples to implement these components in VHDL. It also shows how to design a simple circuit using D-type flip flops and XOR gates.

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15 views

Lecture 5

The document discusses sequential circuit design using VHDL. It describes latches, D-type flip flops, parallel registers, and provides code examples to implement these components in VHDL. It also shows how to design a simple circuit using D-type flip flops and XOR gates.

Uploaded by

beshoymaherr1
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Sequential

circuit
design using
VHDL
Dr. Fatma ElFouly
Latch
Latch
A latch is a level sensitive memory cell that is transparent to signals passing
from the D input to Q output when enabled and holds the value of D on Q at
the time when it becomes disabled.
din
dout
latch
load
load

din

dout
• library ieee;
• use ieee.std_logic_1164.all;
• use ieee.std_logic_arith.all;
• entity d_latch is
• port (din, load: in std_logic;
• dout: out std_logic);
• end entity d_latch;
• architecture rtl of d_latch is
latch • begin
• process (din, load)
• begin
• if (load = ‘1’) then
• dout <= din;
• end if;
• end process;
• end architecture rtl;
D-Type Flip Flop
D-FF rst

din

D_FF q

clk

The D-type flip-flop is an edge triggered memory device that transfers a


signal’s value on its D input, to its Q output, when an active edge transition occurs on
its clock input. The output value is held until the next active clock edge.
Reset
Asynchronous

reset
reset
Synchronous
reset
rst
D-FF Asynchronous
reset rst

din
clk
D_FF q

din clk

q
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity d_flip_flop is
port (din, clk, rst: in std_logic;
q: out std_logic);
end entity d_flip_flop;
architecture first of d_flip_flop is

D-FF
begin
process (rst, clk)
begin
if (rst = ‘1’) then
q <= ‘0’;
elsif (rising_edge(clk)) then
q <= din;
end if;
end process;
end architecture first;
rst
D-FF Synchronous
reset rst

din
clk
D_FF q

din clk

q
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity d_flip_flop is
port (din, clk, rst: in std_logic;
q: out std_logic);
end entity d_flip_flop;
process (clk)
begin
if (rising_edge(clk)) then
if (rst = ‘1’) then
D-FF
q <= ‘0’;
else
q <= din;
end if;
end if;
end process;
end architecture second;
Parallel Register
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity P_reg is
port (din : in std_logic_vector(7 downto 0);
clk, rst: in std_logic;
q: out std_logic_vector(7 downto 0));
end entity P_reg;
architecture first of P_reg is
begin
process (rst, clk)
begin
P-reg
if (rst = ‘1’) then
q <= (others=>’0’);
elsif (rising_edge(clk)) then
q <= din;
end if;
end process;
end architecture first;
rst

y x q
Solved din q
y
Problem DFF

Variable clk
z
• entity circuit_1 is
• port (x,y,clk,rst: in std_logic;
• q: out std_logic);
• end entity circuit_1;
• architecture rtl of circuit_1 is
• Signal din :std_logic;
• begin
• process (clk,rst)
• begin
• if (rst =’1’)then
Variable • q <= ‘0’;
• elsif (rising_edge(clk)) then
• din <= x XOR y;
• q <= din;
• End if;
• End process;
• End rtl;
Variable

rst rst

x y
din q q
din q
dout
y
DFF DFF

clk clkclk
z
Variable
architecture rtl of circuit_1 is
begin
process (clk,rst)
variable din :std_logic;
begin
if (rst =’1’)then
q <= ‘0’;
elsif (rising_edge(clk)) then
din := x XOR y;
q <= din;
End if;
End process;
End rtl;

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