Is SCC 2024 Advance Program

DRAFT 11-22-2023 IEEE SOLID-STATE CIRCUITS SOCIETY
NEW
Corporations &
2024 IEEE
SAN FRANCISCO
FEBRUARY
Exhibition
THIS YEAR!
Research Institutions
SOLID-STATE
ADVANCE
INTERNATIONAL
18, 19, 20, 21, 22

CONFERENCE THEME:
MARRIOTT MARQUIS HOTEL

PROGRAM
ICS FOR A BETTER WORLD

CIRCUITS CONFERENCE
SUNDAY ALL-DAY THURSDAY ALL-DAY
2 FORUMS: E FFICIENT C HIPLETS AND D IE - TO -D IE C OMMUNICATIONS ; E NERGY-E FFICIENT AI-C OMPUTING S YSTEMS FOR L ARGE -L ANGUAGE M ODELS
4 FORUMS: ANALOG CIRCUITS; INTELLIGENT SENSING
OWER AMPS; DIGITALLY-ASSISTED VOLTAGE; CIRCUIT DESIGN 2.5D/3D; POWER MANAGEMENT; PLL TECHNIQUES;
5 - D AY 10 TUTORIALS: SCALABLE L5OW- D-PAY FREQUENCY SYNTHESIS; HIGHLY-INTEGRATED TRANSCEIVERS
CIRCUITS FOR RESILIENCE SIDE CHANNEL; CT ADCS; 3D FLASH MEMORY; DOMAIN-SPECIFIC ACCELERATORS; TRANSCEIVERS FOR COMM/SENSING
PROGRAM
PROGRAM 2 EVENING EVENTS: GRADUATE STUDENT RESEARCH IN PROGRESS; MENTORING / NETWORKING SESSION SHORT-COURSE: MACHINE LEARNING HARDWARE
ISSCC VISION STATEMENT
The International Solid-State Circuits Conference is the foremost global forum for
presentation of advances in solid-state circuits and systems-on-a-chip. The
Conference offers a unique opportunity for engineers working at the cutting edge of
IC design and application to maintain technical currency, and to network with leading
experts.
CONFERENCE TECHNICAL HIGHLIGHTS

On Sunday, February 18th, the day before the official opening of the Conference, ISSCC
2024 offers:
• A choice of 10 Tutorials, or
• A choice of 1 of 2 all-day Advanced-Circuit-Design Forums:
“Efficient Chiplets and Die-to-Die Communications”
“Energy-Efficient AI-Computing Systems for Large-Language Models”
The 90-minute tutorials offer background information and a review of the basics in specific
circuit- and system-design topics. In the all-day Advanced-Circuit-Design Forums, leading
experts present state-of-the-art design strategies in a workshop-like format. The Forums
are targeted at designers experienced in the technical field.
On Sunday, February 18th, there are two events: “Mentoring Session / Networking Bingo”
will be offered starting at 4:00 pm. In addition, the Student-Research Preview, featuring
ninety-second introductory presentations followed by a poster session from selected
graduate-student researchers from around the world will begin at 8:00 pm. The SRP will
start with an inspirational lecture by Dr. Ian Young (Intel).
On Monday, February 19th, ISSCC 2024 at 8:30 am offers four plenary papers on the theme:
“ICs for a Better World”. On Monday at 1:30 pm, there are five parallel technical sessions,
followed by a Social Hour at 5:15 pm open to all ISSCC attendees. The Social Hour, held
in conjunction with Book Displays and Author Interviews, will also include a Demonstration
Session, two selected papers: “Career Trajectories: Sharing our Paths to Success”, and
“Mixed Foundry Chiplets? Opportunities and Challenges”.
On Tuesday, February 20th , there are five parallel technical sessions, both morning and
afternoon. Book Displays and Author Interviews will be accompanied by a second
Demonstration Session. Tuesday evening includes two events, entitled: “Generative AI for
Chip Design” and “The Legacy of Gordon Moore”.
On Wednesday, February 21st , there will be five parallel technical sessions, both morning
and afternoon, followed by Author Interviews.
On Thursday, February 22nd, ISSCC offers a choice of five all-day events:

• A Short Course entitled:
“Machine Learning Hardware: Considerations and Accelerator Approaches”
• Four Advanced-Circuit-Design Forums entitled:
“Digitally Enhanced Analog Circuits: Trends & State-of-the-Art Designs”
“Intelligent Sensing”
“Recent Developments in High-Performance Frequency Synthesis Circuits
and Systems”
“Toward Next Generation of Highly Integrated Electrical
and Optical Transceivers”
This year, again, there is an option that allows an attendee to sample parts of all 5 Thursday
offerings. Registration for educational events on Sunday and Thursday will be filled on a
first-come first-served basis. Use of the ISSCC Web-Registration Site
(http://www.isscc.org) is strongly encouraged. Registrants will be provided with immediate
confirmation on registration for the Conference, Tutorials, Forums, and the Short Course.
Need Additional Information? Go to: www.isscc.org

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TABLE OF CONTENTS
Circuit Insights....................................................................................................................4
Tutorials...........................................................................................................................5-9
FORUMS
F1 Efficient Chiplets and Die-to-Die Communications ...........................................................10
F2 Energy-Efficient AI-Computing Systems for Large-Language Models .......................11
EVENING EVENTS
Mentoring Session/Networking Bingo Event ....................................................................12
EE1 Student Research Preview: Short Presentations with Poster Session..............................12
PAPER SESSIONS
1 Plenary ........................................................................................................................13-14
2 Processors and Communication SoCs ..............................................................................15
3 Analog Techniques ............................................................................................................16
4 High Performance Transceivers and Transmitters for Communication and Ranging.........17
5 Wireless RF and mm-Wave Receiver Techniques..............................................................18
6 Imagers and Ultrasound....................................................................................................19
7 Ultra-High-Speed Wireline ................................................................................................20
Demonstration Session 1.......................................................................................................21

EVENING EVENTS
Rising Stars 2024 Workshop ...........................................................................................22
EE2 Career Trajectories: Sharing Our Paths to Success ..........................................................23
EE3 Mixed-Foundry Chiplets? Opportunities and Challenges..................................................24
PAPER SESSIONS
8 Hybrid DC-DC Converters .................................................................................................25
9 Noise-Shaping and SAR ADCs ..........................................................................................26
10 Frequency Synthesis .........................................................................................................27
11 Industry Invited.................................................................................................................28
12 Electromagnetic Interface ICs for Information and Power.................................................29
13 High-Density Memory and Interfaces................................................................................30
14 Digital Techniques for System Adaptation, Power Management and Clocking ..................31
15 Embedded Memories & Ising Computing .........................................................................32
16 Security: From Processors to Circuits...............................................................................33
17 Emerging Sensing and Computing Technologies ..............................................................34
18 High-Performance Optical Transceivers ............................................................................35
19 RF to mm-Wave Oscillators and Multipliers ......................................................................36
Demonstration Session 2.......................................................................................................37
EVENING EVENTS
EE4 Generative AI for Chip Design .........................................................................................38
EE5 The Legacy of Gordon Moore..........................................................................................38
PAPER SESSIONS
20 Machine Learning Accelerators .........................................................................................39
Conference Timetable ......................................................................................................40-41
PAPER SESSIONS
21 Audio Amplifiers ...............................................................................................................42
22 High-Speed Analog-to-Digital Converters .........................................................................43
23 Energy-Efficient Connectivity Radios ................................................................................44
24 D-Band/Sub-THz Transmitters and Sensors......................................................................45
25 Invited: Innovations from Outside the (ISSCC’s) Box ........................................................46
26 Display and User Interaction Technologies .......................................................................47
27 Wireless Power .................................................................................................................48
28 High-Density Power Management.....................................................................................49
29 ICs for Quantum Technologies ..........................................................................................50
30 Domain-Specific Computing and Digital Accelerators .......................................................51
31 Power Converter Techniques.............................................................................................52
32 Power Amplification and Signal Generation ......................................................................53
33 Intelligent Neural Interfaces and Sensing Systems ...........................................................54
34 Compute-In-Memory ........................................................................................................55
SHORT COURSE
SC Machine Learning Hardware:.......................................................................................56-58
Considerations and Accelerator Approaches
FORUMS
F3 Digitally Enhanced Analog Circuits ....................................................................................59
Trends & State-of-the-Art Designs
F4 Intelligent Sensing.............................................................................................................60
F5 Recent Developments in High-Performance Frequency ....................................................61
Synthesis Circuits and Systems
F6 Toward Next Generation of Highly Integrated Electrical.....................................................62
and Optical Transceivers
Committees.......................................................................................................................63-73
Conference Information ....................................................................................................74-78
Conference Space Layout ......................................................................................................79
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CIRCUIT INSIGHTS Saturday, February 17th, 9:00 AM
ISSCC 2024 Circuit Insights
Organizer/Moderator:
Ali Sheikholeslami, University of Toronto, Toronto, Canada
ISSCC Education Chair
ISSCC 2024 offers the third edition of its Circuit Insights on Saturday, Feb. 17,
2024, 9:00am - 4:00pm PST. As in the past two years, this event is targeting 3rd-
and 4th-year undergraduate students and starting graduate students in the area
of circuit design but may be of interest to new circuit design engineers as well.
The event will be held in person for a small audience of 50 students (by invitation
only) at the ISSCC venue at the Marriott Hotel in San Francisco, and will be
recorded for later release on the SSCS/ISSCC YouTube channel.
The event consists of four 60-minute talks on fundamentals of Circuit Design,

each to be followed by a 15-minute Q&A Session, with a 1-hour networking lunch
after the second talk.
Agenda
Time Topic
8:30 AM Coffee
9:00 AM Opening Remarks
Ali Sheikholeslami, Circuit Insights Organizer/Moderator
9:05 AM Welcoming Remarks
Eugenio Cantatore, ISSCC Conference Chair
John Long, SSCS President
9:15 AM Fundamentals of Digital Circuit Design
Jan Rabaey, University of California, Berkeley, CA
10:15 AM Interactive Q & A
10:30 AM Break
10:45 AM CMOS Circuits for Biomedical Applications
Carolina Mora-Lopez, imec, Leuven, Belgium
11:45 AM Interactive Q & A
12:00 PM Networking Lunch
1:00 PM The Basics of Radio Frequency (RF) Circuits
Hossein Hashemi, University of Southern California, CA
2:00 PM Interactive Q & A
2:15 PM Break
2:30 PM The Basics of Silicon-Photonic Circuits
Sudip Shehkar, University of British Columbia, Canada
3:30 PM Interactive Q & A
3:45 PM Attendees Feedback/Quiz
4:00 PM Conclusion
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TUTORIALS Sunday, February 18th, 8:30 AM
8:30 AM
T1: Process-Scalable Low-Power Amplifiers
Minkyu Je
KAIST, Daejeon, Korea
Dynamic amplifiers have received increasing interest in state-of-the-art systems

due to their superior power efficiency and scalability with technology. They have,
for example, found many applications in low-power ADCs as error/residue
amplifiers or loop filters. This tutorial will introduce various types of dynamic
and ring amplifiers. Their conventional structures and basic operational
principles will be explained, and a diverse range of topologies, as well as
corresponding design tradeoffs, will be described. The effects of PVT variations
on their performance and design considerations will also be discussed. Through
this tutorial, attendees will obtain a solid understanding of the basics of dynamic
and ring amplifiers, including design choices, tradeoffs, and considerations,
along with an overview of recent developments.
Minkyu Je received the B.S., M.S., and Ph.D. degrees from KAIST, Korea. He is
now an Associate Professor in the School of Electrical Engineering at KAIST,
Korea. His research areas are circuits for sensor interfaces, wireless
communication, and power management, as well as microsystem integration.
He is an editor of 1 book, an author of 6 book chapters, and has more than 300
peer-reviewed international conference and journal publications. He also has
more than 50 patents issued or filed. He has served on the TPC for ISSCC, SOVC,
and A-SSCC. He was a Distinguished Lecturer of the CASS.
8:30 AM
T2: Fundamentals of Digital and Digitally Assisted
Linear Voltage Regulators
Arijit Raychowdhury
Georgia Institute of Technology, Atlanta, GA
Linear voltage regulators, including low-dropout (LDO) regulators, are a popular

choice for on-die voltage regulation in SoC processors. Although analog LDOs
have been used in supply-sensitive applications over the years, there has been
a recent resurgence in research and development of all-digital and digitally
assisted LDOs targeted for digital applications. In some of these topologies,
traditional design metrics such as power-supply rejection or load regulation are
often traded-off for higher energy efficiency and performance during large
current and voltage transients, as well as a wide dynamic operating range. This
tutorial introduces the fundamentals of all-digital and digitally assisted LDOs and
then presents recent advances in circuit topologies. While highlighting the trade-
offs between digital and analog LDOs, this presentation covers key metrics such
as the transient response, current efficiency, dropout-voltage requirements, and
stability via analysis of theoretical control models. Finally, this tutorial explores
circuit topologies to unify voltage and clock frequency regulation, to allow
designers to reduce voltage guardbands in digital circuits.
Arijit Raychowdhury is the Steve W. Chaddick School Chair in the School of

Electrical and Computer Engineering (ECE) at Georgia Tech. He is currently the
director of the Center for the Co-Design of Cognitive Systems (CoCoSys), a Joint
University Microelectronics Program 2.0. Prior to joining Georgia Tech,
Raychowdhury held research positions at Intel Corporation for six years and at
Texas Instruments for one-and-a-half years. His research interests include low-
power digital and mixed-signal circuit design, design of specialized accelerators,
power converters, signal processors, and exploring the interactions of circuits
with device technologies. He has published over 350 peer-reviewed articles. He
and his students have over 16 best-paper awards and several research awards
and fellowships. Raychowdhury is a Fellow of IEEE.
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8:30 AM
T3: Fundamentals of Circuit Design
for 2.5D/3D Integration
Kenny C. H. Hsieh
TSMC, Hsinchu, Taiwan
Chiplets and 2.5D/3D integration schemes allow performance and yield beyond
monolithic approaches. This tutorial covers advanced packaging technologies
and the new capabilities they enable. Circuit techniques suitable for side-by-side
and stacked integration will be reviewed, including mitigation of inter-symbol-
interferences, timing alignment between data and forwarded clocks, shielding
against crosstalk, and integrity of power-delivery networks. An example system
achieving throughput of 11Tb/s along one millimeter die edge is demonstrated.
Kenny Hsieh is deputy director in TSMC’s Design-Technology-Platform

organization (DTP) in Hsinchu, Taiwan, where he leads groups responsible for
mixed-signal and RF solutions. He joined TSMC in 2013 after working in SerDes
design teams at LSI (now Broadcom) and Xilinx (now AMD) in California, USA,
for about 15 years in total. Prior to those experiences, Kenny designed SRAM
and DRAM. He is now serving on the wireline subcommittee of ISSCC.
10:30 AM
T4: Fundamentals of Power Management Systems:
Constraints and Solutions
Frank Praemassing
Infineon Technologies Austria AG, Villach, Austria
Power management systems are partitioned across fine-grained power domains

to meet low-power requirements and efficient power-distribution requirements.
This tutorial provides an overview of the power-management systems for
scalable power domains in modern microcontrollers, including the standby
controller subsystem, system startup, power- and clock-generation
infrastructure, component monitoring, and power-management integrated-circuit
(PMIC) interface. Additionally, concepts are presented to ensure reliable system
start-up behavior under demanding power-sequencing conditions.
Frank Praemassing received the Dipl.-Ing. degree in electrical engineering from

the University of Bochum, Germany, in 1998. He then continued his PhD studies
at the University of Duisburg-Essen and graduated in 2004. Since 2003 he has
worked at Infineon in the field of on-chip voltage regulators for MCUs. He is
currently Distinguished Engineer with a focus on system resources, which
include power- and clock-management, standby controllers, and system-mode
management. He is also involved in innovating R&D methodology, particularly
in the area of power and signal integrity for mixed-signal analog IP at the SoC
and package level.
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10:30 AM
T5: Calibration Techniques in PLLs
Salvatore Levantino
Politecnico di Milano, Milano, Italy
Digitally assisted PLLs have become the mainstream solution to design lower
jitter and more agile clock generators in modern CMOS processes. In this
tutorial, after introducing the basics of adaptive filtering, we describe some of
the calibration techniques for low-jitter fast-switching frequency synthesizers.
These include techniques to correct for digital-time-converter (DTC) gain errors
and nonlinearity, to calibrate loop bandwidth, and to speed up lock transients.
The tutorial will discuss the issues in the practical implementation of the different
approaches and present some state-of-the-art examples.
Salvatore Levantino is a professor at Politecnico di Milano, Italy. He co-authored
the textbook Integrated Frequency Synthesizers for Wireless Systems,
Cambridge University Press, 2007. He is a member of the TPC of the ISSCC and
ESSCIRC. He was an IEEE Distinguished Lecturer for the Solid-State Circuits
Society in 2018 and 2019, served on the Steering Committee and the TPC for
the IEEE RFIC Symposium from 2012 to 2018, as Guest Editor for the IEEE JSSC
in 2016, and as an Associate Editor for IEEE TCAS-I in 2014 and 2015 and IEEE
TCAS-II in 2012 and 2013.
10:30 AM
T6: Recent Circuit Advances for Resilience
to Side-Channel Attacks
Shreyas Sen
Purdue University, West Lafayette, IN
Computationally secure cryptographic algorithms, when implemented on
physical hardware, leak correlated physical signatures (e.g. power supply
current, electromagnetic radiation, acoustic, thermal) which could be utilized to
break the crypto engine. Physical-layer countermeasures, guided by
understanding of the physical leakage, including circuit-level and layout-level
countermeasures promise strong resilience by reducing the physical leakage at
the source of the leakage itself. The past decade has seen significant
advancements in circuit-level countermeasures, advancing resilience to side-
channel attacks. In this tutorial, we will cover the fundamentals of the leakages
and how each countermeasure increases resilience, by diving into the working
mechanism of each and comparing the pros and cons of these techniques. The
tutorial concludes by highlighting the open problems and future needs of this
field.
Shreyas Sen is an Elmore Associate Professor of ECE & BME, Purdue University
and the Founder and CTO of Ixana. His current research interests span mixed-
signal circuits/systems and electromagnetics for the Internet of Bodies (IoB) and
Hardware Security. He has authored/co-authored 3 book chapters, over 200
journal and conference papers and has 20 patents granted/pending. Dr. Sen
serves as the Director of the Center for Internet of Bodies (C-IoB) at Purdue. His
work has been covered by 250+ news releases worldwide, including invited
appearances on TEDx Indianapolis, multiple Television shows (CNBC, NASDAQ
live) and podcasts. Dr. Sen is a recipient of the 2018 MIT TR35 India Award,
2022 Georgia Tech 40 Under 40 Award, NSF CAREER Award 2020, AFOSR Young
Investigator Award 2016, NSF CISE CRII Award 2017, Intel Outstanding
Researcher Award 2020, Google Faculty Research Award 2017, Purdue CoE Early
Career Research Award 2021, Intel Labs Quality Award 2012 for industry-wide
impact on USB-C type, Intel Ph.D. Fellowship 2010, IEEE Microwave Fellowship
2008, GSRC Margarida Jacome Best Research Award 2007, and nine best paper
awards including IEEE CICC 2019, 2021 and in IEEE HOST from 2017 to 2020,
for four consecutive years. Dr. Sen’s work was chosen as one of the top-10
papers in the Hardware Security field (TopPicks 2019). He serves/has served as
an Associate Editor for IEEE Solid-State Circuits Letters (SSC-L), Nature
Scientific Reports, Frontiers in Electronics, IEEE Design & Test, and as a TPC
member of ISSCC, CICC, CCS, DAC, IMS, DATE, ISLPED, ICCAD, among others.
Dr. Sen is a Senior Member of IEEE.
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TUTORIALS Sunday, February 18th, 1:30 PM
1:30 PM
T7: Fundamentals of Continuous-Time ADCs
Shanthi Pavan
IIT Madras, Chennai, India
This tutorial provides a comprehensive overview of continuous-time analog-to-

digital converters (ADCs), with a focus on the principles and architectures behind
these devices. We start with an introduction to the basics of sampling and
quantization, before delving into the operation of continuous-time ADCs. We
cover various architectures, including continuous-time pipeline ADCs and
continuous-time multistage noise-shaping (MASH) converters, and explain the
trade-offs and design considerations for each. The tutorial provides intuitive
explanations of the underlying principles, making it accessible to beginners while
also providing valuable insights for more experienced designers. By the end of
this tutorial, participants will have a solid understanding of continuous-time
ADCs and their underlying principles.
Shanthi Pavan is the Alexander Chair Professor of Electrical Engineering at the

Indian Institute of Technology, Madras. He is co-author of “Understanding Delta-
Sigma Modulators (second edition)” which received the Outstanding
Professional Book Award from IEEE Press in 2020. Shanthi has received
numerous awards for his work, including the Outstanding Forum Presenter at
ISSCC 2021. He serves on the Technical Program Committee (TPC) of ISSCC
and on the editorial boards of the IEEE Journal of Solid-State Circuits and Solid-
State Circuits Letters. He is a Fellow of the IEEE.
1:30 PM
T8: 3D Flash Memory from Technology to the System:
Past, Present and Future Developments
Violante Moschiano
Intel, Rome, Italy
Meeting the increasing demand for non-volatile memory in a range of critical

applications has required improving memory cost, performance, and power
consumption. Moving from 2D to 3D NAND has become critical for meeting
these requirements. Substantial density increase is enabled by wafer-level
stacking of more than 300 layers and by multi-level cells via threshold-voltage
scaling, with up to 5bits/cell. But, such stacking and threshold-voltage control
introduce sensitivities to reliability and variations, which impact overall system
performance and must be managed with smart circuit design. This tutorial covers
the fundamentals of 3D NAND flash, describing the main blocks and major
design approaches that have led to the most recent innovations in the field. The
tutorial goes on to describe tradeoffs between the components that impact
system operation, with intuition on how component-level metrics (tread, tprog,
trigger rate) translate to system requirements (MB/s, IOPS, QoS). The tutorial
concludes by overviewing and introducing future trends in flash memory to
provide perspectives on the evolution of NAND over the next decade.
Violante Moschiano is a Senior Director and Senior Principal Design Engineer

at Intel. He received a master’s degree in electronic engineering from the
University of Naples “Federico II” (Italy) in 2003. In 2004, he joined Micron
Technology (Avezzano, Italy), where he spent 18 years involved in NAND flash
memory, contributing to the development of important innovation in the field.
Violante has authored over 300 U.S. Patents and Applications, and has published
papers in key IEEE conferences. He has served on the ISSCC ITPC in the memory
subcommittee since 2020.
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TUTORIALS Sunday, February 18th, 3:30 PM
3:30 PM
T9: Domain-Specific Accelerators:
From Hardware to Systems
Sophia Shao
UC Berkeley, Berkeley, CA
Domain-specific accelerators have become a key component in today’s systems-

on-chip (SoCs) and systems-on-package (SoPs), driving active research and
product development to build novel accelerators for emerging applications such
as machine learning, robotics, cryptography, and many more. This tutorial will
discuss challenges and opportunities for the next generation of domain-specific
accelerators, with a special focus on system-level implications of designing,
integrating, and scheduling of future heterogeneous platforms. Specifically, we
will cover: hardware optimization for efficient accelerator design; state-of-the-
art SoC integration protocols (AXI, TileLink, CXL); and runtime system design
to dynamically manage accelerator and shared resources at the system level.
Sophia Shao is an Assistant Professor of EECS at UC Berkeley. Previously, she

was a Senior Research Scientist at NVIDIA and received her Ph.D. degree in 2016
from Harvard University. Her research interests are in the area of computer
hardware, with a special focus on domain-specific architecture, deep-learning
accelerators, and design methodology. Her work has been awarded a Best Paper
Award at MICRO’2019, a Best Paper Award at DAC’2021, a Best Paper Award at
JSSC’2021, a Research Highlight of CACM (2021), Top Picks in Computer
Architecture (2014), and two Honorable Mentions (2019).
3:30 PM
T10: Fundamentals of Transceivers
for Communication and Sensing
Giuseppe Gramegna
imec, Leuven, Belgium
Wireless communication and radar systems are ubiquitous, and integrating both
together is an active recent area of research. This tutorial will cover the basics
of wireless communication and FMCW/PMCW/OFDM radar, while adopting a
unified language and approach to encompass both communication and sensing
topics. The advantages and disadvantages of existing transceiver architectures
and beamforming implementations for communication and sensing will be
explained, while MIMO radar will be introduced and compared with a
beamforming approach. A few building blocks common to communication and
radar systems will be described. Finally, a communication implementation will
be compared with several radar architectures to provide insights into the
challenges of adding sensing functionality to a communication system.
Giuseppe Gramegna, MS (1993) and Ph.D (1996), started his career at imec
and later worked on low-noise CMOS front-ends and GPS SoCs at
STMicroelectronics until 2008. Following that, he held leadership positions at
Nemerix, CSR, and Samsung, where he led the development of fully integrated
GPS and BT/WiFi chipsets until 2015. He then moved to Huawei, where he
contributed to the design of 5G mm-wave Radios. In 2018, he joined RFS as
R&D Director. Since 2021, he is at imec, focusing his research on phased-array
communication and sensing architectures for 6G. Giuseppe has served on the
Technical Program Committee (TPC) for IEEE ESSCIRC from 2005 to 2018 and
the TPC for ISSCC (RF sub-committee) from 2017 to 2018. Since 2021, he has
been serving on the ISSCC TPC (Wireless sub-committee). He has co-authored
numerous papers and patents in the field of communication and sensing
architectures.
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FORUM 1 Sunday, February 18th, 8:30 AM
Efficient Chiplets and Die-to-Die Communications
Organizers: Shidhartha Das, AMD, Cambridge, United Kingdom
John Wuu, AMD, Fort Collins, CO
Co-Organizers: Yvain Thonnart, CEA-List, Grenoble, France

Hugh Mair, MediaTek, Austin, TX
Champions: Fatih Hamzaoglu, Intel, Hillsboro, OR

Kostas Doris, NXP, Eindhoven, The Netherlands
Maturation of 2.xD/3D technologies has triggered a revolution in computing

through chiplet-based heterogeneous integration of disparate process
technologies and computing architectures. Beyond yield enhancement, the
integration of general-purpose computing, domain-specific accelerators and
cutting-edge memory technologies enables opportunities for substantial
performance and energy-efficiency gains. System modularity drives a greater
emphasis on standardized energy-efficient chip-to-chip communication
necessitating cross-domain innovations across process technology, system
architectures and transceiver design while guaranteeing link performance under
adverse power delivery and thermal ambient conditions. This forum will feature
expert technologists and architects who will describe the SotA and the future
trends for technology, heterogeneous computing architectures and chip-to-chip
communications, covering the whole spectrum of challenges from protocol
definitions to emerging technologies, circuit design and test.
Agenda
Time Topic
8:00 AM Breakfast
8:15 AM Introduction
John Wuu, AMD, Fort Collins, CO
8:25 AM Advanced CMOS and Packaging Technology for Multi-Chiplet
and Trillion Transistor 3DIC System-in-Package by 2030
Geoffrey Yeap, TSMC, Hsinchu, Taiwan
9:15 AM The Packaging and Interconnect Requirements of the IC
Industry’s Chiplet-Based Future
Sam Naffziger, AMD, Fort Collins, CO
10:05 AM Break
10:20 AM Do Chiplets Open the Space for Emerging Memory
in the HPC System?
Gouri Sankar Kar, IMEC, Leuven, Belgium
11:10 AM In-Memory Computing Chiplets for Future AI Accelerators
Echere Iroaga, EnCharge AI, Santa Clara, CA
12:00 PM Lunch
1:20 PM Efficient Domain-Specific Compute with Chiplets
Dejan Marković, UCLA, Los Angeles, CA
2:10 PM Innovations in Chiplet Interconnects, Protocols and the
Path to Standardization
Lihong Cao, ASE US, Austin, TX
3:00 PM Break
3:15 PM Photonics for Die-to-Die Interconnects: Links and Optical
I/O Chiplets
Chen Sun, Ayar Labs, Santa Clara, CA
4:05 PM Robust Circuit/Architecture Co-Design for Chiplet Integration
Wen-Chou Wu, MediaTek, Hsinchu, Taiwan
4:55 PM Closing Remarks
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FORUM 2 Sunday, February 18th, 8:30 AM
Energy-Efficient AI-Computing Systems
for Large-Language Models
Organizers: Eric Karl, Intel, Portland, OR
Jun-Seok Park, Samsung Electronics, Gyeonggi-do, Korea
Co-Organizers: Jae-sun Seo, Cornell Tech, New York, NY

Yongpan Liu, Tsinghua University, Beijing, China
Champions: Vivek De, Intel, Hillsboro, OR
Alicia Klinefelter, NVIDIA, Durham, NC
Large-language models (LLMs), such as ChatGPT and Bard, recently gained
tremendous attention by demonstrating astonishing capabilities in recognizing,
summarizing, translating, predicting, and generating text and other content based
on extensive knowledge from massive datasets. As LLMs serve as a crucial tool
for human-to-machine communication, these models are driving a paradigm shift
in the capabilities and possibilities for AI computing. The enormous energy
consumption for the LLM training and inference has emerged as the key limitation
to future AI computing.
This forum presents the current and next generation circuits, architectures, and
systems for high-performance computing (HPC) to address the energy-efficiency
challenges associated with LLMs. This includes GPU and HPC systems, cloud
server SoCs, accelerators, high-bandwidth access to storage, in-package high-
bandwidth memory, and DRAM processing in memory. Furthermore, this forum
explores LLM quantization techniques to enable next-generation mobile SoCs for
LLM inference. This forum welcomes experts across industry and research
organizations to present innovations to enable future energy-efficient AI-
computing systems for LLMs.
Agenda
Time Topic
8:00 AM Breakfast
Eric Karl, Intel, Portland, OR
8:25 AM A Brief History of Large Language Models...
and a glimpse into the future
Larry Heck, Georgia Tech, Atlanta, GA
9:15 AM LLM Training and Inference on GPU & HPC Systems
Mohammad Shoeybi, NVIDIA, Santa Clara, CA
10:05 AM Break
10:20 AM Cloud Processors for LLM Inference
Sailesh Kottapalli, Intel, Santa Clara, CA
11:10 AM LLMs Energy Problem (and what we can do about it)
Sushma Prasad, Google, Sunnyvale, CA
12:00 PM Lunch
1:20 PM Latency Processing Unit for Acceleration of Large-Language-
Model Inference
Joo-Young Kim, KAIST, Daejeon, Korea
HyperAccel, Gyeonggi-do, Korea
2:10 PM High-Bandwidth Memory and Processing-in-Memory in the Era
of Generative AI
Kyomin Sohn, Samsung, Hwaseong, Korea
3:00 PM Break
3:15 PM Quantizing LLMs for Efficient Inference at the Edge
Bram Verheof, Axelera, Eindhoven, The Netherlands
4:05 PM Next-Generation Mobile Processors with Large-Language
Models (LLMs) and Large Multimodal Models (LMMs)
Bor-Sung Liang, MediaTek, Hsinchu City, Taiwan
11
EVENING EVENT Sunday, February 18th
Mentoring Session/Networking Bingo Event
(Open to all Attendees)
4:00 - 6:00 PM
Women in Circuits (WiC) together with ISSCC will be holding a networking and mentoring
session on Sunday afternoon. Distinguished panelists from the “Sharing Our Paths to
Success” panel, WiC members, and other participants will play getting-to-know-you bingo
to promote engagement between various members of the community. This will give
participants the chance to network and mingle with people across a spectrum of seniority
in the field in a casual setting. This event is open to all ISSCC attendees and the public.
EE1: Student Research Preview (SRP)

8:00 PM
The Student Research Preview (SRP) will highlight selected student research projects
in progress. The SRP consists of 23 ninety-second presentations followed by a Poster
Session, by graduate students from around the world, which have been selected on the
basis of a short submission concerning their on-going research. Selection is based on
the technical quality and innovation of the work. This year, the SRP will be presented in
three theme sections: 1) 5G+, Satcom, Optical and Quantum Circuits, 2) Advances in
Power, Data Conversion, and Frequency Synthesis Techniques, and 3) Cutting-edge
Processing and Sensing Techniques.
The SRP will include an inspirational lecture by Dr. Ian Young (Intel). SRP begins at
8:00 pm on Sunday, February 18th. It is open to all ISSCC registrants.
SRP ORGANIZING COMMITTEE

Co-Chair: Jerald Yoo, National University of Singapore, Singapore
Co-Chair: Mondira (Mandy) Pant, Intel, MA
Advisor: Anantha Chandrakasan, Massachusetts Institute of Technology,
MA
Advisor: Jan Van der Spiegel, University of Pennsylvania,
Philadelphia, PA
Media/Publications: Laura Fujino, University of Toronto, Toronto, Canada
A/V: Trudy Stetzler, Halliburton, Houston, TX
COMMITTEE MEMBERS
Utsav Banerjee, IISC, India
Po-Hung Chen, National Chiao Tung University,Taiwan
Woo-Seok Choi, Seoul National University, Korea
Sijun Du, Delft University of Technology, The Netherlands
Antoine Frappe, University of Lille, France
Hao Gao, Eindhoven University of Technology, The Netherlands
Preet Garcha, Texas Instruments, TX
Minkyu Je, KAIST, Korea
Matthias Kuhl, University of Freiburg, Germany
Jaydeep Kulkarni, University of Texas at Austin, TX
Jiamin Li, Southern University of Science and Technology, China
Xilin Liu, University of Toronto, Toronto, Canada
Noriyuki Miura, Osaka University, Japan
Phillip Nadeau, Analog Devices, MA
Mondira Pant, Intel, MA
Negar Reiskarimian, Massachusetts Institute of Technology, MA
Chutham Sawigun, imec, Belgium
Atsushi Shirane, Tokyo Institute of Technology, Japan
Mahsa Shoaran, EPFL, Switzerland
Yildiz Sinangil, Apple, CA
Mahmut Sinangil, Nvidia, CA
Filip Tavernier, KU Leuven, Belgium
Chia-Hsiang Yang, National Taiwan University, Taiwan
Lita Yang, Meta, CA
Rabia Tugce Yazicigil, Boston University, MA
Jerald Yoo, National University of Singapore, Singapore
Milin Zhang, Tsinghua University, China
12
SESSION 1 Monday, February 19th, 8:30 AM
Plenary Session — Invited Papers
Chair: Eugenio Cantatore, Eindhoven University of Technology,
Eindhoven, The Netherlands
ISSCC Conference Chair
Associate Chair: Frank O’Mahoney, Intel, Hillsboro, OR

ISSCC International Technical-Program Chair
FORMAL OPENING OF THE CONFERENCE 8:30 AM
1.1 Semiconductor Industry: Present & Future 8:45 AM

Kevin Zhang, Senior Vice President, Business Development
& Overseas Operations Office,
Taiwan Semiconductor Manufacturing Company
Semiconductors are the foundation of today’s digital economy and are powering
innovations that will shape the trajectory of human history. This paper highlights
the latest progress of the semiconductor industry to support a vast spectrum of
applications that have forever changed our lives. It gives insight into the paths of
continued advanced technology scaling, the essential role of design-technology
co-optimization (DTCO), and how system-level integration will elevate system
performance to new heights. The advancements of semiconductors will enable
many new innovations in artificial intelligence (AI), high-performance computing
(HPC), wireless connectivity, and autonomous driving. The paper also provides
the trends of technologies ranging from low-power and edge AI devices to cloud-
based computing. By harnessing the new capabilities of semiconductors, these
innovations will greatly improve productivity, efficiency, safety, as well as
sustainability. The semiconductor industry is indeed experiencing a “golden era”
in spurring remarkable economic growth and unleashing innovations to create a
better future for society.
1.2 Racing Down the Slopes of Moore’s Law 9:20 AM

Bram Nauta, Professor & Head IC Design Group,
University of Twente
During the past decades, Moore’s law has been the driving force for IC design.
Although during the early decades, “everything” seemed to have gotten better, in
the meantime, we have lost scaling of processor clock speed and RF transistor
speed, and now it looks like power efficiency of digital gates will stall. What
remains is scaling in transistor count, thanks to 3D integration.
Thus, this is an excellent moment to reconsider how we design for analog- and
digital-signal processing. The higher the required signal-to-noise, the more power-
efficient digital signal processing is compared to analog. Pure analog processing
remains more efficient only for ~30dB SNR or less. Thus, the conversion from
analog-to-digital should be made as early in the chain as possible. Thanks to the
figure-of-merit race, analog-to-digital converters have experienced a tremendous
win in power efficiency. However, these ADCs require a large input voltage swing
while the input signals to be converted, such as from an antenna or sensor
interface, are usually much smaller. Therefore, RF and analog fron-tends are
needed, which consume much more power than the ADCs to be driven.
Let us re-think these analog front-ends. Can we still efficiently design these front-
ends in future CMOS? Do we need so much linear amplification? Do we need
active linear circuits at all? Can we not use “digital” components to replace analog
front-ends and AD converters?
ISSCC, SSCS, IEEE AWARD PRESENTATIONS 9:55 AM
BREAK 10:20 AM
13
SESSION 1 Monday, February 19th, 10:40 AM
1.3 Computing in the Era of Generative AI 10:40 AM
Jonah Alben, Senior Vice President, GPU Engineering
NVIDIA
Generative AI has captured the imagination of users across multiple industries,
and we have only begun to tap the potential of this amazing technology. GenAI
applications can create text, computer code, protein sequences, images, video,
rendered 3D graphics, music, with more generation types being constantly
added. The combination of high compute demands, and the real-time
requirements of many GenAI-based applications requires design thinking at data-
center scale. This paper will cover the breadth of technology innovations, from
circuits to silicon to software to data center, needed to enable today’s latest
supercomputers for GenAI, and discuss our experiences applying GenAI to
various business sectors.
1.4 Fueling Semiconductor Innovation 11:15 AM

and Entrepreneurship in the Next Decade
Lip-Bu Tan, Chairman of Walden International,
Founding Managing partner of Walden Catalyst Ventures,
Senior Advisor & former CEO Cadence Design
This paper provides a comprehensive overview of the future of semiconductor
technology, focusing on the interplay between innovation and entrepreneurship.
It is organized into sections that discuss the current state of the semiconductor
industry, the role of entrepreneurship in driving innovation, and the potential
future developments in this field. It highlights the virtuous cycle of innovation
and entrepreneurship, where advancements in semiconductor technology fuel
new business opportunities, which in turn drive further technological progress.
This cycle is crucial for the creation of the next generation of intelligent electronic
systems. The paper also explores the ‘stack’ of semiconductor technology, from
materials and design to manufacturing and generative AI applications. It
establishes that there are beneficial relationships between these different parts
of the stack, with advancements in one area often enabling progress in others.
This interconnectedness underscores the importance of a holistic approach to
innovation in the semiconductor industry, where advancements in different parts
of the stack can collectively drive the industry forward.
PRESENTATION TO PLENARY SPEAKERS 11:50 AM
CONCLUSION 11:55 AM
14
SESSION 2 Monday, February 19th, 1:30 PM
Processors and Communication SoCs
Session Chair: Shidhartha Das, Advanced Micro Devices, Cambridge,
United Kingdom
Session Co-Chair: Sugako Otani, Renesas Electronics, Kodaira, Japan
1:30 PM
2.1 A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU
Subsystem-Based 5G Mobile SoC
A. Varma1, S. Gururajarao1, H. Chen1, T. Chen1, G. Gammie1, H. Mair2, J-H. Yang3,
H-H. Yu3, S-C. Chang3, C-H. Yang3, L-A. Huang3, K. Ramanathan1, R. Halli4, E. Ho1,
T-W. Hung3, S-Y. Hsueh3, L. Li3, A. Thippana1, E. Wang3, S. Hwang3
1
MediaTek, Austin, TX; 2MediaTek, Dallas, TX; 3MediaTek, Hsinchu, Taiwan
4
MediaTek, Bengaluru, India
1:55 PM
2.2 “Zen 4c”: The AMD 5nm Area-Optimized x86-64 Microprocessor Core
T. Burd1, S. Venkataraman*1, W. Li*1, T. Johnson1, J. Lee1, S. Velaga1, M. Wasio1,
T. Yiu1, F. Bodine1, M. McCabe1, U. Salim1, S. K. Thouta1, M. Golden1,
S. Ramachandran 1, G. S. L. Devi1, J. Wuu2, Y. Kuszczak3, G. Singla3, C. Henrion2,
A. Robison2, S. Balagangadharan4, U. Nair4, N. Srivastava4, H. Prasad4,
M. Polimetla4, P. Chennupati4, E. Gupta4, M. Vykuntam4, S. Sarkar4,
P. K. Duvvuru4, T. Mardi4, S. G4; 1AMD, Santa Clara, CA; 2AMD, Fort Collins, CO
3
AMD, Markham, Canada; 4AMD, Bangalore, India
*Equally Credited Authors (ECAs)
2:20 PM
2.3 Emerald Rapids: 5th-Generation Intel® Xeon® Scalable Processors
A. O. Munch1, N. Nassif1, C. L. Molnar1, J. Crop2, R. Gammack1, C. P. Joshi3,
G. Zelic1, K. Munshi1, M. Huang4, C. R. Morganti2, S. Kandula1, A. Biswas1
1
Intel, Hudson, MA; 2Intel, Fort Collins, CO; 3Intel, Hillsboro, OR
4
Intel, Santa Clara, CA
2:45 PM
2.4 ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency
Critical Applications
C-H. Yu, H-E. Kim, S. Shin, K. Bong, H. Kim, Y. Boo, J. Bae, M. Kwon, K. Charfi,
J. Kim, H. Kim, M. Shim, C. Ha, W. Shin, J-S. Yoon, M. Chi, B. Lee, S. Choi,
D. Kim, J. Woo, S. Yoon, H. Jo, H. Kim, H. Heo, Y-J. Jin, J. Yu, J. Lee, H. Kim,
M. Kang, S. Choi, S-G. Kim, M. Choi, J. Oh, Y. Kim, H. Kim, S. Je, J. Ham,
J. Yoon, J. Lee, S. Park, Y. Park, J. Lee, B. Hong, J. Ryu, H. Ko, K. Chung,
J. Choi, S. Jung, Y. F. Arthanto, J. Kim, H. Cho, H. Jeong, S. Choi, S. Han, J. Park,
K. Lee, S-I. Bae, J. Bang, K-J. Lee, Y. Jang, J. Park, S. Park, J. Park, H. Shin,
S. Park, J. Oh, Rebellions, Seongnam-si, Korea
Break 3:10 PM
3:35 PM
2.5 A 28nm Physical-Based Ray-Tracing Rendering Processor for
Photorealistic Augmented Reality with Inverse Rendering and
Background Clustering for Mobile Devices
S. Guo1, S. Sapatnekar2, J. Gu1
1
Northwestern University, Evanston, IL; 2University of Minnesota, Minneapolis, MN
4:00 PM
2.6 A 131mW 6.4Gb/s 256×32 Multi-User MIMO OTFS Detector for Next-
Gen Communication Systems
T. Lee, T-Y. Chen, I-H. Liu, C-H. Yang, National Taiwan University, Taipei, Taiwan
4:25 PM
2.7 BayesBB: A 9.6Gb/s 1.61ms Configurable All-Message-Passing
Baseband-Accelerator for B5G/6G Cell-Free Massive-MIMO in 40nm
CMOS
Y. Zhang*1,2, W. Zhou*1,2, Y. Zhang1,2, H. Ji1,2, Y. Huang1,2, X. You1,2, C. Zhang1,2
1
Southeast University, Nanjing, China
2
Purple Mountain Laboratories, Nanjing, China
4:50 PM
2.8 A 21.9ns 15.7Gb/s/mm2 (128, 15) BOSS FEC Decoder for 5G/6G URLLC
Applications
D. Kam1, S. Yun1, J. Choe1, Z. Zhang2, N. Lee3, Y. Lee1
1
Pohang University of Science and Technology, Pohang, Korea
2
University of Michigan, Ann Arbor, MI; 3Korea University, Seoul, Korea
Conclusion 5:15 PM
15
Analog Techniques
Session Chair: Jiawei Xu, Fudan University, Shanghai, China
Session Co-Chair: Jens Anders, University of Stuttgart, Stuttgart, Germany
1:30 PM
3.1 A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/°C
from -20°C to 125°C
P. Park1, J. Lee2, S. Cho1
1
Korea Advanced Institute of Science and Technology, Daejeon, Korea
2
Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea
1:55 PM
3.2 A 0.028mm2 32MHz RC Frequency Reference in 0.18μm CMOS with
±900ppm Inaccuracy from −40°C to 125°C and ±1600ppm Inaccuracy
After Accelerated Aging
S. Pan1, Y. Cheng1, G. Wu1, Z. Wang1, K. A. A. Makinwa2, H. Wu1
1
Tsinghua University, Beijing, China
2
Delft University of Technology, Delft, The Netherlands
2:20 PM
3.3 A 0.5V 6.14μW Trimming-Free Single-XO Dual-Output Frequency
Reference with [5.1nJ, 120μs] XO Startup and [8.1nJ, 200μs]
Successive-Approximation-Based RTC Calibration
R. Luo1, K-M. Lei1, R. P. Martins1,2, P-I. Mak1
1
University of Macau, Macau, China; 2University of Lisboa, Lisbon, Portugal
2:45 PM
3.4 A 14b 98Hz-to-5.9kHz 1.7-to-50.8μW BW/Power Scalable Sensor
Interface with a Dynamic Bandgap Reference and an Untrimmed Gain
Error of ±0.26% from -40°C to 125°C
Z. Tang*1, Y. Liu*1, P. Chen1, H. Wang1, X. Yu2, K. A. A. Makinwa3, N. N. Tan1
1
Vango Technologies, Hangzhou, China; 2Zhejiang University, Hangzhou, China
3
Break 3:10 PM
3:35 PM
3.5 A 4mW 45pT/√Hz Magnetoimpedance-Based ΔΣ Magnetometer with
Background Gain Calibration and Short-Time CDS Techniques
I. Akita1, S. Tatematsu2, 1AIST, Tsukuba, Japan; 2Aichi Steel, Tokai, Japan
4:00 PM
3.6 An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all
over 129.5dB Dynamic Range for Electrochemical Biosensing
M. A. Akram1, A. Aberra 1, S-J. Kweon2, S. Ha1,3
1
New York University Abu Dhabi, Abu Dhabi, United Arab Emirates
2
The Catholic University of Korea, Bucheon, Korea
3
New York University, New York, NY
4:25 PM
3.7 A β-Compensated NPN-Based Temperature Sensor with ±0.1°C (3σ)
Inaccuracy from -55°C to 125°C and a 200fJ∙K2 Resolution FoM
N. G. Toth, K. A. A. Makinwa, Delft University of Technology, Delft, The Netherlands
4:50 PM
3.8 A 0.65V 900μm2 BEoL RC-Based Temperature Sensor with ±1°C
Inaccuracy from -25°C to 125°C
B-S. Lien*, S. L. Liu*, W-L. Lai, Y-C. Lu, Y-C. Peng, K-H. Hsieh
5:05 PM
3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit
SAR ADC Using 3nm GAA’s 0.7V Thin-Gate-Oxide Transistor
S. Lee, J. Park, J. Park, S. Lee, J. Lee, Y. Cho, M. Choi, J. Shin
Samsung Electronics, Hwaseong, Korea
5:20 PM
3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper
Instrumentation Amplifier with an Input-Boosted First Stage in
22nm/180nm CMOS
X. Xu*1, S. Ye*1, Y. Luan1, J. Gao1, J. Li1, J. Cui1, H. Zhang2, R. Huang1, L. Shen1,
L. Ye1,3
1
Peking University, Beijing, China
2
Nano Core Chip Electronic Technology, Hangzhou, China
3
Advanced Institute of Information Technology of Peking University, Hangzhou, China
Conclusion 5:35 PM
16
SESSIONS 4 Monday, February 19th, 1:30 PM
High Performance Transceivers and Transmitters for
Communication and Ranging
Session Chair: Alireza Zolfaghari, Broadcom, Laguna Hills, CA
Session Co-Chair: Yuanjin Zheng, Nanyang Technological University,
Singapore, Singapore
1:30 PM
4.1 A 79.7μW Two-Transceiver Direct-RF 7.875GHz UWB Radar SoC in 40nm
CMOS
N. Andersen1, S. Bagga1, J. A. Michaelsen1, H. A. Hjortland1, L. Leene1, T. Skår1,
E. Stenersen1, D. T. Wisland1,2
1
Novelda, Oslo, Norway
2
University of Oslo, Oslo, Norway
1:55 PM
4.2 A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving -46dB
TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal
J. Lee, J. Jang, W. Lee, B. Suh, H. Yoo, B. Park, J. Woo, J. Jang, I. Ryu, H. Han,
J. Kim, B. Kang, M. Kang, H. Kang, J. Kang, M. Lee, D. Lee, H. Son, S. Lee, S. Kim,
H. Park, S. Lee, J. Bae, H. Kim, J. Lee, S. Yoo
2:20 PM
4.3 A 43mm2 Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver
with 24RX/3TX Supporting Inter-Band 7CA/5CA 4×4 MIMO with 1K-QAM
J. Bae, S. Lee, J. Lee, I. Jo, H. Kim, K. Yoon, T. Kim, J. Lee, M. Lee, J. Lee, J. Jeong,
S. Lee, T. Kim, S. Kim, G. Cho, D. Kim, S. Lee, P. Jang, E. Yang, J. Song, G. Park,
S-E. Choi, J. Son, W. Ko, J. Kim, S. H. Park, S. Lee, Y. Lee, E. Park, P. Kang, T. Kim,
H. Lee, B. Han, J. Lee, J. Lee, S. Yoo
2:45 PM
4.4 A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3
Duty-Cycle LO Signals for Harmonic Rejection
J. Li*1, Z. Li*1, Y. Yin1, C. Yan1, N. Qi2, M. Liu1, H. Xu1
1
Fudan University, Shanghai, China
2
Chinese Academy of Sciences, Beijing, China
3:00 PM
4.5 A Reconfigurable, Multi-Channel Quantized-Analog Transmitter with
<-35dB EVM and <-51dBc ACLR in 22nm FDSOI
J. Zhong1, K. Vasilakopoulos2, A. Liscidini1
1
University of Toronto, Toronto, Canada
2
Analog Devices, Toronto, Canada
Break 3:15 PM
17
Wireless RF and mm-Wave Receiver Techniques
Session Chair: Wu-Hsin Chen, Qualcomm, San Diego, CA
Session Co-Chair: Ho-Jin Song, Pohang University of Science and
Technology, Pohang, Korea
3:35 PM
5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle
LO and IQ-Leakage Suppression
H. Xu1,2, J. Bi1, T. Zou1, W. He1, Y. Zeng1, J. Gu1, Z. Jiao1, S. Liu3, Z. Zhu3, N. Yan1,2
1
2
Jiashan-Fudan Joint Research Institute, Jiaxing, China
3
Xidian University, Xi’an, China
4:00 PM
5.2 0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna
and BB Achieving +14/+16.5dBm 3rd/5th IB Harmonic B1dB
S. Araei, S. Mohin, N. Reiskarimian
Massachusetts Institute of Technology, Cambridge, MA
4:25 PM
5.3 A 0.072mm2 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a
Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection
in 28nm CMOS
M. Ayesh, S. Mahapatra, C. Yang, M-W. Chen
University of Southern California, Los Angeles, CA
4:50 PM
5.4 A 22.4-to-30.7GHz Phased-Array Receiver with Beam-Pattern
Null-Steering and Beam-Tracking Techniques Achieving >30.2dB
OTA-Tested Spatial Rejection
Y. Yu, B. Sun, M. Geng, C. Zhao, H. Liu, Y. Wu, J. Zhang, K. Kang
University of Electronic Science and Technology of China, Chengdu, China
5:15 PM
5.5 A Stacking Mixer-First Receiver Achieving >20dBm Adjacent-Channel
IIP3 Consuming less than 25mW
S. van Zanten, R. van der Zee, B. Nauta
University of Twente, Enschede, The Netherlands
Conclusion 5:30 PM
18
Imagers and Ultrasound
Session Chair: Andreas Suess, OMNIVISION, San Jose, CA
Session Co-Chair: Masaki Sakakibara, Sony Semiconductor Solutions
Corporation, Atsugi-shi, Kanagawa, Japan
1:30 PM
6.1 12Mb/s 4×4 Ultrasound MIMO Relay with Wireless Power and
Communication for Neural Interfaces
E. So, A. Arbabian, Stanford University, Stanford, CA
1:55 PM
6.2 An Ultrasound-Powering TX with a Global Charge-Redistribution
Adiabatic Drive Achieving 69% Power Reduction and 53° Maximum
Beam Steering Angle for Implantable Applications
M. Gourdouparis1,2, C. Shi1, Y. He1, S. Stanzione1, R. Ukropec3, P. Gijsenbergh3,
V. Rochus3, N. Van Helleputte3, W. Serdijn2, Y-H. Liu1,2
1
imec, Eindhoven, The Netherlands
2
Delft University of Technology, Delft, The Netherlands; 3imec, Leuven, Belgium
2:20 PM
6.3 Imager with In-Sensor Event Detection and Morphological
Transformations with 2.9pJ/pixel×frame Object Segmentation FOM for
Always-On Surveillance in 40nm
J. Vohra, A. Gupta, M. Alioto, National University of Singapore, Singapore, Singapore
2:45 PM
6.4 A Resonant High-Voltage Pulser for Battery-Powered Ultrasound Devices
I. Bellouki1, N. Rozsa1, Z-Y. Chang1, Z. Chen1, M. Tan1,2, M. Pertijs1
1
2
SonoSilicon, Hangzhou, China
3:00 PM
6.5 A 0.5°-Resolution Hybrid Dual-Band Ultrasound Imaging SoC for UAV
Applications
J. Guo1, J. Feng1, S. Chen1, L. Wu1, C-W. Tsai1,2, Y. Huang1, B. Lin1, J. Yoo1,2
1
National University of Singapore, Singapore, Singapore
2
The N.1 Institute for Health, Singapore, Singapore
Break 3:15 PM
3:35 PM
6.6 A 10,000 Inference/s Vision Chip with SPAD Imaging and Reconfigurable
Intelligent Spike-Based Vision Processor
X. Yang*1, F. Lei*1, N. Tian*1, C. Shi2, Z. Wang1, S. Yu1, R. Dou1, P. Feng1, N. Qi1,
J. Liu1, N. Wu1, L. Liu1, 1Chinese Academy of Sciences, Beijing, China
2
Chongqing University, Chongqing, China; *Equally Credited Authors (ECAs)
4:00 PM
6.7 A 160×120 Flash LiDAR Sensor with Fully Analog-Assisted In-Pixel
Histogramming TDC Based on Self-Referenced SAR ADC
S-H. Han1, S. Park1, J-H. Chun2,3, J. Choi2,3, S-J. Kim1
1
Ulsan National Institute of Science and Technology, Ulsan, Korea
2
Sungkyunkwan University, Suwon, Korea; 3SolidVue, Seongnam, Korea
4:25 PM
6.8 A 256×192-Pixel 30fps Automotive Direct Time-of-Flight LiDAR Using 8×
Current-Integrating-Based TIA, Hybrid Pulse Position/Width Converter,
and Intensity/CNN-Guided 3D Inpainting
C. Zou1, Y. Ou1, Y. Zhu1, R. P. Martins1,2, C-H. Chan1, M. Zhang1
1
University of Macau, Macau, China
2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal
4:50 PM
6.9 A 0.35V 0.367TOPS/W Image Sensor with 3-Layer Optical-Electronic
Hybrid Convolutional Neural Network
X. Wang*, Z. Huang*, T. Liu, W. Shi, H. Chen, M. Zhang
Tsinghua University, Beijing, China; *Equally Credited Authors (ECAs)
5:05 PM
6.10 A 1/1.56-inch 50Mpixel CMOS Image Sensor with 0.5μm pitch
Quad Photodiode Separated by Front Deep Trench Isolation
D. Kim, K. Cho, H-C. Ji, M. Kim, J. Kim, T. Kim, S. Seo, D. Im, Y-N. Lee, J. Choi,
S. Yoon, I. Noh, J. Kim, K. J. Lee, H. Jung, J. Shin, H. Hur, K. E. Chang, I. Cho,
K. Woo, B. S. Moon, J. Kim, Y. Ahn, D. Sim, S. Park, W. Lee, K. Kim, C. K. Chang,
H. Yoon, J. Kim, S-I. Kim, H. Kim, C-R. Moon, J. Song
Samsung Semiconductor, Hwaseong, Korea
5:20 PM
6.11 A 320x240 CMOS LiDAR Sensor with 6-Transistor nMOS-Only SPAD
Analog Front-End and Area-Efficient Priority Histogram Memory
M. Kim*1, H. Seo*1,2, S. Kim1, J-H. Chun1,2, S-J. Kim3, J. Choi*1,2
1
Sungkyunkwan University, Suwon, Korea; 2SolidVue, Seongnam, Korea
3
Conclusion 5:35 PM
19
Ultra-High-Speed Wireline
Session Chair: Didem Turker Melek, Cadence, San Jose, CA
Session Co-Chair: Masum Hossain, Carleton University, Ottawa, Canada
1:30 PM
7.1 A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical
Direct-Detect Application in 5nm FinFET
J. Q. Wang1, A. Tan1, A. Iyer1, A. Fan2, A. Farhoodfar1, B. Alnabulsi3, B. Smith3, C. Loi4,
C. R. Ho1, D. Cartina5, J. Riani1, J. Casanova1, K. Raviprakash1, L. Patra1, L. Wang1,
M. Bachu1, S. Ray1, S. Chong4, S. Dallaire3, T. Nguyen1, T-F. Wu2, V. Giridharan1,
V. Gurumoorthy1, X. Ding4, Y. Yin1, Z. Sun4, S. Jantzi2, L. Tse1
1
Marvell, Santa Clara, CA; 2Marvell, Irvine, CA; 3Marvell, Ottawa, Canada
4
Marvell, Singapore, Singapore; 5Marvell, Burnaby, Canada
1:55 PM
7.2 A 224Gb/s sub-pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm
FinFET
M. Cusmai1, N. Familia1, E. Kuperberg1, M. Nashash1, D. Gottesman1, D. Kumar2,
Z. Marcus1, Y. Horwitz1, S. Zalcman1, J. Kim3, S. Kundu3, I. Radashkevich1, Y. Segal1,
D. Lazar1, U. Virobnik1, M. P. Li4, A. Cohen1
1
Intel, Jerusalem, Israel; 2Intel, Bangalore, India; 3Intel, Hillsboro, OR
4
Intel, San Jose, CA
2:20 PM
7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS
D. Pfaff1, M. Nummer1, N. Hai2, P. Xia2, K. G. Yang2, M-M. Mohsenpour1,
M-A. LaCroix1, B. Zamanlooy3, T. Eeckelaert1, D. Petrov1, M. Haroun1, C. Dick2,
A. Zaman1, H. Mei1, S. Moazzeni1, T. Shakir1, C. Carvalho1, H. Huang1, P. Kumari1,
R. Mason1, F. Brishty2, I. Jaffri2
1
Synopsys, Ottawa, Canada; 2Synopsys, Mississauga, Canada
3
Synopsys, Markham, Canada
2:45 PM
7.4 A 0.027mm2 5.6-to-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling
PLL Scoring 220.3fsrms Jitter and −74.2dBc Reference Spur
Y. Huang1, Y. Chen1, Z. Yang2, R. P. Martins1,3, P-I. Mak1
1
2
Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China
3
University of Lisboa, Lisboa, Portugal
Break 3:10 PM
3:35 PM
7.5 A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB
Equalization for 800GbE/1.6TbE
X. Luo1, X. You1, Z. Li1, H. Mosalam1, D. Xu1, T. Fan1, H. Qiao1, W. Zhou1, H. Wu1,
L. Zhong1, P. Y. Chiang2, Q. Pan1
1
Southern University of Science and Technology, Shenzhen, China
2
4:00 PM
7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with
31dB Loss Compensation in 28nm CMOS
L. Zhong*, H. Wu*, Y. Zhang*, X. Cheng, W. Wu, C. Wang, X. Luo, T. Fan, D. Xu,
Q. Pan, Southern University of Science and Technology, Shenzhen, China
4:25 PM
7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b
ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm
CMOS
Y-P. Lin*, P-J. Peng*, C-C. Lu, P-T. Shen, Y-C. Jao, P-H. Hsieh
National Tsing Hua University, Hsinchu, Taiwan; *Equally Credited Authors (ECAs)
4:50 PM
7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-to-14GHz and
-54.4dBc Spurs Under 50mV Supply Noise
M. A. Khalil, M. B. Younis, R. Xia, A. E. Abdelrahman, T. Wang, K-S. Park,
P. K. Hanumolu, University of Illinois, Urbana, IL
5:05 PM
7.9 An 8b 6-to-12GHz 0.18mW/GHz DC Modulated Ramp-Based Phase
Interpolator in 65nm CMOS Process
S. Mohapatra, E. Afshar, Z. Zhou, D. Heo, Washington State University, Pullman, WA
Conclusion 5:20 PM
20
Demonstration Session 1, Monday February 19th, 5:00-7:00 PM
This year, the Demonstration Session extending in selected regular papers, both Academic and Industrial,
will take place on Monday February 19th, and Tuesday February 20th, from 5 pm until 7 pm in the Golden
Gate Hall. These demonstrations will feature real-life applications made possible by new ICs presented at
ISSCC 2024, as noted by the symbol DS1
List to Come
21
RISING STARS Monday February 19th, 6:30 PM
Rising Stars 2024 Workshop
Organizers: Preet Garcha, TI, Dallas, TX

Ulkuhan Guler, WPI, Worcester, MA
Co-Organizers: Sally Amin, Intel, Hillsboro, OR

Dilara Caygara, BU, Boston, MA
Vanessa Chen, CMU, Pittsburgh, PA
Zeynep Deniz, IBM Research, Yorktown Heights, NY
Najme Ebrahimi, University of Florida, Gainesville, FL
Dina Eldamak, GUC, Cairo, Egypt
Yasemin Engur, EPFL, Lausanne, Switzerland
Soumya Gupta, OSU, Corvallis, OR
Ping-Hsuan Hsieh, NTHU, Hsinchu, Taiwan
Yaoyao Jia, UT Austin, Austin, TX
Elpida Karapepera, University of Washington, Seattle, WA
Kwantae Kim, ETH Zürich, Zürich, Switzerland
Rabia Yazicigil Kirby, BU, Boston, MA
Deeksha Lal, pSemi, Raleigh, NC
Shalini Lal, pSemi, Raleigh, NC
Fatemeh Marefat, Keysight Technologies, Santa Clara, CA
Aishwarya Natarajan, Hewlett Packard Labs, Milpitas, CA
Sirma Orguc, MIT, Cambridge, MA
Negar Reiskarimian, MIT, Cambridge, MA
Kamala R. Sadagopan, Qualcomm, San Diego, CA
Farhana Sheikh, Intel, Hillsboro, OR
Trudy Stetzler, Houston, TX
Alice Wang, UTD, Richardson, TX
Miaorong Wang, Tenstorrent, Cambridge, MA
Kathy Wilcox, AMD, Boxborough, MA
Wanghua Wu, Samsung Semiconductor, San Jose, CA
Advisors: Anantha Chandrakasan, MIT, Cambridge, MA

Ingrid Verbauwhede, KU Leuven, Leuven, Belgium
The IEEE SSCS Women in Circuits, together with ISSCC, is sponsoring the “Rising
Stars 2024 Workshop” for outstanding students and young professionals in
Electrical Engineering and Computer Science. We will be selecting 24 bright minds
from both academia and industry, with a holistic approach to diversity. The
workshop includes a special dinner, keynote from IEEE Fellow Prof. Ingrid
Verbauwhede, and a poster session with lightning talks.
Additionally, established members of academia and industry will talk about their
unique journeys in a career panel: “Sharing our Paths to Success”, touching upon
educational choices, research pursuits, skill development, networking, work-life
balance, effective transitioning between academia and industry, and more. The
panel is open to all ISSCC 2024 attendees and the public.
Panelists: Xiaolin Lu, TI, Dallas, TX

Kofi Makinwa, TU Delft, Delft, Netherlands
Kathleen Philips, imec, Eindhoven, Belgium
Heein Yoon, UNIST, Ulsan, Korea
22
EVENING EVENT Monday February 19th, 8:00 PM
EE2: Career Trajectories: Sharing Our Paths to Success
Organizers: Preet Garcha, TI, Dallas, TX
Ulkuhan Guler, WPI, Worcester, MA
Co-Organizers: Dilara Caygara, BU, Boston, MA

Najme Ebrahimi, University of Florida, Gainesville, FL
Yasemin Engur, EPFL, Lausanne, Switzerland
Soumya Gupta, OSU, Corvallis, OR
Elpida Karapepera, University of Washington, Seattle, WA
Alicia Klinefelter, NVIDIA, Durham, NC
Kamala R. Sadagopan, Qualcomm, San Diego, CA
Farhana Sheikh, Intel, Hillsboro, OR
Trudy Stetzler, Houston, TX
Alice Wang, UTD, Richardson, TX
Kathy Wilcox, AMD, Boxborough, MA
Advisors: Anantha Chandrakasan, MIT, Cambridge, MA

Ingrid Verbauwhede, KU Leuven, Leuven, Belgium
Moderators: Ulkuhan Guler, WPI, Worcester, MA

Preet Garcha, TI, Dallas, TX
This career panel event aims to provide a broader perspective on the potential
career options available in academia and industry. The panelists will share their
experiences, including the pivotal decisions they made, obstacles they
encountered, and lessons they learned along the way. They will address critical
topics such as educational choices, research pursuits, skill development,
networking, work-life balance, and effective transitioning between academia and
industry. Participants will gain a deeper understanding of the skills, qualifications,
and experiences necessary to excel in each domain, enabling them to make more
deliberate choices and develop effective career strategies.
Panelists: Xiaolin Lu, TI, Dallas, TX

Kofi Makinwa, TU Delft, Delft, Netherlands
Kathleen Philips, imec, Eindhoven, Belgium
Heein Yoon, UNIST, Ulsan, Korea
23
EVENING EVENT Monday February 19th, 8:00 PM
EE3: Mixed-Foundry Chiplets?
Opportunities and Challenges
Organizer: Eric Wang, TSMC, Hsinchu, Taiwan
Co-Organizers: Arijit Raychowdhury, Georgia Institute of Technology,

Atlanta, GA
Daniel Morris, Meta, Menlo Park, CA
Vito Giannini, Uhnder, Austin, TX
Yongpan Liu, Tsinghua University, Beijing, China
Moderator: Bryan Black, Chipletz, Spicewood, TX
One of the advantages of chiplets is the ability to integrate chiplets developed

from different manufacturing processes to realize SoCs with optimal
performance/$. An I/O chip, for instance, could be built by one foundry, the core
processor could be built by another foundry, and then those chips could be put
together on a package. With this, there’s potential for mixing and matching
chiplets from different foundries. To make this happen, many challenges need
to be overcome for the industry, including standardized interfaces between
chiplets, verification of whole SoCs using chiplets made from different
processes, design flows from multiple foundries, and reliability assurance,
including thermal and electromagnetic interactions between chiplets. A mixed-
foundry chiplet ecosystem will be crucial to facilitate productization of complex
systems-on-chiplet.
Panelists: Lalitha Immaneni, Intel, Tempe, AZ

Subramanian S. Iyer, CHIPS R&D Office, Los Angeles, CA
Yujun Li, TSMC, Hsinchu, Taiwan
Sam Naffziger, AMD, Fort Collins, CO
Cheolmin Park, Samsung, Hwaseong, Korea
Boyd Phelps, Cadence, Hillsboro, OR
Geert Van der Plas, imec, Leuven, Belgium
24
SESSION 8 Tuesday, February 20th, 8:00 AM
Hybrid DC-DC Converters
Session Chair:
Xin Zhang, IBM T. J. Watson Research Center, Yorktown Heights, NY
Session Co-Chair:
Lin Cheng, University of Science and Technology of China, Hefei, China
8:00 AM
8.1 A 94.5%-Peak-Efficiency 3.99W/mm2-Power-Density Single-Inductor Bipolar-
Output Converter with a Concise PWM Control for AMOLED Displays
J. Jin*1, W. Xu*2, L. Cheng1,2
1
University of Science and Technology of China, Hefei, China
2
Hefei CLT Microelectronics, Hefei, China; *Equally Credited Authors (ECAs)
8:25 AM
8.2 A 96.9%-Peak-Efficiency Bilaterally-Symmetrical Hybrid Buck-Boost
Converter Featuring Seamless Single-Mode Operation, Always-Reduced
Inductor Current, and the Use of All CMOS Switches
D-H. Kim, H-S. Kim, Korea Advanced Institute of Science and Technology, Daejeon, Korea
8:50 AM
8.3 A Li-ion-Battery-Input 1-to-6V-Output Bootstrap-Free Hybrid Buck-or-Boost
Converter Without RHP Zero Achieving 97.3% Peak Efficiency 6μs Recovery
Time and 1.13μs/V DVS Rate
J. Ruan1, J. Jiang2, C. Ding1, K. Yuan1, K. N. Leung3, X. Liu1
1
Chinese University of Hong Kong, Shenzhen, China
2
3
Chinese University of Hong Kong, Hong Kong, China
9:15 AM
8.4 A Fast-Transient 3-Fine-Level Buck-Boost Hybrid DC-DC Converter with
Half-Voltage-Stress on All Switches and 98.2% Peak Efficiency
S. Zhao1,2, C. Zhan2, Y. Lu1, 1University of Macau, Macau, China
2
9:30 AM
8.5 A 6nA Fully-Autonomous Triple-Input Hybrid-Inductor-Capacitor Multi-Output
Power Management System with Multi-Rail Energy Sharing, All-Rail Cold
Startup, and Adaptive Conversion Control for mm-Scale Distributed Systems
X. Liu, A. Agrawal, A. Tanaka, B. Calhoun, University of Virginia, Charlottesville, VA
Break 9:45 AM
10:05 AM
8.6 An Integrated Dual-side Series/Parallel Piezoelectric Resonator-Based
20-to-2.2V DC-DC Converter Achieving a 310% Loss Reduction
W-C. B. Liu1, G. Pillonnet2, P. P. Mercier1
1
University of California, San Diego, CA; 2CEA-Léti, Grenoble, France
10:30 AM
8.7 A 92.7% Peak Efficiency 12V-to-60V Input to 1.2V Output Hybrid DC-DC
Converter Based on a Series-Parallel-Connected Switched Capacitor
H-J. Choi1, C-H. Lee1, Y-J. Jeon1, H. Park1, J-H. Kim1, Y-J. Woo2, J-P. Hong2, H. Jin2,
S-W. Hong1, 1Sogang University, Seoul, Korea; 2LX Semicon, Seoul, Korea
10:55 AM
8.8 A 97.18% Peak-Efficiency Asymmetrically Implemented Dual-phase
(AID) Converter with a full Voltage-Conversion Ratio (VCR) Between 0
and 1
H-J. Park1, J-M. Cho1, C-H. Lee1, Y-J. Oh1, H. Jeong1, J-H. Yang2, J. Lee2, S-W. Hong1
1
Sogang University, Seoul, Korea; 2Samsung Electronics, Seoul, Korea
11:20 AM
8.9 A 96.5% Peak Efficiency Duty-Independent DC-DC Step-Up Converter with
Low Input-Level Voltage Stress and Mode-Adaptive Inductor Current
Reduction
M. Kim1, W. Jung1, H. Park1, J. Song1,2, Y. Ahn2, T. Nam2, Y. Shin2, Y-J. Woo2, H-M. Lee1
1
Korea University, Seoul, Korea; 2LX Semicon, Seoul, Korea
11:35 AM
8.10 A 5V-to-150V Input-Parallel Output-Series Hybrid DC-DC Boost Converter
Achieving 76.4mW/mg Power Density and 80% Peak Efficiency
S. Han1,2, Z. Fang1, Z. Tong1, X. Wu2, H. Jiang2, T. Ren2, Y. Lu1
1
University of Macau, Macau, China; 2Tsinghua University, Beijing, China
11:50 AM
8.11 A 48V-to-5V Buck Converter with Triple EMI Suppression Circuit Meeting
CISPR 25 Automotive Standards
Y-H. Kao1, C-S. Hung1, H-H. Chang1, W-C. Huang1, R-B. Guo1, H-Y. Tsai1, K-H. Chen1,
K-L. Zeng1,2, Y-H. Lin3, S-R. Lin3, T-Y. Tsai3
1
National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2
Chip-GaN Power Semiconductor, Hsinchu, Taiwan
3
Realtek Semiconductor, Hsinchu, Taiwan
Conclusion 12:05 PM
25
Noise-Shaping and SAR ADCs
Session Chair: Jongwoo Lee, Samsung Electronics, Hwaseong-si, Korea
Session Co-Chair: Hajime Shibata, Analog Devices, Toronto, Canada
8:00 AM
9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time
SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level
Shifting
S. Ye1, L. Shen1, J. Gao1, J. Li1, Z. Chen1, X. Xu1, J. Cui1, H. Zhang2, X. Zhang1, L. Ye1,3,
R. Huang1
1
2
3
8:25 AM
9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC Using
Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier
in 8nm
Y. Lim*, J. Lee*, J. Lee, K. Lim, S. Oh, J. Lee, S-U. Kwak
8:50 AM
9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared
Residue Integrating Amplifier Achieving 173dB FoMs
X. He, M. Gu, H. Jiang, Y. Zhong, N. Sun, L. Jie, Tsinghua University, Beijing, China
9:15 AM
9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC Using Cascode Capacitively
Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique
Z. Chen1, L. Shen1, S. Ye1, J. Gao1, J. Li1, J. Cui1, X. Xu1, Y. Luan1, H. Zhang2, L. Ye1,3,
R. Huang1
1
2
3
Break 9:40 AM
10:05 AM
9.5 A 118.5dBA DR 3.3mW Audio ADC with a Class-B Resistor DAC,
Non-Overlap DEM and Continuous-Time Quantizer
A. Subramanian, T. Halder, L. V. Tripurari, A. Kannan
Texas Instruments, Bangalore, India
10:30 AM
9.6 A 6th-Order Quadrature CTDSM Using Double-OTA and Quadrature NSSAR
with 171.3dB FoMs in 14nm
J. Lee, S-E. Cho, J. Lee, Y. Lim, S. Oh, J. Lee, S-U. Kwak
Samsung Electronics, Hwasung, Korea
10:55 AM
9.7 A 94.3dB SNDR 184dB FoMs 4th-Order Noise-Shaping SAR ADC with
Dynamic-Amplifier-Assisted Cascaded Integrator
K-C. Cheng1, S-J. Chang1, C-C. Chen2, S-H. Hung2
1
National Cheng Kung University, Tainan, Taiwan; 2Upbeat Technology, Taipei, Taiwan
11:20 AM
9.8 A 9.3nV/rtHz 20b 40MS/s 94.2dB DR Signal-Chain Friendly Precision SAR
Converter
R. Bodnar1,2, H. Kennedy1, C. P. Hurrell1, A. Ahmad1, M. Vickery1, L. Smithers1,
W. Buckley3, M. Dutt1, P. Delizia4, D. Hummerston1, P. Czapor3
1
Analog Devices, Newbury, United Kingdom
2
University of Southampton, Southampton, United Kingdom
3
Analog Devices, Limerick, Ireland; 4now at Vodafone, Newbury, United Kingdom
11:45 AM
9.9 A 2.75fJ/conv 13b 2MS/s SAR ADC Using Dynamic Capacitive
Comparator with Wide Input Common Mode
S. Lee, H. Kang, M. Lee
Gwangju Institute of Science and Technology, Gwangju, Korea
Conclusion 12:00 PM
26
Frequency Synthesis
Session Chair: Jun Yin, University of Macau, Taipa, Macau
Session Co-Chair: Yu-Li Hsueh, Mediatek, Hsinchu, Taiwan
8:00 AM
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-
Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM
M. Rossoni*, S. M. Dartizio*, F. Tesolin, G. Castoro, R. Dell’Orto, C. Samori,
A. L. Lacaita, S. Levantino, Politecnico di Milano, Milan, Italy
8:25 AM
10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N
Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm
S. Jang*1,2, M. Chae*1,2, H. Park*1,2, C. Hwang1,2, J. Choi2
1
2
Seoul National University, Seoul, Korea; *Equally Credited Authors (ECAs)
8:50 AM
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-
Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs
Integrated Jitter
D. Xu, Z. Liu, Y. Kuai, H. Huang, Y. Zhang, Z. Sun, B. Liu, W. Wang, Y. Xiong, J. Qiu,
W. Madany, Y. Zhang, A. A. Fadila, A. Shirane, K. Okada
Tokyo Institute of Technology, Tokyo, Japan
9:15 AM
10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur
BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and
Wandering Spurs
M. P. Kennedy1,2, V. Mazzaro1,2, S. Tulisi3, M. Scully3, N. McDermott3, J. Breslin3
1
University College Dublin, Dublin, Ireland
2
Microelectronic Circuits Centre Ireland, Dublin, Ireland
3
Analog Devices, Limerick, Ireland
9:30 AM
10.5 A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL
Using a Nonlinearity-Replication Technique
Y. Shin*1,2, J. Lee*1,2, J. Kim*1,2, Y. Jo1,2, J. Choi2
1
2
Seoul National University, Seoul, Korea; *Equally Credited Authors (ECAs)
Break 9:45 AM
10:05 AM
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz
rms Frequency Error Based on a Digital-PLL with a Non-Uniform
Piecewise-Parabolic Digital Predistortion
F. Tesolin*1, S. M. Dartizio*1, G. Castoro1, F. Buccoleri1, M. Rossoni1, D. Cherniak2,
C. Samori1, A. L. Lacaita1, S. Levantino1
1
Politecnico di Milano, Milan, Italy; 2Infineon Technologies, Villach, Austria
10:30 AM
10.7 An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051% rms
Frequency Error under a 2.3GHz Chirp Bandwidth, 2.3GHz/μs Slope, and
50ns Idle Time in 65nm CMOS
X. Wang*1,2, X. Ma*3, Y. Fu1, Y. Zhou1, A. Li1, S. Yang1, X. Wu1,2, D. Wang1,2, L. Li1,2,
X. You1,2
1
Southeast University, Nanjing, China; 2Purple Mountain Laboratories, Nanjing, China
3
Télécom SudParis, Paris, France; *Equally Credited Authors (ECAs)
10:55 AM
10.8 A 281GHz, −1.5dBm Output-Power CMOS Signal Source Adopting a
46fsrms Jitter D-Band Cascaded Subharmonically Injection Locked Sub-
Sampling PLL with a 274MHz Reference
B-T. Moon1,2, H-C. Park2, S-G. Lee1
1
2
11:20 AM
10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter,
−253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused
VCO-Buffer and a Type-I FLL with Rapid Phase Alignment
H. Li1, T. Xu1, X. Meng1, J. Yin1, R. P. Martins1,2, P-I. Mak1
1
2
Conclusion 11:45 AM
27
Industry Invited
Session Chair: Alicia Klinefelter, NVIDIA, Durham, NC
Session Co-Chair: Vivek De, Intel, Beaverton, OR
8:00 AM
11.1 AMD MI300 Modular Chiplet Platform – HPC and AI Accelerator
for Exa-Class Systems
A. Smith1, E. Chapman1, C. Patel1, R. Swaminathan1, J. Wuu2, T. Huang3, W. Jung3,
A. Kaganov3, H. McIntyre4, R. Mangaser5
1AMD, Austin, TX
2AMD, Fort Collins, CO
3AMD, Markham, Canada
4AMD, Santa Clara, CA
5AMD, Boxborough, MA
8:25 AM
11.2 A 3D Integrated Prototype System-on-Chip for Augmented Reality
Applications Using Face-to-Face Wafer-Bonded 7nm Logic at <10μm
Pitch with up to 40% Energy Reduction at Iso-Area Footprint
T. Wu, H. Liu, H. E. Sumbul, L. Yang, D. Baheti, J. Coriell, W. Koven, A. Krishnan,
M. Mittal, M. T. Moreira, M. Waugaman, L. Ye, E. Beigne
Meta, Sunnyvale, CA
8:50 AM
11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-
Efficient Inference at the Edge
P. A. Hager, B. Moons, S. Cosemans, I. A. Papistas, B. Rooseleer, J. Van Loon,
R. Uytterhoeven, F. Zaruba, S. Koumousi, M. Stanisavljevic, S. Mach,
S. Mutsaards, R. Khaddam Aljameh, G. H. Khov, B. Machiels, C. Olar, A. Psarras,
S. Geursen, J. Vermeeren, Y. Lu, A. Maringanti, D. Ameta, L. Katselas, N. Hütter,
M. Schmuck, S. Sivadas, K. Sharma, M. Oliveira, R. Aerne, N. Sharma, T. Soni,
B. Bussolino, D. Pesut, M. Pallaro, A. Podlesnii, A. Lyrakis, Y. Ruffiner, M. Dazzi,
J. Thiele, K. Goetschalckx, N. Bruschi, J. Doevenspeck, B. Verhoef, S. Linz,
G. Garcea, J. Ferguson, I. Koltsidas, E. Eleftheriou
Axelera AI, Eindhoven, The Netherlands
9:15 AM
11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm
Chip
A. S. Cassidy1, J. V. Arthur2, F. Akopyan3, A. Andreopoulos2, R. Appuswamy2,
P. Datta2, M. V. Debole2, S. K. Esser2, C. Ortega Otero2, J. Sawada1, B. Taba2,
A. Amir2, D. Bablani2, P. J. Carlson2, M. D. Flickner2, R. Gandhasri2, G. J. Garreau2,
M. Ito4, J. L. Klamo2, J. A. Kusnitz2, N. J. McClatchey1, J. L. McKinstry2,
Y. Nakamura4, T. K. Nayak2, W. P. Risk2, K. Schleupen3, B. Shaw2, J. Sivagnaname1,
D. F. Smith2, I. Terrizzano2, T. Ueda4, D. Modha2
1
IBM Research, Austin, TX
2
IBM Research, San Jose, CA
3
IBM Research, Yorktown, NY
4
IBM Research, Tokyo, Japan
Break 9:40 AM
28
Electromagnetic Interface ICs for Information and Power
Session Chair: Alyosha Molnar, Cornell University, Ithaca, NY
Session Co-Chair: Noriyuki Miura, Osaka University, Suita, Japan
10:05 AM
12.1 Monolithically Integrated Sub-63fJ/b 8-Channel 256Gb/s Optical
Transmitter with Autonomous Wavelength Locking in 45nm CMOS SOI
K. Omirzakhov, F. Aflatouni
University of Pennsylvania, Philadelphia, PA
10:30 AM
12.2 A mm-Wave/Sub-THz Synthesizer-Free Coherent Receiver with Phase
Reconstruction through Mixed-Signal Kramer-Kronig Processing
S. Ghozzy*, M. Allam*, E. A. Karahan, Z. Liu, K. Sengupta
Princeton University, Princeton, NJ
10:55 AM
12.3 A Scalable and Instantaneously Wideband 5GS/s RF Correlator Based on
Charge Thresholding Achieving 8-bit ENOB and 152 TOPS/W Compute
Efficiency
K. Rashed1, A. Undavalli2, S. Chakrabartty2, A. Nagulu2, A. Natarajan1
1
Oregon State University, Corvallis, OR
2
Washington University, St. Louis, MO
11:20 AM
12.4 A 19μW 200Mb/s IoT Tag Demonstrating High-Definition Video Streaming
via a Digital-Switch-Based Reconfigurable 16-QAM Backscatter
Communication Technique
Y. Zhang, R. Luo, J. Xiong, S. Liang, M. Meng
Tongji University, Shanghai, China
11:35 AM
12.5 A Packageless Anti-Tampering Tag Utilizing Unclonable Sub-THz Wave
Scattering at the Chip-Item Interface
E. Lee, X. Chen, M. Ashok, J. Won, A. Chandrakasan, R. Han
11:50 AM
12.6 A 64.4% Efficiency 5.8GHz RF Wireless Power Transfer Receiver with
GaAs E-pHEMT Rectifier and 45.2μs MPPT Time SIDITO Buck-Boost
Converter Using VOC Prediction Scheme
K. Ichikawa1, T. Iwata1, S. Onishi1, T. Higuchi1, Y. Hirose2, N. Sakai2, K. Itoh2,
K. Miyaji1
1
Shinshu University, Nagano, Japan
2
Kanazawa Institute of Technology, Nonoichi, Japan
Conclusion 12:05 PM
29
High-Density Memory and Interfaces
Session Chair: Dong-Kyun Kim, SK hynix, Icheon-si, Korea
Session Co-Chair: Hidehiro Shiga, KIOXIA, Yokohama, Japan
8:00 AM
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3
IO Circuitry
J. Yang*, H. Ko*, K. Kim, H. Park, J. Park, J-H. Kang, J. Cha, S. Kim, Y. Kim, M. Park, G. Lee,
K. Lee, S. Lee, G. Jeon, S. Jeong, Y. Joo, J. Cha, S. Hwang, B. Kim, S. Byeon, S. Lee, H. Park,
J. Cho, J. Kim, SK hynix Semiconductor, Icheon, Korea; *Equally Credited Authors (ECAs)
8:25 AM
13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a
5th-Generation 10nm DRAM process
I. Choi*, S. Hong, K. Kim, J-S. Hwang, S. Woo, Y-S. Kim, C-R. Cho, E-Y. Lee, H-J. Lee,
M-S. Jung, H-Y. Jung, J-S. Hwang, J-S. Yoon, W-M. Lim, H-J. Yoo, W-K. Lee, J-K. Oh,
D-S. Lee, J-E. Lee, J-H. Kim, Y-K. Kim, S-J. Park, B-K. Ho, B-W. Na, H-I. Choi, C-K. Lee, S-J. Lee,
H. Shin, Y-K. Lee, J-W. Ryu, S. Shin, S. Park, D. Lim, S-J. Bae, Y-S. Sohn, T-Y. Oh, S. Hwang
8:50 AM
13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal
Density and a 3.2GB/s High-Speed IO Rate
H. Kim, W. Jung, D-B. Kim, T-H. Kim, N. Lee, D. Shin, M. Kim, Y. Rho, H-J. Lee, Y. Hyun, J. Park,
T. Kim, H. Kim, G. Lee, J. Lee, J. Jang, J. Park, S. Kim, S. C. Jeon, S. Kim, J-H. Song, M-S. Kim,
T. Lee, B-K. Chun, T. Kim, Y. G. Lee, H. Lee, S. Lee, H. Lee, D. Cho, S-W. Nam, Y. Kim, K. Yoon,
Y. Lee, S. Kim, J. Hwang, R. Song, H. Jang, J. Son, H. Jeon, M. Lee, M. Lee, K. Kim, E. Lee,
M. Lee, S. Jo, C. H. Kim, J. C. Park, K. Yun, S. Seol, J-H. Cho, S. Lee, J-Y. Lee, S-H. Hur
9:15 AM
13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a
6-Phase RDQS Scheme for TSV Area Optimization
J. Lee*, K. Cho*, C. K. Lee, Y. Lee, J-H. Park, S-H. Oh, Y. Ju, C. Jeong, H. S. Cho, J. Lee, T-
S. Yun, J. H. Cho, S. Oh, J. Moon, Y-J. Park, H-S. Choi, I-K. Kim, S. M. Yang, S-Y. Kim, J. Jang,
J. Kim, S-H. Lee, Y. Jeon, J. Park, T-K. Kim, D. Ka, S. Oh, J. Kim, J. Jeon, S. Kim, K. T. Kim,
T. Kim, H. Yang, D. Yang, M. Lee, H. Song, D. Jang, J. Shin, H. Kim, C. Baek, H. Jeong, J. Yoon,
S-K. Lim, K. Y. Lee, Y. J. Koo, M-J. Park, J. Cho, J. Kim
SK hynix Semiconductor, Icheon, Korea; *Equally Credited Authors (ECAs)
Break 9:40 AM
10:05 AM
13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis
Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in
28nm CMOS
W. Wu*, H. Wu*, L. Zhong, X. Cheng, X. Luo, D. Xu, C. Wang, Z. Li, Q. Pan
10:30 AM
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization
and ZQ Calibration
S-Y. Cho, M-C. Choi, J. Baek, D. An, S. Kim, D. Lee, S. Yang, G-Y. Kang, J. Park, K. Lee, H-C. Jung,
G. Cho, C. Lee, H-R. Kim, Y-J. Shin, H. Park, S. Lee, J. Kim, B. Won, J. Mok, K. Kim, U. Lim,
H-J. Jin, Y. Lee, Y-T. Kim, H. Ha, J. Ahn, W. Sung, Y. Jang, H. Song, H. Ban, T. Park, T-Y. Oh,
C. Yoo, S. Hwang, Samsung Electronics, Hwasung, Korea
10:55 AM
13.7 A 1Tb Density 3b/Cell 3D-NAND Flash on a 2YY Tier Technology with a 300MB/s
Write Throughput
K. Kawai1, Y. Einaga1, Y. Oikawa1, Y. He2, B. Iorio3, S. Yamada1, Y. Kamata1, T. Iwasaki2,
A. D’alessandro3, E. Yu2, A. Muralidharan4, Q. Li2, H. Nguyen2, K-F. Chan2, M. Piccardi2,
T. Ichikawa1, J. Yu2, G. Wang2, K. Kim2, C. Kim2, P. Mangalindan4, H. Yun2, L. Nubile3, K. Verma2,
S. Bhushan2, D. Srinivasan2, H. Kuge1, R. Subramanian5, J. Kishimoto1, T. Kamijo1, P. Musunuri2,
C. Siau2, R. Ghodsi2, 1Micron Technology, Tokyo, Japan; 2Micron Technology, San Jose, CA
3
Micron Technology, Avezzano, Italy; 4Micron Technology, Folsom, CA
5
Micron Technology, Hyderabad, India
11:20 AM
13.8 A 1a∙nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with a WCK-Correction
Strategy, a Voltage-Offset Calibrated Receiver and Parasitic Capacitance
Reduction
Y. Seo*, J. Choi*, S. Cho, H. Han, W. Kim, G. Ryu, J. Ahn, Y. Cho, S. Choi, S. Lee, W. Lee, C. Lee,
K. Kim, S. Lee, S. Park, M. Choi, S. Lee, M. Kim, T. Shin, H. Jeong, H. Kim, H. Song, Y. Hong,
S. Yoon, G. Park, H. You, C. Choi, H-K. Jung, J. Cho, J. Kim
SK hynix, Icheon, Korea; *Equally Credited Authors (ECAs)
11:35 AM
13.9 A 25.2Gb/s/pin NRZ/PAM3 Dual-Mode Transmitter with Embedded Partial DBI
Achieving a 133% I/O Bandwidth/Pin Efficiency and a 19.3% DBI Efficiency
C. Han*, K-S. Lee*, J-H. Chae
Kwangwoon University, Seoul, Korea; *Equally Credited Authors (ECAs)
11:50 AM
13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration
and Equalization Schemes For Next-Generation Memory Interfaces and Chiplets
K. Seong, W. Oh, H. Lee, G. Bae, Y. Suh, H. Lee, J. Kim, E. Kim, Y. Kang, G. Mo, Y. Lee, M. Kim,
S. Lee, D. Park, B-J. Yoo, H-G. Rhew, J. Shin, Samsung Electronics, Hwaseong, Korea
Conclusion 12:05 PM
30
SESSION 14 Tuesday, February 20th, 1:30 PM
Digital Techniques for System Adaptation,
Power Management and Clocking
Session Chair: Yvain Thonnart, CEA-List, Grenoble, France
Session Co-Chair: Heein Yoon, Ulsan National Institute of Science and
Technology, Ulsan, Korea
1:30 PM
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited
Inference Performance in a 5nm AI SoC
M. Kar1, J. Silberman1, S. Venkataramani1, V. Srinivasan1, B. Fleischer1, J. Rubin1, J. Lancaster1,
S. K. Lee1, M. Cohen1, M. Ziegler1, N. Cao1, S. Woodward2, A. Agrawal1, C. Zhou1, P. Chatarasi1,
T. Gooding2, M. Guillorn1, B. Hekmatshoartabari1, P. Jacob1, R. Jain1, S. Jain1, J. Jung1, K. H. Kim1,
S. Koswatta1, M. Lutz1, A. Mannari3, A. Mathew4, I. Nair1, A. Ranjan1, Z. Ren1, S. Rider5, T. Rower1,
D. Satterfield6, M. Schaal1, S. Sen1, G. Tellez1, H. Tran1, W. Wang1, V. Zalani1, J. Zhang1, X. Zhang1,
V. Shah7, R. Senger1, A. Kumar1, P-F. Lu1, L. Chang1
1
IBM Research, Yorktown Heights, NY; 2IBM, Rochester, MN; 3IBM Research, Zurich, Switzerland
4
IBM, Austin, TX; 5IBM, Poughkeepsie, NY; 6IBM Research, Lowell, MA
7
IBM, Hursley, United Kingdom
1:55 PM
14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control
Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm
CMOS
W. Shan, K. Zhou, K. Li, Y. Du, Z. Chen, J. Qian, H. Ge, J. Yang, X. Si
2:20 PM
14.3 A 3nm Adaptive Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock
Duty-Cycle Distortion
D. Yingling1, Y. Peng1, R. Vachon1, D. Pal2, S. Jariwala2, F. Cabral3, J. Hu2, R. Verma2, V. Chiranji2,
A. Kumar2, S. Sarma2, K. Bowman1
1
Qualcomm, Raleigh, NC; 2Qualcomm, San Diego, CA; 3Qualcomm, Cork, Ireland
2:45 PM
14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System
Budgeting in a 4nm-Plus Octa-Core CPU
C-Y. Lu1, B-J. Huang1, M-C. Chen1, O. Tsai1, A. Tsai1, E-W. Fang1, Y. Cho1, H. H. Chen1, P. Kao1,
E. Wang1, H. Mair2, S-A. Hwang1, 1MediaTek, Hsinchu, Taiwan; 2MediaTek, Austin, TX
3:00 PM
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed
Hardware Power Management and Flexible NoC-Based Data Orchestration
M. Cassel dos Santos*1, T. Jia*2, J. Zuckerman*1, M. Cochet*3, D. Giri1, E. J. Loscalzo1,
K. Swaminathan3, T. Tambe2, J. J. Zhang2, A. Buyuktosunoglu3, K-L. Chiu1, G. Di Guglielmo1,
P. Mantovani1, L. Piccolboni1, G. Tombesi1, D. Trilla3, J-D. Wellman3, E-Y. Yang2, A. Amarnath3,
Y. Jing4, B. Mishra4, J. Park2, V. Suresh4, S. Adve4, P. Bose3, D. Brooks2, L. P. Carloni1,
K. L. Shepard1, G-Y. Wei2, 1Columbia University, New York, NY
2
Harvard University, Cambridge, MA; 3IBM Research, Yorktown Heights, NY
4
University of Illinois, Urbana, IL; *Equally Credited Authors (ECAs)
Break 3:15 PM
3:35 PM
14.6 A 10A Computational Digital LDO Achieving 263A/mm2 Current Density with
Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for
Mobile SoC Application in 3nm GAAFET
D. Lee, S. Kim, T. Nomiyama, D-H. Jung, D. Kim, J. Lee, S. Kwak
4:00 PM
14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a
Voltage-Mode Phase Interpolator in 28nm CMOS
L. Feng, X. Ji, L. Kuang, Q. Liao, S. Han, J. Zhao, W. Rhee, Z. Wang
4:25 PM
14.8 KASP: A 96.8% 10-Keyword Accuracy and 1.68μJ/Classification Keyword Spotting
and Speaker Verification Processor Using Adaptive Beamforming and Progressive
Wake-Up
J. Xiao1, X. Zhang1, S. Zhu1, Z. Yang1, M. Du1, C. Ji1, Y. Long1, X. Chen2, X. Miao2, L. Zhou1,
L. Chang1, S. Liu1, J. Zhou1
1
2
China Micro Semicon, Chengdu, China
4:50 PM
14.9 A Monolithic 10.5W/mm2 600MHz Top-Metal and C4 Planar Spiral Inductor-Based
Integrated Buck Voltage Regulator on 16nm-Class CMOS
S. Kim, H. K. Krishnamurthy, Z. Ahmed, N. Desai, S. Weng, A. Augustine, H. T. Do, J. Yu,
P. D. Bach, X. Liu, K. Radhakrishnan, K. Ravichandran, J. W. Tschanz, V. De
Intel, Hillsboro, OR
5:05 PM
14.10 34.7A/mm2 Scalable Distributed All-Digital 6×6 Dot-LDOs Featuring Freely
Linkable Current-Sharing Network: A Fine-Grained On-Chip Power Delivery
Solution in 28nm CMOS
Y-J. Lee1,2, W. Jang1,2, H-H. Bae1, J-H. Cho1, H-S. Kim1
1
2
Conclusion 5:20 PM
31
Embedded Memories & Ising Computing
Session Chair: Takashi Ito, Renesas, Kodaira-shi, Tokyo, Japan
Session Co-Chair: John Wuu, Advanced Micro Devices, Fort Collins, CO
1:30 PM
15.1 A 0.795fJ/b Physically-Unclonable-Function-Protected TCAM for
Software-Defined Networking Switch
Z. Yue1, X. Xiang1, F. Tu2, Y. Wang1, Y. Wang1, S. Wei1, Y. Hu1, S. Yin1
1
2
Hong Kong University of Science and Technology, Hong Kong, China
1:55 PM
15.2 A 2048×60m4 SRAM Design in Intel 4 with Around-the-Array
Power-Delivery Scheme Using PowerVia
D. Kim, Y. Kim, A. Shrivastava, G. Park, A. Mahadevan Pillai, K. Bannore, T. Doan,
M. Rahman, G. Baek, C. Ong, X. Wang, Z. Guo, E. Karl
2:20 PM
15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and
1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture
M. Haraguchi1, Y. Fujino1, Y. Yokoyama1, M-H. Chang2, Y-H. Hsu2, H-C. Cheng2, K. Nii1,
Y. Wang2, T-Y. J. Chang2
1
TSMC Design Technology Japan, Yokohama, Japan
2
2:45 PM
15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a
Resistance-Dominated Technology Node
M. Yeo1, K. Cho1, G. Kim1, W. J. Jo1, J. Oh1, S. Kim1, K. Baek1, S. Park1, S. J. Yei1,
S-O. Jung1,2
1
Yonsei University, Seoul, Korea
2
Articron, Ansan, Korea
3:00 PM
15.5 LISA: A 576×4 All-in-One Replica-Spin Continuous-Time Latch-Based
Ising Computer Using Massively-Parallel Random-Number Generations
and Replica Equalizations
J. Bae*1, J. Koo*2, C. Shim*1, B. Kim1
1
University of California, Santa Barbara, CA
2
Sejong University, Seoul, Korea
Break 3:15 PM
3:35 PM
15.6 e-Chimera: A Scalable SRAM-Based Ising Macro with an Enhanced-
Chimera Topology for Solving Combinatorial-Optimization Problems
Within Memory
J. Bae, C. Shim, B. Kim, University of California, Santa Barbara, CA
4:00 PM
15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249um2 Bitcell,
a 3.2GB/S Read Throughput, a 10kCycle Write Endurance and 10-Year
Retention at 105°C
Y-C. Huang, S-H. Liu, H-S. Chen, H-C. Feng, C-F. Li, C-Y. Yang, W-K. Chang, C-F. Yang,
C-Y. Wu, Y-C. Lin, T-T. Yang, C-Y. Chang, W-T. Chu, H. Chuang, Y. Wang, Y-D. Chih,
T-Y. J. Chang
4:25 PM
15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz
Random-Read Access and a 10.4MB/s Write Throughput with an In-Field
Programmable 0.3Mb MTJ-OTP for High-End MCUs
T. Ogawa, K. Matsubara, Y. Taito, T. Saito, M. Izuna, K. Takeda, Y. Kaneda, T. Shimoi,
H. Mitani, T. Ito, T. Kono
Renesas Electronics, Tokyo, Japan
4:50 PM
15.9 A 16nm 16Mb Embedded STT-MRAM with 20ns Write Time, a 1012
Write Endurance and Integrated Margin-Expansion-Schemes
K-F. Lin*, H. Noguchi*, Y-C. Shih, P-F. Yuh, Y-J. Lee, T-C. Chang, S-P. Huang,
Y-F. Lin, C-Y. Lee, Y-H. Huang, J-C. Tsai, S. Adham, P. Noel, R. Yazdi, M. Gershoig,
Y. Shin, V. Joshi, T. Wong, M-R. Jiang, J. J. Wu, C-T. Cheng, Y-J. Wang, H. Chuang,
Y-D. Chih, Y. Wang, T-Y. J. Chang
Conclusion 5:15 PM
32
Security: From Processors to Circuits
Session Chair: Sanu Mathew, Intel, Portland, OR
Session Co-Chair: Takeshi Sugawara,
The University of Electro-Communications, Tokyo, Japan
1:30 PM
16.1 A 2.7-to-13.3μJ/boot/slot Flexible RNS-CKKS Processor in 28nm CMOS
Technology for FHE-Based Privacy-Preserving Computing
H. Lee*, H. Kwon*, Y. Lee
Pohang University of Science and Technology, Pohang, Korea
1:55 PM
16.2 A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor
Across Multiple Mathematical Problems
Y. Zhu1, W. Zhu1,2, Y. Ouyang1, J. Sun1,2, M. Zhu3, Q. Zhao1,2, J. Yang1, C. Chen1,2,
Q. Tao1,2, G. Yang1,2, A. Zhang1, S. Wei1,2, L. Liu1,2
1
2
Beijing National Research Center for lnformation Science and Technology(BNRist),
Beijing, China
3
Micro Innovation Integrated Circuit Design Co.,Ltd, Wuxi, China, Wuxi, China
2:20 PM
16.3 3nm Physical Unclonable Function with Multi-Mode Self-Destruction and
3.48×10-5 Bit Error Rate
E. Hunt-Schroeder1, P. Lin-Butler2, A. Degada1, T. Xia2
1
Marvell, Burlington, VT
2
University of Vermont, Burlington, VT
2:45 PM
16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and
39× BER Reduction After Unstable Bit Detection and Masking
S. S. Kudva1, M. E. Sinangil1, S. Tell2, N. Nedovic1, S. Song1, B. Zimmer1, C. T. Gray2
1
Nvidia, Santa Clara, CA
2
Nvidia, Durham, NC
Break 3:10 PM
3:35 PM
16.5 A Synthesizable Design-Agnostic Timing Fault Injection Monitor Covering
2MHz to 1.26GHz Clocks in 65nm CMOS
Y. He, K. Yang
Rice University, Houston, TX
4:00 PM
16.6 PACTOR: A Variation-Tolerant Probing-Attack Detector for a 2.5Gb/s×4-
Channel Chip-to-Chip Interface in 28nm CMOS
M. Li1, Z. Wang1, S. K. Mathew2, V. De2, M. Seok1
1
Columbia University, New York, NY
2
4:25 PM
16.7 Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-
Aligned Globally-Synchronous-Locally-Asynchronous Operation Based
on Tunable Replica Circuits
S. Oruganti*1, M. Wang*1, V. V. Iyer1, Y. Wang1, M. Yang1, R. Kumar2, S. K. Mathew2,
J. P. Kulkarni1
1
University of Texas, Austin, TX
2
4:50 PM
16.8 A 60Mb/s TRNG with PVT-Variation-Tolerant Design Based on STR in 4nm
J. Park, Y. Lee, K. Bohdan, Y. Choi, J. Shin, H-G. Rhew, J. Shin
Conclusion 5:15 PM
33
Emerging Sensing and Computing Technologies
Session Chair: Rabia Yazicigil, Boston University, Boston, MA
Session Co-Chair: Denis Daly, Apple, Wellesley, MA
1:30 PM
17.1 Omnidirectional Magnetoelectric Power Transfer for Miniaturized
Biomedical Implants via Active Echo
W. Wang, Z. Yu, Y. Zou, J. Woods, P. Chari, J. T. Robinson, K. Yang
1:55 PM
17.2 A Miniature Multi-Nuclei NMR/MRI Platform with a High-Voltage SOI
ASIC Achieving a 134.4dB Image SNR with a 173×250×103μm3
Resolution
S. Fan1, Q. Zhou1, K. M. LEI1, R. P. Martins1,2, P-I. Mak1
1
2:20 PM
17.3 A Fully Wireless, Miniaturized, Multicolor Fluorescence Image Sensor
Implant for Real-Time Monitoring in Cancer Therapy
R. Rabbani*1, M. Roschelle*1, S. Gweon1, R. Kumar1, A. Vercruysse1, N. W. Cho2,
M. H. Spitzer2, A. M. Niknejad1, V. M. Stojanovic1, M. Anwar1,2
1
University of California, Berkeley, CA; 2University of California, San Francisco, CA
2:45 PM
17.4 Environmentally Friendly Disposable Circuit and Battery System for
Reducing Impact of e-Wastes
N. Miura1, H. Taguchi*1, K. Watanabe2, M. Nohara1, T. Makita3, M. Tanabe3,
T. Wakimoto3, S. Kumagai2, H. Nosaka1, A. Aratake1, T. Okamoto2, S. Watanabe2,
J. Takeya2, T. Komatsu1, 1Nippon Telegraph and Telephone, Atugi, Japan
2
University of Tokyo, Kashiwa, Japan; 3PI-CRYSTAL Incorporation, Kashiwa, Japan
3:00 PM
17.5 A 24V Mini-Coil Magnetic Neural Stimulator with Closed-Loop Deadtime
Control and ZCS Control Achieving 99.76% Charge Recovery Efficiency
Y. Fan *, Y. Liu *, G. Topali, R. Lycke, L. Luan, C. Xie, T. Chi
Rice University, Houston, TX; *Equally Credited Authors (ECAs)
Break 3:15 PM
3:35 PM
17.6 Fully Integrated CMOS Ferrofluidic Biomolecular Processing Platform
with On-Chip Droplet-Based Manipulation, Multiplexing and Sensing
D. Lee*1, K-S. Choi*1, F. Jiang*1, H. Liu1, D. Jung2, Y. Kong1, M. Saif1, Z. Huang1,
J. Wang1, H. Wang1, 1ETH Zürich, Zurich, Switzerland; 2Qualcomm, Santa Clara, CA
4:00 PM
17.7 Droplet Microfluidics Co-Designed with Real-Time CMOS Luminescence
Sensing and Impedance Spectroscopy of 4nL Droplets at a 67mm/s
Velocity
Q. Liu, D. Arguijo Mendoza, A. Yasar, D. Caygara, A. Kassem, D. Densmore,
R. T. Yazicigil, Boston University, Boston, MA
4:25 PM
17.8 0.4V 988nW Time-Domain Audio Feature Extraction for Keyword Spotting
Using Injection-Locked Oscillators
A. Mostafa, E. Hardy, F. Badets, CEA-Léti, Grenoble, France
4:50 PM
17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting
(KWS) Chip Incorporating Transfer-Computing Speaker Verification,
Hybrid-Domain Computing and Scalable 5T-SRAM
F. Tan1, W-H. Yu1, J. Lin1, K-F. Un1, R. P. Martins1,2, P-I. Mak1
1
University of Macau, Macau, China; 2University of Lisboa, Lisboa, Portugal
5:05 PM
17.10 A 0.4V, 750nW, Individually Accessible Wireless Capacitive Sensor
Interface IC for a Tactile Sensing Network
H. Hao, A. G. Richardson, Y. Ding, L. Du, M. G. Allen, J. Van der Spiegel, F. Aflatouni
5:20 PM
17.11 A 9mW Ultrasonic Through Transmission Transceiver for Non-Invasive
Intracranial Pressure Sensing
G. Topalli1, Y. Fan1, M. Y. Cheung1, A. Veeraraghavan1, M. Hirzallah2, T. Chi1
1
Rice University, Houston, TX; 2Baylor Collage of Medicine, Houston, TX
Conclusion 5:35 PM
34
High-Performance Optical Transceivers
Session Chair: Tamer Ali, Mediatek, Laguna Hills, CA
Session Co-Chair: Hyo Gyuem Rhew, Samsung, Hwaseong-si,
Gyeonggi-do, Korea
1:30 PM
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Front-End with
4x105GS/s 8b ADC/DAC in 16nm CMOS
G. Li1, A. Garg1, T. He1, U. Singh1, J. Zhang1, L. Rao1, C. Liu1, M. Nazari1, Y. Liu1,
Y. Liu1, H. Zhang1, T. Ali1,2, B. Rhew1,3, J. Ru1,4, D. Cui1, A. Nazemi1, B. Zhang1,
A. Momtaz1, J. Cao1
1
Broadcom, Irvine, CA
2
MediaTek, Irvine, CA
3
4
1:55 PM
18.2 A 4×64Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch
VCSEL-Based Optical Transmitter
S. Mondal, J. Qiu, S. Krishnamurthy, J. Kennedy, S. Bose, T. Acikalin, S. Yamada,
J. Jaussi, M. Mansuri
2:20 PM
18.3 An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based
Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical
Applications in 5nm
F. Ahmad1, A. Mellati1, A. Fernandez2, A. Iyer3, A. Fan1, B. Reyes2, C. Abidin 1, C. Nani4,
D. Albano4, F. Solis2, G. Minoia4, G. Hatcher1, H. Carrer2, K. Kota1, L. Wang1,
M. Bachu3, M. Garampazzi4, M. Hassanpourghadi1, N. Fan1, P. Prabha1, R. Nguyen1,
S. Ho5, T. Dusatko5, T. Wu1, W. Elsharkasy1, Z. Sun6, S. Jantzi1, L. Tse3
1
Marvell, Irvine, CA
2
Marvell, Cordoba, Argentina
3
Marvell, Santa Clara, CA
4
Marvell, Pavia, Italy
5
Marvell, Vancouver, Canada
6
Marvell, Singapore, Singapore
2:45 PM
18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s
Optical Coherent Communications in 5nm FinFET
R. L. Nguyen1, A. Mellati1, A. Fernandez2, A. Iyer3, A. Fan1, B. Reyes2, C. Abidin1,
C. Nani4, D. Albano4, F. Ahmad1, F. Solis2, G. Minoia4, G. Hatcher1, M. Bachu3,
M. Garampazzi4, M. Hassanpourghadi1, N. Fan1, P. Prabha1, S. Fan3, S. Ho5,
T. Dusatko5, T. Wu1, W. Elsharkasy1, Z. Sun6, S. Jantzi1, L. Tse3
1
Marvell, Irvine, CA
2
Marvell, Cordoba, Argentina
3
Marvell, Santa Clara, CA
4
Marvell, Pavia, Italy
5
Marvell, Vancouver, Canada
6
Marvell, Singapore, Singapore
Break 3:10 PM
35
RF to mm-Wave Oscillators and Multipliers
Session Chair: Hongtao Xu, Fudan University, Shanghai, China
Session Co-Chair: Swaminathan Sankaran, Texas Instruments, Allen, TX
3:35 PM
19.1 A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with a 62.5MHz
Reference, -259.7dB FoMJ, and -56.6dBc Reference Spur
H. Choi, S. Cho
4:00 PM
19.2 A 12.4% Efficiency, 11dBm Psat, Odd-Harmonics-Recycling, 62-to-92GHz
CMOS Frequency Quadrupler Using an Amplitude-Phase Coordinating
Technique
Z. Lin1,2, Y. Shen1,2, Y. Ding1, S. Hu1,2
1
2
Purple Mountain Laboratories, Nanjing, China
4:25 PM
19.3 An 8.9-to-21.9GHz Single-Core Oscillator with Reconfigurable Class-F–1
and Enhanced-Colpitts Dual-Mode Operation Achieving 209dBc/Hz FoMT
Z. Kang, C. Yu, L. Wu
4:50 PM
19.4 A 0.07mm2 20-to-23.8GHz 8-phase Oscillator Incorporating Magnetic +
Dual-Injection Coupling Achieving 189.2dBc/Hz FoM@10MHz and
200.7dBc/Hz FoMA in 65nm CMOS
Y. Zhao*1, C. Fan*1, Q. Fang1, G. Zhang1, J. Yin2, P-I. Mak2, L. Geng1
1
Xi’an JiaoTong University, Xi’an, China
2
University of Macau, Macao, China
5:05 PM
19.5 A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using
an Oscillation-Mode-Splitting Technique
H. Ge, H. Jia, W. Deng, R. Ma, Z. Wang, B. Chi
Conclusion 5:20 PM
36
Demonstration Session 2, Tuesday, February 20th, 5:00-7:00 PM
This year, the Demonstration Session extending in selected regular papers, both Academic and Industrial,
will take place on Monday February 19th, and Tuesday February 20th, from 5 pm until 7 pm in the Golden
Gate Hall. These demonstrations will feature real-life applications made possible by new ICs presented at
ISSCC 2024, as noted by the symbol DS2
List to Come
37
EVENING EVENTS Tuesday February 20th, 8:00 PM
EE4: Generative AI for Chip Design
Organizer: Johan Vanderhaegen, Google, Mountain View, CA
Co-Organizer: Wu-Hsin Chen, Qualcomm, San Diego, CA
JuangYing Chue, Etron, Taipei, Taiwan
Jae-sun Seo, Cornell Tech, New York, NY
ShonHang Wen, Mediatek, Hsinchu, Taiwan
Moderator: Jan Rabaey, University of California, Berkeley, CA

and imec, Leuven, Belgium
With the emergence of machine learning and generative AI, many types of jobs
are being transformed by GPT-based tools. Large Language Models are starting
to be used for education and can be used to contribute to publications, and AI
is being embedded into EDA tools. Join this evening panel with experts from
industry and academia to discuss how generative AI or AI in general will change
IC design.
Panelists: Thomas Andersen, Synopsys, Mountain View, CA

Edith Beigné, Meta, Menlo Park, CA
Vidya Chhabria, Arizona State University, Phoenix, AZ
Georges Gielen, KU Leuven, Leuven, Belgium
Rajeev Jain, Qualcomm, San Diego, CA
Hammond Pearce, University of New South-Wales,
Sydney, Australia
EE5: The Legacy of Gordon Moore

Organizer: Bodhisatwa Sadhu, IBM T. J. Watson Research Center,
Yorktown Heights, NY
Co-Organizers: Kaushik Sengupta, Princeton University, Princeton, NJ
Tanay Karnik, Intel, Hillsboro, OR
Shahrzad Naraghi, Legato Logic, San Jose, CA
Moderator: Thomas Lee, Stanford University, Stanford, CA
Moore’s Law has propelled the semiconductor industry for decades,

transforming the world through advancements in digital electronics, and to some
extent, analog and RF electronics. These advancements have fueled other
engineering fields such as artificial intelligence, biomedical engineering and
quantum engineering. In this session, we will have a fireside chat with
semiconductor and IC design luminaries celebrating the life and legacy of Gordon
Moore, discussing the impact of Moore’s law on our industry, and venturing into
the next chapter of Moore’s law in the context of upcoming IC ecosystems.
Panelists: Chenming Hu, University of California, Berkeley, CA

H.-S. Philip Wong, Stanford University, Stanford, CA
Mendy Furmanek, IBM, Dallas, TX
Ian Young, Intel, Hillsboro, OR
Isabelle Ferain, Global Foundries, Dresden, Germany
38
SESSION 20 Wednesday, February 21st, 8:00 AM
Machine Learning Accelerators
Session Chair: Chia-Hsiang Yang, National Taiwan University, Taipei, Taiwan
Session Co-Chair: Ji-Hoon Kim, Ewha Womans University, Seoul, Korea
8:00 AM
20.1 NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for
High-Resolution Visual-Quality Enhancement on Smart Devices
M-E. Shih*1, S-W. Hsieh*1, P-Y. Tsai*1, M-H. Lin1, P-K. Tsung1, E-J. Chang1, J. Liang1,
S-H. Chang1, C-L. Huang1, Y-Y. Nian1, Z. Wan2, S. Kumar2, C-X. Xue1, G. Jedhe2,
H. Fujiwara3, H. Mori3, C-W. Chen1, P-H. Huang1, C-F. Juan1, C-Y. Chen1, T-Y. Lin1,
C. Wang1, C-C. Chen1, K. Jou1
1
MediaTek, Hsinchu, Taiwan
2
MediaTek, San Jose, CA
3
8:25 AM
20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator
Exploiting Denoising-Similarity for Diffusion Models
R. Guo1, L. Wang1, X. Chen1, H. Sun1, Z. Yue1, Y. Qin1, H. Han1, Y. Wang1, F. Tu2,
S. Wei1, Y. Hu1, S. Yin1
1
2
Hong Kong University of Science and Technology, Hong Kong, China
8:50 AM
20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-
Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-
Time Robot Applications
K. Nose, T. Fujii, K. Togawa, S. Okumura, K. Mikami, D. Hayashi, T. Tanaka, T. Toi
9:15 AM
20.4 A 28nm Physics Computing Unit Supporting Emerging Physics-Informed
Neural Network and Finite Element Method for Real-Time Scientific
Computing on Edge Devices
Y. Ju, G. Xu, J. Gu
Northwestern University, Evanston, IL
Break 9:40 AM
10:05 AM
20.5 C-Transformer: A 2.6-to-18.1μJ/Token Homogeneous DNN-
Transformer/Spiking-Transformer Processor with Big-Little
Network and Implicit Weight Generation for Large Language Models
S. Kim, S. Kim, W. Jo, S. Kim, S. Hong, H-J. Yoo
10:30 AM
20.6 LSPU: A Fully Integrated Real-Time LiDAR-SLAM SoC with Point-Neural-
Network Segmentation and Multi-Level kNN Acceleration
J. Jung1, S. Kim1, B. Seo1, W. Jang1, S. Lee1, J. Shin1, D. Han2, K. J. Lee1
1
2
10:55 AM
20.7 NeuGPU: A 18.5mJ/Iter Neural-Graphics Processing Unit for Instant-
Modeling and Real-Time Rendering with Segmented-Hashing
Architecture
J. Ryu1, H. Kwon1, W. Park1, Z. Li1, B. Kwon1, D. Han2, D. Im1, S. Kim1, H. Joo1,
H-J. Yoo1
1
2
11:20 AM
20.8 Space-Mate: A 303.5mW Real-Time Sparse Mixture-of-Experts-Based
NeRF-SLAM Processor for Mobile Spatial Computing
G. Park1, S. Song1, H. Sang1, D. Im1, D. Han2, S. Kim1, H. Lee1, H-J. Yoo1
1
2
Conclusion 11:45 AM
39
TIMETABLE OF ISSCC 2024 SESSIONS
ISSCC 2024 • SUNDAY, FEBRUARY 18TH
TUTORIALS
T2: Fundamentals of Digital and Digitally Assisted T3: Fundamentals of Circuit Design
8:30 AM T1: Process-Scalable Low-Power Amplifiers
Linear Voltage Regulators for 2.5D/3D Integration
T4: Fundamentals of Power Management T6: Recent Circuit Advances for Resilience to
10:30 AM T5: Calibration Techniques in PLLs
Systems: Constraints and Solutions Side-Channel Attacks
T8: 3D Flash Memory from Technology to the System:
1:30 PM T7: Fundamentals of Continuous-Time ADCs Past, Present and Future Developments
3:30 PM T9: Domain-Specific Accelerators: From Hardware to Systems T10: Fundamentals of Transceivers for Communication and Sensing
FORUMS
8:00 AM F1: Efficient Chiplets and Die-to-Die Communications F2: Energy-Efficient AI-Computing Systems for Large-language Models
EVENTS BELOW IN BOLD BOX ARE INCLUDED WITH YOUR CONFERENCE REGISTRATION
EVENING EVENTS
4:00 PM: Mentoring Session / Networking Bingo Event 8:00 PM EE1: Student Research Preview Short Presentations with Poster Session
ISSCC 2024 • MONDAY, FEBRUARY 19TH • PAPER SESSIONS
8:30 AM SESSION 1: PLENARY SESSION
Session 4:
High Performance Transceivers
Session 2: Session 3: and Transmitters for Session 6: Session 7:
1:30 PM Processors Analog Techniques Communication and Ranging Imagers and Ultrasound Ultra-High-Speed Wireline
and Communication SoCs 3:35 PM – Session 5:
Wireless RF and mm-Wave
Receiver Techniques
12noon to 7:00 PM – Book Displays • 3:00 PM to 8:00 PM – Corporations/Institution Exhibition
5:00 PM to 7:00 PM – Demonstration Session • 5:30 PM – Author Interviews • Social Hour
EVENING EVENTS
8:00 PM EE2: Career Trajectories: Sharing our Paths to Success EE3: Mixed-Foundry Chiplets? Opportunities and Challenges
ISSCC 2024 • TUESDAY, FEBRUARY 20 TH
• PAPER SESSIONS
Session 11:
Session 8: Session 9: Session 10: Industry Invited Session 13:
8:00 AM Hybrid DC-DC Converters Noise Shaping and SAR ADCs Frequency Synthesis High-Density Memory
10:05 AM – Session 12: and Interfaces
Electromagnetic Interface ICs
for Information and Power
Session 18:
Session 14: High-Performance Optical
Session 15: Session 16: Session 17: Transceivers
Digital Techniques for System
1:30 PM Adaptation, Power Management Embedded Memories Security: Emerging Sensing and Computing
& Ising Computing From Processors to Circuits Technologies 3:35 PM – Session 19:
and Clocking RF to mm-Wave Oscillators
and Multipliers
9:30 AM to 1:30 PM; and from 3:00 PM to 8:00 PM – Corporations/Institution Exhibition • 10:00 AM to 7:00 PM – Book Displays
5:00 PM to 7:00 PM – Demonstration Session • 5:30 PM – Author Interviews • Social Hour
EVENING EVENTS
8:00 PM EE4: Generative AI for Chip Design EE5: The Legacy of Gordon Moore
ISSCC 2024 • WEDNESDAY, FEBRUARY 21 ST
• PAPER SESSIONS
Session 21: Session 23: Session 25: Session 27:
Energy-Efficient Invited: Innovations from Outside
Session 20: Audio Amplifiers
Connectivity Radios the (ISSCC's) Box Wireless Power
8:00 AM Machine Learning
Accelerators 10:05 AM – Session 22: 10:05 AM – Session 24: 10:05 AM – Session 26: 10:05 AM – Session 28:
High-Speed Analog-to-Digital D-Band/Sub-THz Transmitters Display and User Interaction
Converters and Sensors Technologies High-Density Power Management
Session 29:
ICs for Quantum Technologies Session 31: Session 32: Session 33: Session 34:
1:30 PM Power Converter Techniques Power Amplification Intelligent Neural Interfaces and Compute-In-Memory
3:35 PM – Session 30: and Signal Generation Sensing Systems
Domain-Specific Computing
and Digital Accelerators
10:00 AM to 3:00 PM – Book Displays • 5:30 PM – Author Interviews
ISSCC 2024 • THURSDAY, FEBRUARY 22ND
Short Course: F3: F4: F5: F6:
Machine Learning Hardware: Digitally Enhanced Analog Intelligent Sensing Recent Developments in Toward Next Generation of
8:00 AM Considerations and Circuits: Trends & High-Performance Frequency Highly Integrated Electrical
Accelerator Approaches State-of-the-art Designs Synthesis Circuits and Systems and Optical Transceivers
40 41
Audio Amplifiers
Session Chair: Shon-Hang Wen, Mediatek, Hsinchu, Taiwan
Session Co-Chair: Chinwuba Ezekwe, Robert Bosch, Sunnyvale, CA
8:00 AM
21.1 A 121.7dB DR and -109.0dB THD+N Filterless Digital-Input Class-D
Amplifier with an HV Multibit IDAC Using Tri-level Output and Employing
a Transition-Rate-Balanced Bidirectional RTDEM Scheme
H. Zhang*1, M. Zhang*1, M. Chen1, A. Admiraal1, M. Zhang1, M. Berkhout2, Q. Fan1
1
2
Goodix Technology, Nijmegen, The Netherlands
8:25 AM
21.2 A 0.81mA, -105.2dB THD+N Class-D Audio Amplifier with Capacitive
Feedforward and PWM-Aliasing Reduction for Wide-Band-Effective
Linearity Improvement
K. Zhou, J. Zhou, Y. Tang, J. Li, Z. Hong, J. Xu
8:50 AM
21.3 A -106.3dB THD+N Feedback-After-LC Class-D Audio Amplifier
Employing Current Feedback to Enable 530kHz LC-Filter Cut-Off
Frequency
H. Zhang1, H. Fan1, M. Zhang1, M. Berkhout2, Q. Fan1
1
2
Goodix Technology, Nijmegen, The Netherlands
9:15 AM
21.4 A -108dBc THD+N, 2.3mW Class-H Headphone Amplifier with Power-
Aware SIMO Supply Modulator
S-H. Wen*, C-H. Hsiao*, Y-W. Huang*, K-Y. Lin, Y-S. Chen, Y-C. Chen, M-C. Tsai,
K-H. Chen, K-D. Chen
MediaTek, Hsinchu, Taiwan
Break 9:40 AM
42
High-Speed Analog-to-Digital Converters
Session Chair: Pieter Harpe, Eindhoven University of Technology,
Session Co-Chair: Benjamin Hershberg, Intel, Portland, OR
10:05 AM
22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive
Calibration of TI Errors and Linearized Input Buffer
Y. Cao1, M. Zhang1, Y. Zhu1, R. P. Martins1,2, C-H. Chan1
1
2
10:30 AM
22.2 A 700MHz BW –164dBFS/Hz Small-Signal-NSD 703mW Continuous-Time
Pipelined ADC with On-Chip Digital Reconstruction Achieving <–85dBFS
HD3 Using Digital Cancellation of DAC Errors
S. Patil1, A. Ganesan1, H. Shibata1, V. Kozlov1, G. Taylor2, Q. Yu3, Z. Li1, Z. Lulec1,
K. Vasilakopoulos1, P. Shrestha2, D. Paterson4, R. Theertham1, A. Chowdhury5
1
2
Analog Devices, San Diego, CA
3
now with Amazon, Toronto, Canada
4
Analog Devices, Wilmington, MA
5
now with University of Toronto, Toronto, Canada
10:55 AM
22.3 A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC
with Common-Mode Input Tracking
A. Whitcombe1, S. Kundu2, H. Chandrakumar3, A. Agrawal3, T. Brown3, S. Callender4,
B. Carlton3, S. Pellerano3
1
2
AMD, Hillsboro, OR
3
4
Intel, Fort Collins, CO
11:20 AM
22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based
Background Timing-Skew Calibration and Bit-Distribution-Based
Background Ping-Pong Comparator Offset Calibration
Y. Tao, M. Gu, B. Chi, Y. Zhong, L. Jie, N. Sun
11:45 AM
22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC
E. Martens1, A. Cooman1, P. Renukaswamy1, S. Nagata2, S. Park1, J. Lagos1,
N. Markulic1, J. Craninckx1
1
imec, Heverlee, Belgium
2
Sony Semiconductor Solutions, Atsugi, Japan
Conclusion 12:00 PM
43
Energy-Efficient Connectivity Radios
Session Chair: Renzhi Liu, Intel, Hillsboro, OR
Session Co-Chair: Giuseppe Gramegna, IMEC, Golfe Juan, France
8:00 AM
23.1 A 44μW IoT Tag Enabling 1μs Synchronization Accuracy and OFDMA
Concurrent Communication with Software-Defined Modulation
J. Shen*1, F. Zhu*2, Y. Liu1, B. Liu1, C. Shi1, L. Huang1, L. Xu1, X. Tian2, R. Zhang1
1
East China Normal University, Shanghai, China
2
Shanghai Jiao Tong University, Shanghai, China
8:25 AM
23.2 A 1mm2 Software-Defined Dual-Mode Bluetooth Transceiver with 10dBm
Maximum TX Power and -98.2dBm Sensitivity 2.96mW RX Power at
1Mb/s
N. Scolari, F. X. Pengg, K. Manetakis, C. A. Salazar, A. Vouilloz, E. Pérez Serna,
A. Dissanayake, P. Persechini, V. Kopta, E. Le Roux, F. Chicco, S. Cillo, N. Gerber,
C. Barbelenet, F. Epifano, P. A. Dal Fabbro, N. Raemy
CSEM, Neuchâtel, Switzerland
8:50 AM
23.3 A Passive Crystal-Less Wi-Fi-to-BLE Tag Demonstrating Battery-Free
FDD Communication with Smartphones
Z. Chang*1, Q. Xiao*1, C. Chen2, W. Wang1, X. Hu1, C. Yang1, Z. Li1, Y. Luo1, B. Zhao1
1
Zhejiang University, Hangzhou, China
2
Microaiot, Hangzhou, China
9:15 AM
23.4 A 167μW 71.7dB-SFDR 2.4GHz BLE Receiver Using a Passive
Quadrature-Front-End, a Double-Sided Double-Balanced Cascaded Mixer
and a Dual-Transformer-Coupled Class-D VCO
H. Shao1, R. P. Martins1,2, P-I. Mak1
1
2
University of Lisboa, Lisboa, Portugal
9:30 AM
23.5 A 7.6mW IR-UWB Receiver Achieving −13dBm Blocker Resilience with
a Linear RF Front-End
A. N. Bhat, P. Mateman, Z. Xu, P. Vis, P. Detterer, G. K. Ramachandra, Y. Baykal,
M. Konijnenburg, Y-H. Liu, C. Bachmann, P. Zhang
imec, Eindhoven, The Netherlands
Break 9:45 AM
44
D-Band/Sub-THz Transmitters and Sensors
Session Chair: Bodhisatwa Sadhu, IBM T. J. Watson Research Center,
Session Co-Chair: Shahriar Shahramian, Nokia – Bell Labs,
New Providence, NJ
10:05 AM
24.1 A 90-to-180GHz APD-Integrated Transmitter Achieving 18dBm Psat in
28nm CMOS
D. Tang1, X. Xia1, Z. Yan1, P. Zhou1, Z. Li1, C. Yang1, R. Zhang1, Z. Chen1, J. Chen1,
H. Gao1,2, W. Hong1
1
2
Eindhoven University of Technology, Eindhoven, The Netherlands
10:30 AM
24.2 A Scalable 134-to-141GHz 16-Element CMOS 2D λ/2-Spaced Phased
Array
J. Zhang*, B. Dai*, X. Meng, Y. Hu, M. Guan, H. Deng, B. Zhang, C. Wang
10:55 AM
24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in
65nm CMOS
C. Wang1, H. Herdian1, W. Zheng1, C. Liu1, J. Mayeda1, Y. Liu1, O. A. Yong1, W. Wang1,
Y. Zhang1, C. D. Gomez1, A. Shehata1, S. Kato1, I. Abdo2, T. Jyo2, H. Hamada2,
H. Takahashi2, H. Sakai1, A. Shirane1, K. Okada1
1
Tokyo Institute of Technology, Tokyo, Japan
2
Nippon Telegraph and Telephone, Tokyo, Japan
11:20 AM
24.4 Sub-THz Ruler: Spectral Bistability in a 235GHz Self-Injection-Locked
Oscillator for Agile and Unambiguous Ranging
S. M. H. Naghavi1,2, M. Tavakoli Taba1,3, A. Tabatabavakili1, A. Mostajeran1,4,
M. Aseeri5, A. Cathelin6, E. Afshari1
1
University of Michigan, Ann Arbor, MI
2
now at The University of Washington, Seattle, WA
3
now at Apple, Cupertino, CA
4
now at Zadar Labs, San Jose, CA
5
King Abdulaziz City for Science and Technology, Riyadh, Saudi Arabia
6
STMicroelectronics, Crolles, France
Conclusion 11:45 AM
45
Invited: Innovations from Outside the (ISSCC’s) Box
Session Chair: Firooz Aflatouni, University of Pennsylvania,
Philadelphia, PA
Session Co-Chair: Kaushik Sengupta, Princeton University, Princeton, NJ
8:00 AM
25.1 Short-Reach Silicon Photonic Interconnects with Quantum Dot Mode
Locked Laser Comb Sources
A. Netherton1, M. Dumont1, Z. Nelson1, J. Jhonsa1, A. Mo1, J. Koo1, D. McCarthy1,
N. Pestana2, S. Deckoff-Jones2, C. Poulton2, M. Frankel3, J. Bovington4,
L. Theogarajan1, J. Bowers1
1
2
Analog Photonics, Boston, MA
3
Ciena, Hanover, MD
4
Cisco Optical, Nuremberg, Germany
8:25 AM
25.2 Extreme Wave-Based Metastructures
N. Engheta
8:50 AM
25.3 Toward Exponential Growth of Therapeutic Neurotechnology
J. T. Robinson1,2, J. E. Woods1, K. Yang1
1
2
Motif Neurotech, Houston, TX
9:15 AM
25.4 Liquid Metal – Polymer Composites for Stretchable Circuits, Soft
Machines, and Thermal Management
C. Majidi
Carnegie Mellon University, Pittsburgh, PA
Break 9:40 AM
46
Display and User Interaction Technologies
Session Chair: Mutsumi Hamaguchi, Sharp Corporation, Nara, Japan
Session Co-Chair: Leonardo Gasparini, Fondazione Bruno Kessler,Trento, Italy
10:05 AM
26.1 A 600ch 10b Source-Driver IC with a Charge-Modulation DAC Achieving
1-Horizontal Time of 1.5μs Suitable for 240Hz-Frame-Rate Mobile
Displays
Y. Park1, G-G. Kang1, G-W. Lim1, S. Shin1, Y-S. Ahn2, W. Kim2, H-S. Kim1
1
2
LX Semicon, Seoul, Korea
10:30 AM
26.2 A Fully Nonlinear Compact 10b Source Driver with Low-Voltage Gamma
Slope DAC and Data/Phase Dependent Current Modulation Achieving
2411μm2/Channel for Mobile OLED Displays
J. Ahn1, S. H. Choi1, J. An1, K-D. Kim2, H-M. Lee1
1
Korea University, Seoul, Korea
2
C&Tech, Seoul, Korea
10:55 AM
26.3 Noise Immunity in Capacitive Sensing: Single-Ended AFE Design with
Common-Current Subtraction for Mutual- and Self-Capacitance Sensing
in 390pF Load
J. Y. An1, S. H. Choi1, S-W. Kim2, J-Y. Lee2, H-M. Lee1, Y-K. Choi1
1
2
11:20 AM
26.4 A 620pF-Compensated Dual-Mode Capacitance Readout IC for
Sub-Display TSP with VRR Scan
J. Lee*1, J. Ham*1, H. Lee1, W. Jang1, H. Kim2, B. So2, S. Ko1
1
Kwangwoon University, Seoul, Korea
2
Zinitix, Suwon, Korea
11:45 AM
26.5 A 977μW Capacitive Touch Sensor with Noise-Immune Excitation Source
and Direct Lock-In ADC Achieving 25.2pJ/step Energy Efficiency
X. Feng1, Z. Wang1, Y. Chen1, T. Cai1, Y. Xuan1, C. Yang1, W. Wang1, Y. Zhang1, Z. Tang2,
Y. Luo1, B. Zhao1
1
Zhejiang University, Hangzhou, China
2
Vango Technologies, Hangzhou, China
Conclusion 12:00 PM
47
Wireless Power
Session Chair: Patrik Arno, ST Microelectronics, Grenoble, France
Session Co-Chair: Kousuke Miyaji, Shinshu University, Nagano, Japan
8:00 AM
27.1 A Differential Hybrid Class-ED Power Amplifier with 27W Maximum
Power and 82% Peak E2E Efficiency for Wireless Fast Charging To-Go
F. Mao, R. Martins, Y. Lu
8:25 AM
27.2 A 6.78MHz 79.5%-Peak-Efficiency Wireless Power Transfer System
using a Wireless Mode-Recognition Technique and a Fully-On/off
Class-D Power Amplifier
J. Ge, Y. Lu, R. Yang, D. Pan, L. Cheng
8:50 AM
27.3 A 90.8%-Efficiency SIMO Resonant Regulating Rectifier Generating 3
Outputs in a Half Cycle with Distributed Multi-Phase Control for
Wirelessly-Powered Implantable Devices
H-S. Lee, K. Eom, H-M. Lee
9:15 AM
27.4 A 13.56MHz Wireless Power Transfer System with Hybrid
Voltage-/Current-Mode Receiver and Global Digital-PWM
Regulation Achieving 150% Transfer Range Extension and 72.3%
End-to-End Efficiency
T. Lu, S. Du
9:30 AM
27.5 A Wireless Power Transfer System with Up-to-27.9% Efficiency
Improvement Under Coupling Coefficient Ranging from 0.1 to 0.39 Based
on Phase-Shift/Time-Constant Detection and Hybrid Transmission Power
Control
Y. Chen, Y. Luo, Y. Lin, L. Shao, D. Chen, J. Guo
Sun Yat-Sen University, Guangzhou, China
Break 9:45 AM
48
High-Density Power Management
Session Chair: Xun Liu, Chinese University of Hong Kong,
Shenzhen, China
Session Co-Chair: Hanh-Phuc Le, University of California,
San Diego, La Jolla, CA
10:05 AM
28.1 A Fully Integrated, Domino-Like-Buffered Analog LDO Achieving –28dB
Worst-Case Power-Supply Rejection Across the Frequency Spectrum
from 10Hz to 1GHz with 50pF On-Chip Capacitance
J-G. Lee1, H-H. Bae1, S. Jang2, H-S. Kim1
1
2
Electronics and Telecommunications Research Institute, Daejeon, Korea
10:30 AM
28.2 A 12V-Input 1V-1.8V-Output 94.7%-Peak-Efficiency 685A/cm3-Current-
Density Hybrid DC-DC Converter with a Charge Converging Phase
Y. Ji, J. Jin, L. Cheng
10:55 AM
28.3 A 12-28V to 0.6-1.8V Ratio-Regulatable Dickson SC Converter with Dual-
Mode Phase Misalignment Operations Achieving 93.1% Efficiency and
6A Output
Q. Ma1, Y. Jiang1, H. Li1, X. Zhang1, M-K. Law1, R. P. Martins1,2, P-I. Mak1
1
2
University of Lisboa, Lisbon, Portugal
11:20 AM
28.4 A Monolithic 12.7W/mm2-Pmax, 92% Peak-Efficiency CSCR-First
Switched-Capacitor DC-DC Converter
N. Butzen, H. Krishnamurthy, J. Yu, Z. K. Ahmed, S. Weng, K. Ravichandran,
R. H. Ahangharnejhad, J. Waldemer, C. Pelto, J. Tschanz
11:35 AM
28.5 A 94.1%-Efficiency Parallel-SC Hybrid Buck Converter Designed Using
VCR-Aware Topology Optimizer for a 4.2A/mm2 Current-Density FoM
H. Han, J-H. Cho, W. Jang, Y. Park, J. Lee, H-S. Kim
11:50 AM
28.6 An 87% Efficient 2V-Input, 200A Voltage Regulator Chiplet Enabling
Vertical Power Delivery in Multi-kW Systems-on-Package
R. Jain1, S. Xu2, R. Kaushal1, C. Mariscal1, H. Caballero3, T. Salus4, C. Schaef1,
A. Deka5, A. Payala5, K. Chen6, H. Do7, J. Douglas7
1
2
3
Intel, Guadalajara, Mexico
4
Intel, Haifa, Israel
5
Intel, Bangalore, India
6
Intel, Hudson, MA
7
Intel, Chandler, AZ
Conclusion 12:05 PM
49
SESSION 29 Wednesday, February 21st, 1:30 PM
ICs for Quantum Technologies
Session Chair: Giorgio Ferrari, Politecnico di Milano, Milano, Italy
Session Co-Chair: Joseph Bardin, Google & UMass Amherst, Goleta, CA
1:30 PM
29.1 A 22nm FD-SOI <1.2mW/Active-Qubit AWG-Free Cryo-CMOS Controller
for Fluxonium Qubits
L. Le Guevel1, C. Wang1, J. C. Bardin1,2
1
University of Massachusetts, Amherst, MA
2
Google Quantum AI, Goleta, CA
1:55 PM
29.2 A Cryo-CMOS Controller with Class-DE Driver and DC Magnetic-Field
Tuning for Color-Center-Based Quantum Computers
L. Enthoven*1, N. Fakkel*1, H. Bartling2, M. van Riggelen2, K-N. Schymik2, J. Yun2,
E. Tsapanou Katranara2, R. Vollmer2, T. Taminiau2, F. Sebastiano**1, M. Babaie**1
1
2
QuTech, Delft, The Netherlands
2:20 PM
29.3 A Cryo-CMOS Receiver with 15K Noise Temperature Achieving 9.8dB
SNR in 10μs Integration Time for Spin Qubit Readout
B. Prabowo1,2, O. Pietx-Casas1,2, M. A. Montazerolghaem1, G. Scappucci1,2,
L. M.K. Vandersypen1,2, F. Sebastiano1,2, M. Babaie1,2
1
2
QuTech, Delft, The Netherlands
2:45 PM
29.4 A Cryo-CMOS Quantum Computing Unit Interface Chipset in 28nm Bulk
CMOS with Phase-Detection Based Readout and Phase-Shifter Based
Pulse Generation
Y. Guo1,2, Q. Liu3, W. Huang1, Y. Li1, T. Tian1, N. Wu1, S. Zhang1, T. Li1,3, Z. Wang1,
N. Deng1, Y. Zheng2, H. Jiang1
1
2
Nanyang Technological University, Singapore, Singapore
3
Beijing Academy of Quantum Information Sciences, Beijing, China
3:00 PM
29.5 A Portable 14GHz Dual-Mode Pulse and Continuous-Wave Electron
Paramagnetic Resonance Spectrometer Using a Subharmonic Direct
Conversion Receiver
J-H. Sun, M. Rustom, T. D. Nguyen, J. Singh, P. Qin, C. Sideris
University of Southern California, Los Angeles, CA
Break 3:15 PM
50
Domain-Specific Computing and Digital Accelerators
Session Chair: Huichu Liu, Meta Reality Labs, Sunnyvale, CA
Session Co-Chair: Jae-sun Seo, Cornell Tech, New York, NY
3:35 PM
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a
Localization Solver for Bristle Robot Surveillance
S. D. Spetalnick*1, A. S. Lele*1, B. Crafton1, M. Chang1, S. Ryu1, J-H. Yoon2, Z. Hao1,
A. Ansari1, W-S. Khwa3, Y-D. Chih4, M-F. Chang3, A. Raychowdhury1
1
2
3
TSMC Corporate Research, Hsinchu, Taiwan
4
TSMC Design Technology, Hsinchu, Taiwan
4:00 PM
30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network
Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive
In-Memory Computing
Y. Liu*1, Y. Ma*1, N. Shang1, T. Zhao2, P. Chen1, M. Wu1, J. Ru1, T. Jia1, L. Ye1,
Z. Wang3, R. Huang1
1
2
3
Beijing Information Science and Technology University, Beijing, China
4:25 PM
30.3 VIP-Sat: A Boolean Satisfiability Solver Featuring 5×12 Variable In-
Memory Processing Elements with 98% Solvability for 50-Variables
218-Clauses 3-SAT Problems
C. Shim, J. Bae, B. Kim
4:50 PM
30.4 A Fully Integrated Annealing Processor for Large-Scale Autonomous
Navigation Optimization
Y-C. Chu, Y-C. Lin, Y-C. Lo, C-H. Yang
National Taiwan University, Taipei, Taiwan
5:05 PM
30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine
Featuring 15-Level Coefficients and Leaked Negative-Feedback
Annealing
J. Song*, Z. Wu*, X. Tang, B. Xu, H. Luo, Y. Yang, Y. Wang, R. Wang, R. Huang
5:20 PM
30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-
Memory Vector Register File for Efficient High-Performance Computing
Y. Wang, M. Yang, C-P. Lo, J. P. Kulkarni
University of Texas, Austin, TX
Conclusion 5:35 PM
51
Power Converter Techniques
Session Chair: Saurav Bandyopadhyay, Texas Instruments, Dallas, TX
Session Co-Chair: Dongsu Kim, Samsung Electronics, Hwasung-si, Korea
1:30 PM
31.1 An 83.4%-Peak-Efficiency Envelope-Tracking Supply Modulator Using a Class-G
Linear Amplifier and a Single-Inductor Dual-Input-Dual-Output Converter for
200MHz Bandwidth 5G New Radio RF Applications
C. Chen, X. Li, R. Hu, L. Cheng, University of Science and Technology of China, Hefei, China
1:55 PM
31.2 A Ripple-Less Buck Converter with Sub -21.94dB EVM for 5G Low Earth Orbit
Application
Y-H. Kao1, J-L. Wu1, W-C. Huang1, H-H. Chang1, H-Y. Tsai1, R-B. Guo1, K-H. Chen1, K-L. Zeng1,2,
Y-H. Lin3, S-R. Lin3, T-Y. Tsai3
1
2
Chip-GaN Power Semiconductor, Hsinchu, Taiwan; 3Realtek Semiconductor, Hsinchu, Taiwan
2:20 PM
31.3 A 950ns 0.5-to-5.5V 5G NR RF PA Supply Modulator with Floating Capacitor
Control for Symbol Power Tracking
I-H. Kim, J-I. Seo, Y. Choo, S. Park, J. Han, W. Kim, S. Jung, T. Ko, D. Kim, J. Lee, S. Kwak
2:45 PM
31.4 98.7% Efficiency 1200V-to-48V LLC Converter with CC/CV Mode Charging
Compliant with EVSE Level 1
T-W. Wang1, S-H. Hung1, P-J. Chiu1, C-Y. Chen1, C-L. Go1, Y-T. Huang1, X-Q. Wu1, K-H. Chen1,
K-L. Zeng1,2, Y-H. Lin3, S-R. Lin3, T-Y. Tsai3
1
2
Chip-GaN Power Semiconductor, Hsinchu, Taiwan; 3Realtek Semiconductor, Hsinchu, Taiwan
3:00 PM
31.5 A 750-mW, 37% Peak Efficiency Isolated DC-DC Converter with 54/18-Mb/s
Full-Duplex Communication Using a Single Pair of Transformers
T. Hu1, M. Huang1, R. P. Martins1,2, Y. Lu1
1
Break 3:15 PM
3:35 PM
31.6 A SIDO/DISO VCF-Step-Reconfigurable Continuously Scalable-Conversion-Ratio
SC Converter Achieving 91.4%/92.6% Peak Efficiency and Almost-lossless
Channel Switching
Y. Wang1, M. Huang1, R. P. Martins1,2, Y. Lu1
1
University of Macau, Macao, China; 2University of Lisboa, Lisbon, Portugal
4:00 PM
31.7 A 3.6W 16V-Output 180ns-Response-Time 94%-Efficiency SC Sigma Converter
with Output Impedance Compensation and Ripple Mitigation for LiDAR Driver
Applications
C. Hu*1, X. Huang*1, X. Liu2, S. Du3, X. Liu4, J. Jiang1
1
2
3
Delft University of Technology, Delft, The Netherlands; 4Tsinghua University, Beijing, China
4:25 PM
31.8 A 11.7W 9mV/A-Cross-Regulation Single-Inductor Triple-Output Buck Converter
Using Unordered Power-Distributive Control for a 2A Load Transient
B. Wang, X. Wu, L. Cheng, University of Science and Technology of China, Hefei, China
4:50 PM
31.9 An 85-264 Vac to 3-4.2 Vdc 1.05W Capacitive Power Converter with Idle Power
Reduction and 4-Phase 1/10X SC Converter Achieving 5.11mW Quiescent Power
and 78.2% Peak Efficiency
G. Liu1,2, H. Wu1, C. Hu1, C. Huang3, X. Liu2, J. Jiang1
1
2
Chinese University of Hong Kong, Shenzhen, China; 3Iowa State University, Ames, IA
5:05 PM
31.10 A Fully Integrated 500V, 6.25MHz GaN-IC for Totem-Pole PFC Off-Line Power
Conversion
N. Deneke, B. Wicht, Leibniz University Hannover, Hannover, Germany
5:20 PM
31.11 A Capacitor-Based Bias-Flip Rectifier with Electrostatic Charge Boosting for
Triboelectric Energy Harvesting Achieving Auto-MPPT at Breakdown Voltage
and 14× Power Extraction Improvement
W. Peng, X. Yue, L. Pakula, S. Du, Delft University of Technology, Delft, The Netherlands
Conclusion 5:35 PM
52
Power Amplification and Signal Generation
Session Chair: Ruonan Han, Massachusetts Institute of Technology,
Cambridge, MA
Session Co-Chair: Henrik Sjöland, Lund University, Ericsson Research,
Lund, Sweden
1:30 PM
32.1 A 47GHz 4-Way Doherty PA with 23.7dBm P1dB and 21.7% / 13.1% PAE
at 6/12dB Back-Off Supporting 2000MHz 5G NR 64-QAM OFDM
X. Zhang*, H. Guo*, T. Chi, Rice University, Houston, TX
1:55 PM
32.2 A 24.25-to-29.5GHz Extremely Compact Doherty Power Amplifier with
Differential-Breaking Phase Offset Achieving 23.7% PAEavg for 5G
Base-Station Transceivers
H. Oh, S. Park, J. Lee, S. Baek, J. Jung, T. Kim, J. Kim, W. Lee, J-H. Park, K. Kim,
D-H. Lee, S. Lee, J. H. Lee, J. H. Kim, Y. Kim, S. Park, B. Suh, S. Oh, D. Lee, S. Jeon,
J. Son, S-G. Yang, Samsung Electronics, Suwon, Korea
2:20 PM
32.3 A Load-Variation-Tolerant Doherty Power Amplifier with
Dual-Adaptive-Bias Scheme for 5G Handsets
S. Imai, H. Sato, K. Mukai, H. Okabe, Murata, Kyoto, Japan
2:45 PM
32.4 A 67.8-to-108.2GHz Power Amplifier with a Three-Coupled-Line-Based
Complementary-Gain-Boosting Technique Achieving 442GHz GBW and
23.1% peak PAE
W. Wu, X. Bao, S. Chen, Y. Wang, L. Zhang, Tsinghua University, Beijing, China
3:00 PM
32.5 E-band (71-to-86GHz) GaN Power Amplifier with 4.37W Output Power
and 18.5% PAE for 5G Backhaul
B. Cimbili1,2,3, M. Bao2, C. Friesicke1, R. Quay1,3, 1Fraunhofer IAF, Freiburg, Germany
2
Ericsson, Gothenburg, Sweden; 3University of Freiburg, Freiburg, Germany
Break 3:15 PM
3:35 PM
32.6 A 76-to-81GHz Direct-Digital 7b 14GS/s Double-Balanced I/Q Mixing-DAC
Radar-Waveform Synthesizer
M. Neofytou1,2, K. Doris1,2, M. Ganzerli1, M. Lont1, G. I. Radulov2
1
NXP Semiconductors, Eindhoven, The Netherlands
2
Eindhoven University of Technology, Eindhoven, The Netherlands
4:00 PM
32.7 A 25.2dBm PSAT, 35-to-43GHz VSWR-Resilient Chain-Weaver Eight-Way
Balanced PA with an Embedded Impedance/Power Sensor
M. Pashaeifar, A. K. Kumaran, L. C. de Vreede, M. S. Alavi
4:25 PM
32.8 A 27.8-to-38.7GHz Load-Modulated Balanced Power Amplifier with
Scalable 7-to-1 Load-Modulated Power-Combine Network Achieving
27.2dBm Output Power and 28.8%/23.2%/16.3%/11.9% Peak/6/9/12dB
Back-Off Efficiency
W. Zhu1, J. Ying1, L. Chen2, J. Zhang2, G. Lv2, X. Yi2, Z. Zhao1, Z. Wang1, Y. Wang2,
W. Chen2, H. Sun1
1
Beijing Institute of Technology, Beijing, China; 2Tsinghua University, Beijing, China
4:50 PM
32.9 An Ultra-Compact 28GHz Doherty Power Amplifier with an
Asymmetrically-Coupled-Transformer Output Combiner
E. Liu1,2, H. Wang1, 1ETH Zurich, Zurich, Switzerland
2
5:05 PM
32.10 A Compact Broadband VSWR-Resilient True Power and Gain Sensor
with Dynamic-Range Compensation for Phased-Array Applications
E. Liu*1, D. Munzer*2, J. Lee2, H. Wang1
1
ETH Zurich, Zurich, Switzerland; 2Georgia Institute of Technology, Atlanta, GA
Conclusion 5:20 PM
53
Intelligent Neural Interfaces and Sensing Systems
Session Chair: Jerald Yoo, National University of Singapore,
Singapore, Singapore
Session Co-Chair: Mehdi Kiani, The Pennsylvania State University,
University Park, PA
1:30 PM
33.1 A High-Accuracy and Energy-Efficient Zero-Shot-Retraining Seizure-Detection
Processor with Hybrid-Feature-Driven Adaptive Processing and Learning-Based
Adaptive Channel Selection
J. Liu1, X. Liu1, X. Wang1, Z. Xie1, Z. Zhong1, J. Fan1, H. Qiu1, Y. Xu1, H. Qin1, Y. Long1, Y. Zhou2,
Z. Shen3, L. Zhou1, L. Chang1, S. Liu1, S. Lin1, C. Wang3, J. Zhou1
1
2
West China Hospital of Sichuan University, Chengdu, China
3
Huazhong University of Science and Technology, Wuhan, China
1:55 PM
33.2 A Sub-1μJ/class Headset-Integrated Mind Imagery and Control SoC for VR/MR
Applications with Teacher-Student CNN and General-Purpose Instruction Set
Architecture
Z. Zhong*, Y. Wei*, L. C. Go, J. Gu, Northwestern University, Evanston, IL
2:20 PM
33.3 MiBMI: A 192/512-Channel 2.46mm2 Miniaturized Brain-Machine Interface Chipset
Enabling 31-Class Brain-to-Text Conversion Through Distinctive Neural Codes
M. Shaeri1,2, U. Shin1,2,3, A. Yadav1,2, R. Caramellino4, G. Rainer1,4, M. Shoaran1,2
1
EPFL, Lausanne, Switzerland; 2Neuro-X Institute, Geneva, Switzerland
3
Cornell University, Ithaca, NY; 4University of Fribourg, Fribourg, Switzerland
2:45 PM
33.4 A Multi-Loop Neuromodulation Chipset Network with Frequency-Interleaving Front-
End and Explainable AI for Memory Studies in Freely Behaving Monkeys
Y. Hou1, Y. Zhu1, X. Wu1, Y. Li1, T. Lucas2, A. Richardson3, X. Liu1
1
University of Toronto, Toronto, Canada; 2Ohio State University, Columbus, OH
3
3:00 PM
33.5 Closed-Loop 100-Channel Highly-Scalable Retinal Implant with 1.02μW Analog
ED-Based Adaptive-Threshold Spike Detection and Poisson-Coded Temporally
Distributed Optogenetic Stimulation
T. Yousefi, G. Zoidl, H. Kassiri, York University, Toronto, Canada
Break 3:15 PM
3:35 PM
33.6 A Millimetric Batteryless Biosensing and Stimulating Implant with Magnetoelectric
Power Transfer and 0.9pJ/b PWM Backscatter
Z. Yu*, H-C. Liao*, F. Alrashdan, Z. Wen, Y. Zou, J. Woods, W. Wang, J. T. Robinson, K. Yang
Rice University, Houston, TX; *Equally Credited Authors (ECAs)
4:00 PM
33.7 An Adhesive Interposer-Based Reconfigurable Multi-Sensor Patch Interface with
On-Chip Application Tunable Time-Domain Feature Extraction
J. Cho*, Y. J. Pyeon*, J. Yeom*, H. Kim*, S. Cho, Y. Kim, T. Kim, J-H. Kwak, G. Choi, Y. Lee,
H. Shin, H. E. Jeong, J. Kim, Ulsan National Institute of Science and Technology, Ulsan, Korea
4:25 PM
33.8 A Two-Electrode Bio-Impedance Readout IC with Complex-Domain Noise-
Correlated Baseline Cancellation Supporting Sinusoidal Excitation
S-I. Cheon*1, H. Choi*1, G. Yun1, S. Oh1, J-H. Suh1, S. Ha2, M. Je1
1
2
New York University Abu Dhabi, Abu Dhabi, United Arab Emirates
4:50 PM
33.9 A Miniature Neural Interface Implant with a 95% Charging Efficiency Optical
Stimulator and an 81.9dB SNDR ΔΣM-Based Recording Frontend
L. Zhao1, W. Shi2, Y. Gong3, X. Liu3, W. Li3, Y. Jia1, 1University of Texas, Austin, TX
2
Meta, Santa Clara, CA; 3Michigan State University, East Lansing, MI
5:05 PM
33.10 A 2.7ps-ToF-Resolution and 12.5mW Frequency-Domain NIRS Readout IC with
Dynamic Light Sensing Frontend and Cross-Coupling-Free Inter-Stabilized Data
Converter
Z. Ma1, Y. Lin1, C. Chen1, X. Qi1, Y. Li1, K-T. Tang2, F. Wang3, T. Zhang4, G. Wang1, J. Zhao1
1
Shanghai Jiao Tong University, Shanghai, China; 2National Tsing Hua University, Hsinchu, Taiwan
3
Shanghai United Imaging Microelectronics Technology, Shanghai, China
4
Shanghai Mental Health Center, Shanghai, China
5:20 PM
33.11 A Hybrid Recording System with 10kHz-BW 630mVPP 84.6dB-SNDR
173.3dB-FOMSNDR and 5kHz-BW 114dB-DR for Simultaneous ExG and Biocurrent
Acquisition
T. Seol, G. Kim, S. Lee, S. Kim, D. Kim, J. Wie, Y. Shin, H. Kang, J. E. Jang, A. K. George, J. Lee
Conclusion 5:35 PM
54
Compute-In-Memory
Session Chair: Ankur Agrawal, IBM T. J. Watson Research Center,
Session Co-Chair: Eric Wang, TSMC, Hsinchu City, Taiwan
1:30 PM
34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for
High-Accuracy AI Application
Y. Wang, X. Yang, Y. Qin, Z. Zhao, R. Guo, Z. Yue, H. Han, S. Wei, Y. Hu, S. Yin
1:55 PM
34.2 A 16nm 96Kb Integer-Floating-Point Dual-Mode Gain-Cell-Computing-in-Memory
Macro with 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices
W-S. Khwa*1, P-C. Wu*2, J-J. Wu1, J-W. Su2,3, H-Y. Chen2, Z-E. Ke2, T-C. Chiu2, J-M. Hsu2,
C-Y. Cheng2, Y-C. Chen2, C-C. Lo2, R-S. Liu2, C-C. Hsieh2, K-T. Tang2, M-F. Chang1,2
1
TSMC Corporate Research, Hsinchu, Taiwan; 2National Tsing Hua University, Hsinchu, Taiwan
3
Industrial Technology Research Institute, Hsinchu, Taiwan
2:20 PM
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with
Compressed Adder Tree and Analog-storage Quantizers for Transformer and CNNs
A. Guo1, X. Chen1, F. Dong1, J. Chen1, Z. Yuan2,3, X. Hu3, Y. Zhang2, J. Zhang1, Y. Tang1, Z. Zhang1,
G. Chen3, D. Yang3, Z. Zhang1, L. Ren1, T. Xiong1, B. Wang1, B. Liu1, W. Shan1, X. Liu1, H. Cai1,
G. Sun2, J. Yang1, X. Si1
1
2
3
HOUMO, Beijing, China
2:45 PM
34.4 A 3nm 32.5 TOPS/W, 55.0 TOPS/mm2 and 3.78 Mb/mm2 Fully Digital
Computing-in-Memory Supporting INT12 x INT12 with Parallel MAC Architecture
and Foundry 6T SRAM Bitcell
H. Fujiwara1, H. Mori1, W-C. Zhao1, K. Khare1, C-E. Lee1, X. Peng2, V. Joshi3,
C-K. Chuang1, S-H. Hsu1, T. Hashizume4, T. Naganuma4, C-H. Tien1, Y-Y. Liu1,
Y-C. Lai1, C-F. Lee1, T-L. Chou1, K. Akarvardar2, S. Adham3, Y. Wang1, Y-D. Chih1,
Y-H. Chen1, H-J. Liao1, T-Y. J. Chang1
1
TSMC, Hsinchu, Taiwan; 2TSMC, San Jose, CA
3
TSMC, Ottawa, Canada; 4TSMC, Yokohama, Japan
3:00 PM
34.5 A 818-4094 TOPS/W Capacitor-Reconfigured CIM Macro for Unified Acceleration
of CNNs and Transformers
K. Yoshioka, Keio University, Yokohama, Japan
Break 3:15 PM
3:35 PM
34.6 A 28nm 72.12-TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point
SRAM Computing-in-Memory Macro with Logarithm Bit-Width Folding ADC
Y. Yuan1,2, Y. Yang3, X. Wang3, X. Li3, C. Ma1,2, Q. Chen3, M. Tang3, X. Wei3, Z. Hou3, J. Zhu1,2,
H. Wu1,2, Q. Ren1,2, G. Xing1, P-I. Mak4, F. Zhang1
1
2
University of Chinese Academy of Sciences, Beijing, China
3
Beijing Institute of Technology, Beijing, China; 4University of Macau, Macau, China
4:00 PM
34.7 A 28nm 2.4Mb/mm2 6.9-16.3 TOPS/mm2 eDRAM-LUT-Based Digital-
Computing-in-Memory Macro with In-Memory Encoding and Refreshing
Y. He1, S. Fan1, X. Li1, L. Lei1, W. Jia1, C. Tang1, Y. Li1, Z. Huang1, Z. Du1, J. Yue2, X. Li1, H. Yang1,
H. Jia1, Y. Liu1
1
Tsinghua University, Beijing, China; 2Chinese Academy of Sciences, Beijing, China
4:25 PM
34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with
31.2 TFLOPS/W for AI Edge Devices
T-H. Wen*1, H-H. Hsu*1,2, W-S. Khwa*2, W-H. Huang1, Z-E. Ke1, Y-H. Chin1, H-J. Wen1,
Y-C. Chang1, W-T. Hsu1, C-C. Lo1, R-S. Liu1, C-C. Hsieh1, K-T. Tang1, S-H. Teng3, C-C. Chou3,
Y-D. Chih3, T-Y. J. Chang3, M-F. Chang1,2
1
National Tsing Hua University, Hsinchu, Taiwan
2
TSMC Corporate Research, Hsinchu, Taiwan
3
4:50 PM
34.9 A Flash-SRAM-ADC Fused Plastic Computing-in-Memory Macro for Learning in
Neural Networks in a Standard 14nm FinFET Process
L. Wang1,2, W. Li1,2, Z. Zhou1,2, H. Gao1,2, Z. Li1,2, W. Ye1,2, H. Hu1, J. Liu1, J. Yue1, J. Yang1, Q. Luo1,
C. Dou1,2, Q. Liu1,3, M. Liu1,3
1
2
University of Chinese Academy of Sciences, Beijing, China
3
Conclusion 5:15 PM
55
SHORT COURSE Thursday, February 22nd, 8:00 AM
Machine Learning Hardware:
Considerations and Accelerator Approaches
Time: Topic:
8:00 AM Breakfast
8:25 AM Introduction by Chair, Daniel Friedman

IBM Thomas J. Watson Research Center, Yorktown Heights, NY
8:30 AM Introduction to Machine Learning Applications and

Hardware-Aware Optimizations
Ranghajaran Venkatesan, Nvidia, Santa Clara, CA
10:00 AM Break
10:30 AM Architecture and Design Approaches to ML Hardware Acceleration:

Performance Compute Environment
Leland Chang, IBM Thomas J. Watson Research Center,
Yorktown Heights, NY,
12:15 PM Lunch
1:20 PM Architecture and Design Approaches to ML Hardware Acceleration:

Edge and Mobile Environments
Marian Verhelst, KU Leuven, Leuven, Belgium
2:50 PM Break
3:20 PM Emerging ML Accelerator Approaches: In-Memory Computing

Architectures
Naresh Shanbhag, University of Illinois Urbana-Champaign,
Champaign, IL
4:50 PM Conclusion
Introduction
The growth in the application of machine learning and artificial intelligence
technology to problems across virtually all spheres of endeavor has been and is
expected to remain extraordinary. Hardware acceleration for machine learning
tasks is a critical vector that has enabled this exceptionally rapid growth. Further
accelerator advances are necessary to drive everything from improved efficiency
for inference, to support ever-growing network sizes to improvements in support
for network training, to enabling broadening of ML deployments across
platforms with a wide range of power and performance envelopes. In this short
course, we will first present an overview of machine learning and inference,
including describing key metrics, frameworks, application areas, and approaches
to support model scaling. In the second presentation, we will discuss
architectural and design approaches to ML hardware acceleration for applications
in high performance compute environments. In the third presentation, we will
turn to approaches to mapping ML hardware acceleration to constrained
compute footprint contexts as in edge and mobile applications. Finally, we will
present a framework for considering a key emerging topic in hardware design
for ML acceleration, namely, compute-in-memory approaches.
56
SHORT COURSE Thursday, February 22nd, 8:30 AM
SC1:
Introduction to Machine Learning Applications
and Hardware-Aware Optimizations
Ranghajaran Venkatesan, Nvidia, Santa Clara, CA
Deep neural networks (DNNs) have become a crucial solution for tackling complex
challenges in a wide range of fields, such as image recognition, natural language
processing, robotics, healthcare, and autonomous driving. The landscape of DNN
applications is constantly expanding, driving the ongoing evolution of DNN
models. These models come in various architectures, including convolutional
neural networks, transformers, diffusion models, and more, each tailored to meet
the unique demands of their respective applications. These DNN models vary
significantly in size and computational complexity, driving the need for efficient
neural-network computing chips. This has led to a growing exploration of
hardware and software co-design techniques, balancing energy efficiency and
performance without compromising accuracy. This short course offers an
introductory exploration of different neural network models, shedding light on
their individual characteristics and applications. It also delves into various design
strategies, emphasizing the importance of achieving a delicate balance between
efficiency, scalability, and adaptability across different neural network paradigms,
all while paving the way for the emergence of efficient neural network models and
computing architectures.
Rangharajan Venkatesan is a Senior Research Scientist in the ASIC & VLSI
Research group in NVIDIA. He received the B.Tech. degree in Electronics and
Communication Engineering from the Indian Institute of Technology, Roorkee in
2009 and the Ph.D. degree in Electrical and Computer Engineering from Purdue
University in 2014. His research interests are in the areas of low-power VLSI
design and computer architecture with particular focus in deep learning
accelerators, high-level synthesis, and spintronic memories. He has received Best
Paper Awards for his work on deep learning accelerators from the IEEE/ACM
Symposium on Microarchitecture (MICRO) and the Journal of Solid-State Circuits
(JSSC). His work on spintronic memory design was recognized with the Best
Paper Award at the International Symposium on Low Power Electronics and
Design (ISLPED), and Best paper nomination at the Design, Automation and Test
in Europe (DATE). His paper titled, “MACACO: Modeling and Analysis of Circuits
for Approximate Computing”, received the IEEE/ACM International Conference on
Computer-Aided Design (ICCAD) Ten Year Retrospective Most Influential Paper
Award in 2021. He has served as a member of the technical program committees
of several leading IEEE/ACM conferences including ISSCC, DAC, MICRO, and
ISLPED.
SC2:
Architecture and Design Approaches to ML Hardware
Acceleration: Performance Compute Environment
Leland Chang, IBM Thomas J. Watson Research Center, Yorktown Heights, NY
With the recent explosion in generative AI and large language models, hardware
acceleration has become particularly important in high-performance compute
environments. In such applications, AI accelerators should address a broad range
of AI models and enable workflows spanning model pre-training, fine-tuning, and
inference. System-level design and software co-optimization must be considered
to balance compute and communication costs, especially with inference
workloads driving aggressive latency targets and model size growth driving the
use of distributed systems. This talk will discuss these considerations in the
context of high-performance system deployments and explore approaches to AI
accelerator circuit design as well as research roadmaps to improve both compute
efficiency and communication bandwidth.
Leland Chang is a Principal Research Scientist and the Senior Manager of AI
Hardware at IBM Research, where he leads a team developing AI hardware
accelerators for next-generation server and mainframe products. He has worked
across technology, circuits, architecture, and software with key technical
contributions to FinFET technologies, SRAM scaling, integrated voltage regulators,
and AI accelerators. He received the B. S., M. S., and Ph.D. degrees in EECS from
UC Berkeley and has authored 100 technical articles and 135 patents. He is a
former memory subcommittee chair of the ISSCC technical program committee.
57
SHORT COURSE Thursday, February 22nd, 1:20 PM
SC3:
Architecture and Design Approaches to ML Hardware
Acceleration: Edge and Mobile Environments
Marian Verhelst, KU Leuven, Leuven, Belgium
Various applications demand more and more powerful machine inference in

resource-scarce distributed devices, such as phones, watches, glasses, robots or
drones. To allow intelligent applications at ultra-low energy and low latency, one
needs customized processor architectures optimized for extreme edge
applications. This need has resulted in the creation of a wide variety of novel
hardware architectures, supported by HW-algorithm co-optimization methods.
This talk will zoom into ML processor architectures for the edge, as well as tools
for efficient mapping of ML algorithms onto such architectures.
Marian Verhelst is professor at the MICAS laboratories of KU Leuven and a

research director at imec. Her research focuses on embedded machine learning,
hardware accelerators, HW-algorithm co-design and low-power edge processing.
She received a PhD from KU Leuven in 2008, and worked as a research scientist
at Intel Labs from 2008 till 2010. Marian currently is a member of the board of
directors of tinyML, scientific advisor to multiple startups and active in the TPC’s
of DATE and ESSCIRC. She enjoys science communication as an IEEE SSCS
Distinguished Lecturer, as a regular member of the Nerdland science podcast
(Dutch), and as the founding mother of KU Leuven’s InnovationLab high school
program.
SC4:
Emerging ML Accelerator Approaches:
In-Memory Computing Architectures
Naresh Shanbhag, University of Illinois Urbana-Champaign, Champaign, IL
Naresh R. Shanbhag is the Jack Kilby Professor of Electrical and Computer

Engineering at the University of Illinois at Urbana-Champaign. He received his
Ph.D. degree from the University of Minnesota (1993) in Electrical Engineering.
From 1993 to 1995, he worked at AT&T Bell Laboratories at Murray Hill where he
led the design of high-speed transceiver chipsets for very-high-speed digital
subscriber line (VDSL), before joining the University of Illinois at Urbana-
Champaign in August 1995. He has held visiting faculty appointments at the
National Taiwan University (Aug.-Dec. 2007) and Stanford University (Aug.-Dec.
2014). His research focuses on the design of energy-efficient systems for machine
learning, communications, and signal processing, spanning algorithms, VLSI
architectures, and integrated circuits. He has more than 200 publications in this
area, holds thirteen US patents, and is a co-author of two books and multiple book
chapters (see https://shanbhag.ece.illinois.edu/ for details).
Naresh R. Shanbhag received the 2018 SIA/SRC University Researcher Award,

became an IEEE Fellow in 2006, received the 2010 Richard Newton GSRC
Industrial Impact Award, the IEEE Circuits and Systems Society Distinguished
Lecturership in 1997, the National Science Foundation CAREER Award in 1996,
and multiple best paper awards. In 2000, Dr. Shanbhag co-founded and served
as the Chief Technology Officer of the Intersymbol Communications, Inc., which
introduced mixed-signal ICs for electronic dispersion compensation of OC-192
optical links, and became a part of Finisar Corporation in 2007. From 2013-17,
he was the founding Director of the Systems On Nanoscale Information fabriCs
(SONIC) Center, a 5-year multi- university center funded by DARPA and SRC under
the STARnet program. He is currently on the leadership teams of the JUMP 2.0
DARPA and SRC funded Centers for Ubiquitous Connectivity (CUbiC) and
Codesign of Cognitive Systems (CoCoSys), and the NSF-industry funded Center
for Advanced Semiconductor Chips for Accelerated Performance (ASAP).
58
FORUM 3 Thursday, February 22nd, 8:00 AM
Digitally Enhanced Analog Circuits:
Trends & State-of-the-art Designs
Organizer: Ben Calhoun, University of Virginia,
Charlottesville, VA
Co-Organizers: Visvesh Sathe, Georgia Institute of Technology, Atlanta, GA

Jiawei Xu, Fudan University, Shanghai, China
Jeff Walling, Virginia Tech, Blacksburg, VA
Masum Hossain, Carleton University, Ottawa, Canada
Yan Lu, University of Macau, Macao, China
Champions: Makoto Nagata, Kobe University, Kobe, Japan
Man-Kay Law, University of Macau, Macau, China
Traditional all-analog circuits consume large area, power, and design time in
advanced technology nodes and are highly susceptible to process, voltage, and
temperature (PVT) parameter variations. Digital circuits with analog functionality
or digitally assisted analog circuits help to mitigate these challenges. Digital
circuits require less area and power, offer fast time-to-market, provide greater
tolerance to PVT variations, and enable critical storage, programmability, and
runtime computational capabilities that enhance traditional analog circuits through
techniques like calibration and signal processing.
This forum presents the recent treads and state-of-the-art designs for digitally
enhanced analog circuits while highlighting the specific circuit components more
favorable to digital or analog implementations to improve target metrics in analog,
mixed-signal, RF, and power management systems.
Agenda
Time Topic
8:00 AM Breakfast
Ben Calhoun, University of Virginia, Charlottesville, VA
8:25 AM Extending and Augmenting Analog with Digital to Overcome
Technology Scaling Limitations
Alvin Loke, NXP, San Diego, CA
9:15 AM Digitally Enhanced Clock Generation and Distribution
Ping-Hsuan Hsieh, National Tsing Hua University,
Hsinchu City, Taiwan
10:05 AM Break
10:20 AM From Microwatts to Terawatts: Managing GPU Power
Tawfik Rahal-Arabi, AMD, Bellevue, WA
11:10 AM Digital and Mixed-Signal ADC Enhancement Techniques
Pieter Harpe, Eindhoven University of Technology,
12:00 PM Lunch
1:20 PM Sensitivity and Robustness Enhancement of Ultra-Low Power
Digitally Assisted Wakeup Receivers
Steven Bowers, University of Virginia, Charlottesville, VA
2:10 PM Digitally Enhanced Transceiver for High-Speed Signalling
Charlie Boecker, Microsoft, Ames, IA
3:00 PM Break
3:15 PM Applications of Time-Domain Circuits in SoC’s
Steven Kosonocky, Uhnder, Austin, TX
4:05 PM Analog Enhanced Digital and Memory Circuits
Jaydeep Kulkarni, University of Texas Austin, Austin TX
59
Intelligent Sensing
Organizers: Kea-Tiong Tang, National Tsing Hua University,
Hsinchu, Taiwan
Mahsa Shoaran, EPFL, Lausanne, Switzerland
Co-Organizers: Rangharajan Venkatesan, NVIDIA, Santa Clara, CA

Marco Berkhout, Goodix Technology, Nijmegen,
The Netherlands
Takeshi Sugawara, The University of
Electro-Communications, Tokyo, Japan
Champions: Bruce Rae, STMicroelectronics,
Edinburgh, United Kingdom
Makoto Ikeda, University of Tokyo, Tokyo, Japan
The forum lies at the interface of sensors and machine learning - including ML
architectures for in/near-sensor computing such as biomedical, imaging,
environmental, etc. It will cover analog-only architectures, in-memory compute,
edge computing, accelerator architectures and technologies that integrate with
sensors. The forum will discuss edge compute system tradeoffs in sensor-based
applications, system integrations, cloud versus edge computing, and more.
Agenda
Time Topic
8:00 AM Breakfast
Kea-Tiong Tang, National Tsing Hua University, Hsinchu, Taiwan
Mahsa Shoaran, EPFL, Lausanne, Switzerland
8:25 AM Hope for the Best, but Plan for the Worst: Considering Risk and
its Mitigation when Designing Intelligent Sensing Systems
Timothy Denison, University of Oxford, Oxford, United Kingdom
9:15 AM Intelligent Vision Using Smart Imager with Processing-in-Sensor
Techniques
Chih-Cheng Hsieh, National Tsing Hua University, Hsinchu, Taiwan
10:05 AM Break
10:20 AM Activity-Driven Perception for Intelligent Edge Sensory Systems
Shih-Chii Liu, University of Zurich and ETH Zurich,
Zurich, Switzerland
11:10 AM Event-Driven Sensory Analog Processing and Massively Parallel
Mixed-Signal in-Memory Computing for Distributed Adaptive
Intelligence at the Edge
Gert Cauwenberghs, UC San Diego, La Jolla, CA
12:00 PM Lunch
1:20 PM Cross-Layer Innovations for Enabling Real-Time and Efficient
Eye Tracking in VR/AR
Yingyan Lin, Georgia Institute of Technology, Atlanta, GA
2:10 PM Aggressive Design Reuse for Ubiquitous Security -
From Design-Time to Run-Time Intelligent Attack Detection
and Counteraction
Massimo Alioto, Nat U Singapore, Singapore
3:00 PM Break
3:15 PM Implementing on-Sensor Machine Learning for Ultralow Power,
Always-on Inferencing at the Extreme Edge
Mahesh Chowdhary, STMicroelectronics, Santa Clara, CA
4:05 PM Benefits of System Architecture re-Design for 3D Chiplet
Integration Technologies
Dragomir Milojevic, IMEC, Leuven, Belgium
60
Recent Developments in High-Performance Frequency
Synthesis Circuits and Systems
Organizers: Masoud Babaie, Delft University of Technology, Delft,
The Netherlands
Co-Organizers: Jan Prummel, Renesas Design Netherlands,

’s-Hertogenbosch, The Netherlands
Wei-Zen Chen, National Yang Ming Chiao Tung University,
Hsinchu, Taiwan
Danielle Griffith, Texas Instruments, Dallas, TX
Akihide Sai, Toshiba, Kawasaki, Japan
Champions: Matteo Bassi, Infineon Technologies, Villach, Austria
Arun Natarajan, Oregon State University, Corvallis, OR
Frequency synthesizers are among the most critical blocks in wireless, wireline,
and digital clocking applications. This forum will cover the latest advances in
frequency synthesis circuits and systems to efficiently generate LO signals with
low phase noise, low spurious tones, and large modulation bandwidth. Prior-art
techniques will be discussed in-depth, such as energy-efficient reference clocks,
high-FOM wide-tuning range VCOs, low-cost low-power PLLs, and modern
fractional-N digital PLLs. Special attention will also be given to pulling and spur
mitigation techniques, and injection-locked frequency multipliers. The forum will
be concluded by exploring mm-wave PLLs for 5G communication systems, and
FMCW generation for high-performance car radars.
Agenda
Time Topic
8:00 AM Breakfast
Masoud Babaie, Delft University of Technology, Delft,
The Netherlands
8:25 AM High Performance Frequency Synthesis Utilizing BAW
Resonators
Michael Perrott, Texas Instruments, Manchester, NH
9:15 AM Design Techniques to Improve Phase Noise and Tuning Range
of Modern RF/mmW Oscillators
Mina Shahmohammadi, NXP Semiconductors, Delft,
The Netherlands
10:05 AM Break
10:20 AM Low-Power Fractional-N Digital PLL Design Techniques
Kenichi Okada, Tokyo Institute of Technology, Tokyo, Japan
11:10 AM High Performance Digital Fractional-N PLLs for Connectivity
Standards
Ashoke Ravi, Intel, Hillsboro, OR
12:00 PM Lunch
1:20 PM Design of Advanced Low-Jitter Ring Oscillator-Based ILCMs
Suneui Park, Samsung Electronics, Hwaseong, Korea
2:10 PM Prediction and Mitigation of Spurs in Fractional Synthesizers
Michael Peter Kennedy, University College Dublin, Dublin, Ireland
3:00 PM Break
3:15 PM DSM Noise Suppression in Analog Frequency Synthesizers:
From Low-Power Design to High-Performance
mm-Wave Design
David Murphy, Broadcom, Irvine, CA
4:05 PM Linearization Techniques for FMCW Generation in Car Radar
Applications
Luigi Grimaldi, Infineon Technologies, Villach, Austria
61
Toward Next Generation of Highly Integrated Electrical
and Optical Transceivers
Organizers: Mozhgan Mansuri, Intel, Hillsboro, OR
Jay Im, AMD, San Jose, CA
Co-Organizers: Didem Turker Melek, Cadence Design Systems,
San Jose, CA
Masum Hossain, Carleton University, Ottawa, Canada
Peter Ossieur, Imec, University of Ghent, Ghent, Belgium
Sudip Shekhar, University of British Columbia,
Vancouver, Canada
Tamer Ali, Mediatek, Irvine, CA
Champions: Bill Redman-White, HiLight Semiconductor, Southampton,

United Kingdom
Yohan Frans, AMD, San Jose, CA
The next generation of highly integrated transceivers for high throughput

applications poses significant design challenges in terms of power efficiency,
signal integrity, ISI and noise cancellation. This forum discusses the key issues
for deploying 100G+ SERDES and design approaches for 200G+, including noise
mitigation, power efficient analog/digital equalization schemes (CTLE, analog FFE,
DSP FFE/DFE/MLSD), modulation, and system integration (packaging, connectors,
etc).
Optical transceivers also play a crucial role in extending the reach of electrical
interconnects as data rates continue to increase. Various aspects of optical
transceivers based on silicon photonics are discussed, such as foundry
perspectives, directly modulated vs coherent optical links, packaging techniques
and fiber termination challenges. In addition, the forum covers emerging
technologies including co-packaged optics and heterogenous integration of both
photonic and electronic chiplets, promising denser integration while introducing
new challenges.
Agenda
Time Topic
8:00 AM Breakfast
Mozhgan Mansuri, Intel, Hillsboro, OR
8:25 AM Highlights and Challenges in Deploying 100G+ SERDES
Francis Lin, Mediatek, HsinChu, Taiwan
9:15 AM The Impact of Industry Trends on 200+Gbps Wireline R&D
Tony Carusone, Alphawave Semi and University of Toronto,
Toronto, Canada
10:05 AM Break
10:20 AM Beyond 200Gbps Electrical Transceivers – Circuit Architecture,
Design Implementation and Silicon Results
Ariel Cohen, Intel, Jerusalam, Israel
11:10 AM Modulation Schemes for Ultra-High-Speed Transceivers
Naim Ben-Hamida, Cienna, Ottawa, Canada
12:00 PM Lunch
1:20 PM Silicon Photonics Based High Throughput Optical Transceivers
Mayank Raj, AMD, San Jose, CA
2:10 PM Micro-Transfer Printing for Heterogeneous Electronic-Photonic
Integrated Circuits
Gunther Roelkens, Ghent University - imec, Ghent, Belguim
3:00 PM Break
3:15 PM Silicon Photonics and Foundry Requirements for AI Datacenters
Tom Gray, NVIDIA, Durham, NC
4:05 PM Electronic-Photonic Systems-on-Chip for Compute,
Communications and Sensing
Vladimir Stojanovic, UC Berkeley, Berkeley, CA
62
EXECUTIVE COMMITTEE
CONFERENCE CHAIR SRP CHAIR
Eugenio Cantatore Jerald Yoo
Eindhoven University of Technology National University of Singapore
Eindhoven, The Netherlands Singapore
CONFERENCE VICE-CHAIR ADCOM REPRESENTATIVE

Edith Beigné Jan van der Spiegel
Meta, Menlo Park, CA University of Pennsylvania
Philadelphia, PA
EXECUTIVE COMMITTEE SECRETARY
Makoto Nagata DIRECTOR OF PUBLICATIONS
Kobe University, Kobe, Japan Laura Fujino
PROGRAM CHAIR
Frank O’Mahony
PRESS LIAISON AND ARC CHAIR
Intel , Hillsboro, OR
Kenneth C. Smith*
PROGRAM VICE-CHAIR
Thomas Burd
PRESS COORDINATOR
Advanced Micro Devices
Santa Clara, CA Shahriar Mirabbasi
University of British Columbia
PAST PROGRAM CHAIR Vancouver, Canada
Piet Wambacq
imec , Heverlee, Belgium EDUCATION CHAIR
Ali Sheikholeslami
ITPC FAR-EAST REGIONAL CHAIR University of Toronto, Toronto, Canada
Man-Kay Law
University of Macau DIRECTOR OF OPERATIONS
Taipa, Macau, China Melissa Widerkehr
Widerkehr and Associates
ITPC FAR-EAST Lewes, DE
REGIONAL VICE-CHAIR
Jaehyouk Choi DIRECTOR OF FINANCE
Seoul National University John Weinmann
Korea Rochester, NY
ITPC EUROPEAN REGIONAL CHAIR WEB SITE AND A/V CHAIR

Matteo Bassi Trudy Stetzler
Infineon Technologies AG Halliburton, Houston, TX
Villach, Austria
STRATEGY ADVISORY GROUP CHAIR
ITPC EUROPEAN Bram Nauta
REGIONAL VICE-CHAIR University of Twente
Viola Schaffer Enschede, The Netherlands
Texas Instruments
Freising, Germany
SOCIAL MEDIA CHAIR
Carolina Mora-Lopez
ITPC NORTH AMERICA
Imec, Leuven, Belgium
REGIONAL CHAIR
Keith Bowman
WIC REPRESENTATIVE
Qualcomm, Raleigh, NC
Kathy Wilcox
ITPC NORTH AMERICA AMD, Boxborough, MA
REGIONAL VICE CHAIR
Jeff Walling Industry Chair
Virginia Tech, Blacksburg, VA Alicia Klinefelter
NVidia, Durham, NC
DEMO SESSION CHAIR
Patrick Mercier Industry Chair
University of California, San Diego Vivek De
La Jolla, CA Intel, Hillsboro, OR
*To a life well lived

Kenneth C. Smith
ISSCC volunteer since 1974 in various roles:
a member of the program committee,
Awards Chair, Press Chair, etc
63
INTERNATIONAL TECHNICAL PROGRAM COMMITTEE
Technical Editors & Multi-Media Coordinator
Jason H. Anderson James W. Haslett
University of Toronto, Toronto, Canada The University of Calgary, Calgary, Canada
Leonid Belostotski Shahriar Mirabbasi

The University of Calgary, Calgary, Canada University of British Columbia
Vancouver, Canada
Dustin Dunwell
Alphawave IP, Toronto, Canada
MULTI-MEDIA COORDINATOR
Vincent Gaudet AND DIGEST EDITOR
University of Waterloo, Waterloo, Canada
David Halupka
Glenn Gulak StarIC, Toronto, Canada
Analog Subcommittee
Chair: Maurits Ortmanns
Institute of Microelectronics University of Ulm, Ulm, Germany
Ippei Akita Drew Hall
AIST, Tsukuba, Japan University of California, San Diego
La Jolla, CA
Jens Anders
University of Stuttgart, Stuttgart, Germany Minkyu Je
Marco Berkhout
Goodix Technology Man-Kay Law
Nijmegen, The Netherlands University of Macau, Taipa, Macau, China
Chinwuba Ezekwe Viola Schaffer

Robert Bosch, Sunnyvale, CA Texas Instruments, Freising, Germany
Qinwen Fan Shon-Hang Wen

Delft University of Technology MediaTek, Hsinchu, Taiwan
Delft, The Netherlands
Jiawei Xu
Danielle Griffith Fudan University, Shanghai, China
Texas Instruments, Dallas, TX
Data Converters Subcommittee

Chair: Jan Westra
Broadcom, Bunnik, The Netherlands
Lucien J. Breems Shahrzad Naraghi

NXP Semiconductors, Eindhoven, Legato Logic, San Jose, CA
The Netherlands
Shanthi Pavan
Ping Gui IIT Madras, Chennai, India
Southern Methodist University, Dallas, TX
Hajime Shibata
Benjamin Herschberg Analog Devices, Toronto, Canada
Intel, Portland, OR
Shiyu Su
Jongwoo Lee University of Waterloo, Los Angeles, CA
Samsung Electronics, Gyunggi-do, Korea
Nan Sun
Ying-Zu Lin Tsinghua University, Beijing, China
Mediatek, Hsinchu, Taiwan
Yan Zhu
Nima Maghari University of Macau, Taipa, Macau, China
University of Florida, Gainesville, FL
64
Digital Architectures & Systems (DAS) Subcommittee
Chair: Rahul Rao
IBM India, Bangalore, India
Mark A. Anders Sugako Otani
Intel, Hillsboro, OR Renesas Electronics, Tokyo, Japan
Shidhartha Das Soojung Ryu

Advanced Micro Devices SAPEON Korea, Gyeonggi-do, Korea
Cambridge, United Kingdom
Sophia Shao
Ji-Hoon Kim UC Berkeley, Berkeley, CA
Ewha Womans University, Seoul, Korea
Rangharajan Venkatesan
Yongpan Liu NVIDIA, Santa Clara, CA
Chia-Hsiang Yang
Hugh Mair National Taiwan University, Taipei, Taiwan
MediaTek, Austin, TX
Digital Circuits (DCT) Subcommittee

Chair: Keith Bowman
Benton Calhoun Arijit Raychowdhury
University of Virginia, Charlottesville, VA Georgia Institute of Technology
Atlanta, GA
Eric Jia-Wei Fang
Mediatek, Hsinchu, Taiwan Akihide Sai
Toshiba, Kawasaki, Japan
Kazuki Fukuoka
Renesas Electronics, Tokyo, Japan Visvesh Sathe
Tanay Karnik
Intel, Hillsboro, OR Jae-sun Seo
Cornell Tech, New York, NY
Huichu Liu
Meta Agile Silicon Team Yvain Thonnart
Menlo Park, CA CEA-List, Grenoble, France
Jun-Seok Park Heein Yoon
Samsung Electronics Ulsan National Institute of Science
Gyeonggi-do, Korea and Technology
Ulsan, Korea
IMMD Subcommittee
Chair: Rikky Muller
University of California, Berkeley, Berkeley, CA
Jun-Chau Chien Carolina Mora-Lopez
National Taiwan University, Taipei, Taiwan Imec, Leuven, Belgium
Leonardo Gasparini Masaki Sakakibara
Fondazione Bruno Kessler, Trento, Italy Sony Semiconductor Solutions,
Kanagawa, Japan
Sohmyung Ha
New York University Sanshiro Shishido
New York University Abu Dhabi Panasonic Holdings, Osaka, Japan
Abu Dhabi, UAE
Mahsa Shoaran
Mutsumi Hamaguchi EPFL, Geneva, Switzerland
Sharp, Nara, Japan
Andreas Suess
Taekwang Jang OMNIVISION Technologies, Santa Clara, CA
ETH Zurich, Zurich, Switzerland
Kea-Tiong (Samuel) Tang
Mehdi Kiani National Tsing Hua University,
The Pennsylvania State University Hsinchu, Taiwan
University Park, PA
Johan Vanderhaegen
Seong-Jin Kim Google, Mountain View, CA
Ulsan National Institute of Science
and Technology Augusto Ximenes
Ulsan, Korea Meta Platforms, Redmond, WA
Junghyup Lee Jerald Yoo

DGIST, Daegu, Korea National University of Singapore
Singapore
65
Memory Subcommittee
Chair: Meng-Fan Chang
National Tsing Hua University, Hsinchu, Taiwan
Ankur Agrawal Seung-Jae Lee
IBM T. J. Watson Research Center Samsung, Gyeonggi-do, Korea
Ming Liu
Juang-Ying Chueh Fudan University, Shanghai, China
Etron Technology, Taipei, Taiwan
Violante Moschiano
Takashi Ito
Intel Italia, Rome, Italy
Renesas, Tokyo, Japan
Hidehiro Shiga
Eric Karl
Intel, Portland, OR KIOXIA, Yokohama, Japan
Dongkyun Kim Eric Wang

SK hynix, Gyeonggi-do, Korea TSMC, Hsinchu, Taiwan
Hye-Ran Kim John Wuu

Samsung Electronics, Gyeonggi-do, Korea Advanced Micro Devices, Fort Collins, CO
Power Management Subcommittee

Chair: Bernhard Wicht
University of Hannover, Hannover, Germany
Patrik Arno Xun Liu
STMicroelectronics, Grenoble, France The Chinese University of Hong Kong,
Shenzhen
Saurav Bandyopadhyay Shenzhen, China
Yan Lu
Ke-Horng Chen University of Macau, Taipa, Macao, China
National Yang Ming Chiao Tung University
Hsinchu, Taiwan Kousuke Miyaji
Lin Cheng
University of Science and Technology Jiseon Paek
of China Pusan National University, Pusan, Korea
Anhui, China
John Pigott
Shusuke Kawai NXP Semiconductors, Chandler, AZ
Gael Pillonnet
Xugang Ke CEA-Leti, Grenoble, France
Zhejiang University, Zhejiang,
Frank Prämaßing
Dongsu Kim Infineon Technologies Austria
Samsung Electronics, Gyeonggi-do, Korea Villach, Austria
Hyun-Sik Kim Xin Zhang

KAIST, Daejeon, Korea IBM T. J. Watson Research Center
Harish Krishnamurthy
Hanh-Phuc Le
University of California, San Diego
La Jolla, CA
66
RF Subcommittee
Chair: Brian Ginsburg
Masoud Babaie Yu-Li Hsueh
Delft University of Technology Mediatek, Hsinchu, Taiwan
Salvatore Levantino
Yves Baeyens Politecnico di Milano, Milano, Italy
Nokia - Bell Labs, Murray Hill, NJ
Xun Luo
Dmytro Cherniak University of Electronic Science
Infineon Technologies, Villach, Austria and Technology of China
Chengdu, China
Jaehyouk Choi
Seoul National University, Korea Swaminathan Sankaran
Wei Deng
Tsinghua University, Beijing, China Henrik Sjöland
Lund University, Lund, Sweden
Jeremy Dunworth
Qualcomm Technologies, San Diego, CA Jeff Walling
Virginia Tech, Blacksburg, VA
Hiroshi Hamada
NTT, Kanagawa Japan Wanghua Wu
Samsung Semiconductor, San Jose, CA
Ruonan Han
Massachusetts Institute of Technology Hongtao Xu
Cambridge, MA Fudan University, Shanghai, China
Mona Hella Jun Yin
Rensselaer Polytechnic Institute, Troy, NY University of Macau, Taipa, Macau, China
Security Subcommittee
Chair: Ingrid Verbauwhede
KU Leuven, Leuven, Belgium
Utsav Banerjee Thomas Poeppelmann
Indian Institute of Science, Karnataka, India Infineon Technologies, Neubiberg, Germany
Chiraag Juvekar Shreyas Sen
Apple, San Carlos, CA Purdue University, West Lafayette, IN
Yong Ki Lee Takeshi Sugawara
Samsung Electronics, Gyeonggi-do, Korea The University of Electro-Communications
Tokyo, Japan
Sanu Mathew
TD Subcommittee
Chair: Ali Hajimiri
Caltech, Pasadena, CA
Firooz Aflatouni Daniel H. Morris
University of Pennsylvania, Philadelphia, PA Meta, Sunnyvale, CA
Joseph Bardin Fabio Sebastiano
Google & UMass Amherst, Goleta, CA Delft University of Technology
Denis Daly
Apple, Wellesley, MA Kaushik Sengupta
Giorgio Ferrari
Politecnico di Milano, Milano, Italy Sudip Shekhar
University of British Columbia
Shawn Shuo-Hung Hsu
Vancouver, Canada
National Tsing Hua University
Hsinchu, Taiwan Guy Torfs
Ghent University, Gent, Belgium
Kyeongha Kwon
KAIST, Daejeon, Korea Rabia Tugce Yazicigil
Boston University, Boston, MA
Noriyuki Miura
Osaka University, Osaka, Japan Milin Zhang
Alyosha Molnar
Cornell University, Ithaca, NY
67
Wireless Subcommittee
Chair: Chih-Ming Hung
MediaTek, Taipei, Taiwan
Matteo Bassi Negar Reiskarimian
Infineon Technologies, Villach, Austria Massachusetts Institute of Technology
Cambridge, MA
Venumadhav Bhagavatula
Samsung Semiconductor, San Jose CA Bodhisatwa Sadhu
IBM T. J. Watson Research Center
Wu-Hsin Chen Yorktown Heights, NY
Qualcomm, San Diego, CA
Shahriar Shahramian
Vito Giannini Nokia – Bell Labs, New Providence, NJ
Uhnder, Austin, TX
Ho-Jin Song
Giuseppe Gramegna Pohang University of Science and Technology
imec, Leuven, Belgium Pohang, Korea
Jane Gu David Wentzloff
University of California, Davis University of Michigan, Everactive
Davis, CA Ann Arbor, MI
Renzhi Liu Yun Yin
Intel, Hillsboro, OR Fudan University, Shanghai, China
Byung-Wook Min Yuanjin Zheng
Yonsei University, Seoul, Korea Nanyang Technological University
Jan Prummel Singapore, Singapore
Renesas Design Netherlands Alireza Zolfaghari
‘s-Hertogenbosch, The Netherlands Broadcom, Irvine, CA
Wireline Subcommittee
Chair: Thomas Toifl
Cisco Systems, Thalwil, Switzerland
Tamer Ali Jay Im
Mediatek, Irvine, CA AMD, San Jose, CA
Wei-Zen Chen Mozhgan Mansuri

National Yang Ming Chiao Tung University Intel, Hillsboro, OR
Hsinchu, Taiwan
Didem Turker Melek
Zeynep Deniz Cadence Design Systems, San Jose, CA
IBM, Yorktown Heights, NY
Peter Ossieur
Masum Hossain Imec, University of Ghent
Carleton University, Ottawa, Canada Ghent, Belgium
Kenny Hsieh Ben Rhew

TSMC, Hsinchu, Taiwan Samsung, Gyeonggi-do, Korea
68
EUROPEAN REGIONAL SUBCOMMITTEE
ITPC EUROPEAN REGIONAL CHAIR
Matteo Bassi
Infineon Technologies AG, Villach, Austria
ITPC EUROPEAN REGIONAL VICE CHAIR

Viola Schaffer
Texas Instruments, Freising, Germany
ITPC EUROPEAN REGIONAL SECRETARY

Jens Anders
University of Stuttgart, Stuttgart, Germany
Patrik Arno Maurits Ortmanns

STMicroelectronics, Grenoble, France University of Ulm, Ulm, Germany
Masoud Babaie Peter Ossieur

Delft University of Technology Imec, Univ. Ghent, Ghent, Belgium
Gael Pillonnet
Marco Berkhout CEA-Leti, Grenoble, France
Goodix Technology
Nijmegen, The Netherlands Thomas Poeppelmann
Infineon Technologies
Lucien J. Breems
Neubiberg, Germany
NXP Semiconductors
Frank Prämaßing
Infineon Technologies Austria AG
Dmytro Cherniak
Infineon Technologies, Villach, Austria Villach, Austria
Shidhartha Das Jan Prummel

Advanced Micro Devices Renesas Design Netherlands B.V.
Cambridge, United Kingdom ‘s-Hertogenbosch, The Netherlands
Qinwen Fan Fabio Sebastiano

Delft University of Technology Delft University of Technology
The Netherlands Delft, The Netherlands
Giorgio Ferrari Mahsa Shoaran

Politecnico di Milano, Milano, Italy EPFL, Geneva, Switzerland
Leonardo Gasparini Henrik Sjöland

Fondazione Bruno Kessler, Povo, Italy Lund University, Lund, Sweden
Giuseppe Gramegna Yvain Thonnart

imec, Leuven, Belgium CEA-List, Grenoble, France
Sohmyung Ha
Thomas Toifl
New York University
Cisco Systems, Thalwil, Switzerland
New York University Abu Dhabi
Abu Dhabi, UAE
Guy Torfs
Ghent University, Gent, Belgium
Taekwang Jang
ETH Zurich, Zurich, Switzerland
Ingrid Verbauwhede
Salvatore Levantino KU Leuven, Leuven, Belgium
Politecnico di Milano , Milano, Italy
Jan Westra
Carolina Mora-Lopez Broadcom, Bunnik, The Netherlands
Imec, Leuven, Belgium
Bernhard Wicht
Violante Moschiano University of Hannover
Intel Italia SPA, Rome, Italy Hannover, Germany
69
FAR EAST REGIONAL SUBCOMMITTEE
ITPC FAR-EAST REGIONAL CHAIR
Man-Kay Law
University of Macau, Taipa, Macau, China
ITPC FAR-EAST REGIONAL VICE CHAIR

Jaehyouk Choi
Seoul National University, Korea
ITPC FAR-EAST REGIONAL SECRETARY

Wei-Zen Chen
National Yang Ming Chiao Tung University (NYCU) , Hsin-Chu, Taiwan
ITPC FAR-EAST REGIONAL ASSOCIATE SECRETARY

Kousuke Miyaji
Ippei Akita Chih-Ming Hung

AIST, Tsukuba, Japan MediaTek, Taipei, Taiwan
Utsav Banerjee Takashi Ito

Indian Institute of Science Renesas, Tokyo, Japan
Bengaluru, India
Minkyu Je
Meng-Fan Chang KAIST, Daejeon, Korea
National Tsing Hua University
Hsinchu, Taiwan Shusuke Kawai
Ke-Horng Chen
National Yang Ming Chiao Tung University
Xugang Ke
Hsinchu, Taiwan
Zhejiang University, Zhejiang, China
Lin Cheng
University of Science and Technology Dongkyun Kim
of China SK hynix, Gyeonggi-do, Korea
Hefei, China
Dongsu Kim
Jun-Chau Chien Samsung Electronics, Gyeonggi-do, Korea
National Taiwan University
Taipei, Taiwan Hye-Ran Kim
Samsung Electronics, Gyeonggi-do, Korea
Juang-Ying Chueh
Etron Technology, Taipei, Taiwan Hyun-Sik Kim
Wei Deng
Tsinghua University, Beijing, China Ji-Hoon Kim
Ewha Womans University, Seoul, Korea
Eric Jia-Wei Fang
Mediatek, Hsinchu City, Taiwan Seong-Jin Kim
Ulsan National Institute of Science
Kazuki Fukuoka
and Technology
Ulsan, Korea
Hiroshi Hamada
NTT, Kanagawa, Japan Kyeongha Kwon
Mutsumi Hamaguchi
Sharp Corporation, Nara, Japan Jongwoo Lee
Samsung Electronics, Gyunggi-do, Korea
Kenny Hsieh
TSMC, Hsinchu, Taiwan Junghyup Lee
DGIST, Daegu, Korea
Shawn Shuo-Hung Hsu
National Tsing Hua University Seung-Jae Lee
Hsinchu, Taiwan Samsung, Gyeonggi-do, Korea
Yu-Li Hsueh Yong Ki Lee

Mediatek, Hsinchu, Taiwan Samsung Electronics, Gyeonggi-do, Korea
70
FAR EAST REGIONAL SUBCOMMITTEE
Ying-Zu Lin Takeshi Sugawara
Mediatek, Hsinchu, Taiwan The University of Electro-Communications
Tokyo, Japan
Ming Liu
Fudan University, Shanghai, China Nan Sun
Xun Liu
The Chinese University of Hong Kong, Kea-Tiong (Samuel) Tang
Shenzhen National Tsing Hua University
Shenzhen, China Hsinchu, Taiwan
Yongpan Liu Eric Wang

Tsinghua University, Beijing, China TSMC, Hsinchu, Taiwan
Yan Lu Shon-Hang Wen

University of Macau, Taipa, Macao MediaTek, Hsinchu, Taiwan
Xun Luo Hongtao Xu

University of Electronic Science and Fudan University, Shanghai, China
Technology of China
Chengdu, China Jiawei Xu
Byung-Wook Min
Yonsei University, Seoul, Korea Chia-Hsiang Yang
National Taiwan University
Noriyuki Miura Taipei, Taiwan
Osaka University, Osaka, Japan
Jun Yang
Sugako Otani Southeast University, Nanjing, China
Jun Yin
Jun-Seok Park University of Macau, Taipa, Macau, China
Samsung Electronics, Gyeonggi-do, Korea
Yun Yin
Shanthi Pavan Fudan University, Shanghai, China
IIT Madras, Chennai, India
Jerald Yoo
Jiseon Paek National University of Singapore
Pusan National University Singapore
Pusan, Korea
Heein Yoon
Rahul Rao Ulsan National Institute of Science
IBM India, Bangalore, India and Technology
Ulsan, Korea
Ben Rhew
Samsung, Gyeonggi-do, Korea Milin Zhang
Soojung Ryu
SAPEON Korea, Gyeonggi-do, Korea Yuanjin Zheng
Nanyang Technological University
Akihide Sai Singapore, Singapore
Yan Zhu
Masaki Sakakibara University of Macau Avenida
Sony Semiconductor Solutions da Universidade
Kanagawa, Japan Taipa, Macau, China
Hidehiro Shiga
KIOXIA, Yokohama, Japan
Sanshiro Shishido
Panasonic Holdings, Osaka, Japan
Ho-Jin Song
Pohang University of Science
and Technology
Gyeongbuk, Korea
71
NORTH AMERICAN REGIONAL SUBCOMMITTEE
ITPC NORTH AMERICA REGIONAL CHAIR
Keith Bowman
ITPC NORTH AMERICA REGIONAL VICE CHAIR

Jeff Walling
Virginia Tech, Blacksburg, VA
ITPC NORTH AMERICA REGIONAL SECRETARY

Danielle Griffith
Firooz Aflatouni Data Converters

University of Pennsylvania Ping Gui
Philadelphia, PA Southern Methodist University
Dallas, TX
Ankur Agrawal
IBM T. J. Watson Research Center Ali Hajimiri
Yorktown Heights, NY Caltech, Pasadena, CA
Tamer Ali Drew Hall

Mediatek, Irvine, CA University of California, San Diego
La Jolla, CA
Mark A. Anders
Intel, Hillsboro, OR Ruonan Han
Massachusetts Institute of Technology
Yves Baeyens Cambridge, MA
Nokia - Bell Labs, Murray Hill, NJ
Mona Hella
Saurav Bandyopadhyay
Rensselaer Polytechnic Institute
Troy, NY
Joseph Bardin
Benjamin Herschberg
Google & UMass Amherst, Goleta, CA
Intel, Portland, OR
Venumadhav Bhagavatula
Masum Hossain
Samsung Semiconductor, San Jose CA
Carleton University, Ottawa, Canada
Benton Calhoun
Jay Im
University of Virginia, Charlottesville, VA
AMD, San Jose, CA
Wu-Hsin Chen
Qualcomm, San Diego, CA Chiraag Juvekar
Apple, San Carlos, CA
Denis Daly
Apple, Wellesley, MA Eric Karl
Intel, Portland, OR
Zeynep Deniz
Tanay Karnik
IBM, Yorktown Heights, NY
Jeremy Dunworth
Qualcomm Technologies, San Diego, CA Mehdi Kiani
The Pennsylvania State University
Chinwuba Ezekwe University Park, PA
Robert Bosch, Sunnyvale, CA
Harish Krishnamurthy
Vito Giannini Intel, Hillsboro, OR
Uhnder, Austin, TX
Hanh-Phuc Le
Brian Ginsburg University of California, San Diego
Texas Instruments, Dallas, TX La Jolla, CA
Jane Gu Huichu Liu

University of California, Davis Meta Agile Silicon Team
Davis, CA Menlo Park, CA
72
NORTH AMERICAN REGIONAL SUBCOMMITTEE
Renzhi Liu Sophia Shao
Intel, Hillsboro, OR UC Berkeley, Berkeley
Nima Maghari Sudip Shekhar

University of Florida, Gainesville, FL University of British Columbia
Vancouver, Canada
Hugh Mair
MediaTek, Austin, TX Hajime Shibata
Mozhgan Mansuri
Intel, Hillsboro, OR Shiyu Su
University of Waterloo, Los Angeles, CA
Sanu Mathew
Intel, Hillsboro, OR Andreas Suess
OMNIVISION Technologies
Didem Turker Melek Santa Clara, CA
Cadence Design Systems
San Jose, CA Johan Vanderhaegen
Google, Mountain View, CA
Alyosha Molnar
Cornell University, Ithaca, NY Rangharajan Venkatesan
NVIDIA, Santa Clara, CA
Daniel H. Morris
Meta, Sunnyvale, CA David Wentzloff
University of Michigan, Everactive
Rikky Muller Ann Arbor, MI
University of California, Berkeley
Berkeley, CA Wanghua Wu
Samsung Semiconductor
Shahrzad Naraghi San Jose, CA
Legato Logic, San Jose, CA
John Wuu
John Pigott Advanced Micro Devices
NXP Semiconductors Fort Collins, CO
Chandler, AZ
Augusto Ximenes
Arijit Raychowdhury Meta Platforms, Redmond, WA
Georgia Institute of Technology
Atlanta, GA Rabia Tugce Yazicigil
Boston University, Boston, MA
Negar Reiskarimian
Massachusetts Institute of Technology Xin Zhang
Cambridge, MA IBM T. J. Watson Research Center
Bodhisatwa Sadhu
IBM T. J. Watson Research Center, Alireza Zolfaghari
Yorktown Heights, NY Broadcom, Irvine, CA
Swaminathan Sankaran
Visvesh Sathe
Georgia Institute of Technology
Atlanta, GA
Shreyas Sen
Purdue University, West Lafayette, IN
Kaushik Sengupta
Jae-sun Seo
Cornell Tech, New York, NY
Shahriar Shahramian
Nokia – Bell Labs
New Providence, NJ
73
CONFERENCE INFORMATION
HOW TO REGISTER FOR ISSCC
Online: This is the only way to register and will give you immediate email
confirmation of your events. Go to the ISSCC website at www.isscc.org and
select the link to the Registration website.
Payment Options: Immediate payment can be made online via credit card.
Alternative payment options are available including payment by check. Payment
must be made within 10 days to hold your registration. Registrations received
without full payment will not be processed until payment is received at
YesEvents. Please read the instructions on the Registration website.
COVID 19 PROTOCOLS
The health and safety of our conference attendees is our top priority. The ISSCC
2024 conference Organizing Committee remains vigilant in monitoring the
COVID-19 pandemic. The conference will follow CDC and State of California
guidelines. ISSCC is planned as an in-person event but it also has an online
offering. We look forward to you joining us in San Francisco, CA. If you don’t
feel comfortable participating in large gatherings, or if your organization has
travel restrictions, we encourage you to join us online.
MASKS, VACCINATION, SANITIZERS

Masks help slow the spread of the virus. They help to protect the medically
vulnerable and those unable to get vaccinated. In San Francisco there are no
longer masking requirements for most people. People may choose to wear
masks, even when they are not required. Respect the choices others make for
their health.
Currently, proof of vaccination is no longer required in meetings in San

Francisco. We will be monitoring that regulation and the ISSCC website will be
updated as regulations change.
Hand sanitizing lotion will be available throughout the hotel and at the
Registration desk.
REGISTRATION DESK HOURS:

Saturday, February 17: 4:00 pm to 7:00 pm
Sunday, February 18: 7:00 am to 8:30 pm
Monday, February 19: 6:30 am to 4:00 pm
Tuesday, February 20: 8:00 am to 4:00 pm
Wednesday, February 21: 8:00 am to 4:00 pm
Thursday, February 22: 7:00 am to 2:00 pm
Students must present their Student ID

at the Registration Desk to receive the student rates.
Those registering at the IEEE Member rate

must provide their IEEE Membership number.
Deadlines: The deadline for registering at the Early Registration rates is 12:00
Midnight EST Sunday January 14, 2024. After January 14th, and before 12:00
Midnight EST Monday January 29th, 2024, registrations will be processed at
the Late Registration rates. After January 29th, you must register at the on-
site rates. You are urged to register early to obtain the lowest rates and ensure
your participation in all aspects of ISSCC.
Cancellations/Adjustments: Prior to 12:00 Midnight EST Monday January 29,
2024, conference registration can be cancelled. Fees paid will be refunded (less
a processing fee of $75). Send an email to the registration contractor at
[email protected] to cancel or make other adjustments.
No refunds will be made after 12:00 Midnight EST January 29th, 2024. Paid
registrants who do not attend the conference will have access to the on-demand
material.
74
IEEE MEMBERSHIP SAVES ON ISSCC REGISTRATION
Take advantage of significantly reduced ISSCC fees by using your IEEE
membership number. Additional savings are available for members of the IEEE
Solid-State Circuits Society. If you’re an IEEE member and have forgotten your
member number, simply phone IEEE at 1(800) 678-4333 (US and Canada) or
+1 732 981 0060 (all other regions) and ask. IEEE membership staff will take
about two minutes to look up your number for you. If you come to register on
site without your membership card, you can phone IEEE then, too. Or you can
request a membership number look-up online at https://supportcenter.ieee.org.
If you’re not an IEEE member, consider joining before you register to save on
your fees. Join online at www.ieee.org/join any time and you’ll receive your
member number by email. When joining IEEE you can also select a Solid-State
Circuits Society (SSCS) membership, which more than pays for itself by giving
you an additional $30 off the registration fee among other benefits.
SSCS MEMBERSHIP
A VALUABLE PROFESSIONAL RESOURCE FOR YOUR CAREER
GROWTH
Stay Current! Get Connected! Invest in your Career! Membership in the Solid-
State Circuits Society offers you the chance to explore solutions within a global
community of colleagues in our field. Membership extends to you the
opportunity to grow and share your knowledge, hone your expertise, expand or
specialize your network of colleagues, advance your career, and give back to the
profession and your local community.
SSCS MEMBERSHIP DELIVERS:

- Tools for Career growth - Educational development
- Networking with peers - Recognition for your achievements
- Leadership opportunities
We invite you to join or renew today to participate in exclusive educational
events, access to leading research and best practice literature, and start your
own career legacy by mentoring students and young professionals entering our
field. It all starts with becoming a member of the Solid-State Circuits Society
where you can:
-Keep up with the latest trends and cutting-edge developments in our industry -
through our electronic newsletters, member magazine “Solid-State Circuits
Magazine”, and our award winning “Journal of Solid State Circuits”.
-Access valuable career and educational tools - saving you both time and money
with 24/7 access to our website and members-only professional development
and educational material; Distinguished Lecturer Tours, Tutorials, and webinars
by subject matter experts.
-Connect with your Peers - valuable networking opportunities through our world-
class conferences, publication offerings, social media extensions, and interactive
educational opportunities.
-Access exclusive SSCS Conference Digests for ISSCC, CICC, A-SSCC, ESSCIRC,
and Symposium on VLSI Circuits.
-Access publications and EBooks - discounted access to vast online document
libraries of journals, standards, and conference papers offer you one-third of the
world’s technical research to keep your knowledge current. Publications included
in your SSCS membership are the “RFIC Virtual Journal” (RFVJ) and the “Journal
on Exploratory Solid-State Computational Devices and Circuits” (JxCDC), Solid
State Letters, and our newest Journal, the “Open Journal of the Solid-state
Circuits Society” (OJ-SSCS) a fully open-access publication.
75
SSCS MEMBERSHIP SAVES EVEN MORE ON ISSCC
REGISTRATION
This year, SSCS members will again receive an exclusive benefit of a $30
discount on the registration fee for ISSCC in addition to the IEEE discount. Also,
the SSCS will again reward our members with a $10 Starbucks gift card when
they attend the Conference as an SSCS member in good standing.
Join or renew your membership with IEEE’s Solid-State Circuits Society today
at sscs.ieee.org - you will not want to miss out on the opportunities and benefits
your membership will provide now and throughout your career.
ITEMS INCLUDED IN REGISTRATION

Technical Sessions & more: In person registration includes admission to all
technical and evening sessions starting Sunday evening and continuing
throughout Monday, Tuesday and Wednesday. Access to author interviews,
social hours, to the Student Research Preview, to the Demo Sessions, to the
open Women in Circuits Programs and to the new Exhibition are also included.
ISSCC does not offer partial conference registrations.
Technical Book Display: Several technical publishers will have collections of
professional books and textbooks for sale during the Conference. The Book
Display will be open on Monday from Noon to 7:00 pm; on Tuesday from 10:00
am to 7:00 pm; and on Wednesday from 10:00 am to 3:00 pm.
Exhibition: For the first time in 2024, ISSCC is planning to organize an Exhibition
open to Companies and non-academic Research Institutions. The main aim of
the Exhibition is to showcase the participating Corporations/Institutions, their
products and their applications. The Exhibition will be open on Monday from
3:00 pm to 8:00 pm; on Tuesday from 9:30 am to 1:30 pm; and on Tuesday from
3:00 pm to 8:00 pm.
Demonstration Sessions: Hardware demonstrations will support selected papers
on Monday and Tuesday evenings.
Author Interviews: Author Interviews will be held Monday, Tuesday and
Wednesday evenings. Authors from each day’s papers will be available to discuss
their work.
Monday and Tuesday Social Hours: Refreshments will be available starting at
5:30 pm.
University Events: Several universities are planning social events during the
Conference. Check the University Events display at the conference for the list of
universities, locations and times of these events.
Publications: All ISSCC registrants will be able to access online the Digital Digest
and the registrations of the Technical Presentations Besides, Conference
registration includes:
-Papers Visuals: The visuals from all papers presented will be available by
download.
-Demonstration Session Guidebook: A descriptive guide to the Demonstration
Session will be available by download.
-Note: Instructions will be provided for access to all downloads. Downloads will
be available both during the Conference and for a limited time afterwards.
OPTIONAL EVENTS
Educational Events: Many educational events are available at ISSCC for an
additional fee. There are ten 90-minute Tutorials and two all-day Forums on
Sunday. There are four additional all-day Forums on Thursday as well as an all-
day Short Course. All events include a course handout in color. The Forums and
Short Course include breakfast, lunch and break refreshments. The Tutorials
include break refreshments. See the schedule for details of the topics and times.
76
OPTIONAL PUBLICATIONS
ISSCC 2024 Publications: The following ISSCC 2024 digital publications can be
purchased in advance or on site:
2024 ISSCC Download USB: All of the downloads included in conference
registration, (regular papers and presentations) (mailed in March)
2024 Tutorials USB: All of the 90 minute Tutorials (mailed in June).
2024 Short Course USB: (mailed in June).
The Short Course and Tutorial USBs contain audio and written English transcripts
synchronized with the presentation visuals. In addition, the USBs contain a pdf
file of the presentations and pdf files of key reference material.
Earlier ISSCC Publications: Selected publications from earlier conferences can
be purchased. There are several ways to purchase this material:
-Items listed on the registration website can be purchased with registration
and picked up at the conference.
-Visit the ISSCC Publications Desk. This desk is located in the registration area
and has the same hours as conference registration. With payment by cash, check
or credit card, you can purchase materials at this desk. See the posted list at the
Conference for titles and prices.
-Visit the ISSCC website at www.isscc.org and click on the link “SHOP/Shop
ISSCC/Shop Now” where you can order online or download an order form to
mail, email or fax. For a small shipping fee, this material will be sent to you
immediately and you will not have to wait until you attend the Conference to get
it.
HOW TO MAKE HOTEL RESERVATIONS

Online: ISSCC participants are urged to make their hotel reservations at the San
Francisco Marriott Marquis online. Go to the conference website and click on
the Hotel Reservation link. Conference room rates are $279 for a single/double
(per night plus tax). In addition, ISSCC attendees booked in the ISSCC group
receive in-room Internet access for free. All online reservations require the use
of a credit card. Online reservations are confirmed immediately. You should print
the page containing your confirmation number and reservation details and bring
it with you when you travel to ISSCC. Telephone: Call 877- 622-3056 (US) or
415-896-1600 and ask for “Reservations.” When making your reservation,
identify the group as ISSCC 2024 to get the group rate.
Hotel Deadline: Reservations must be received at the San Francisco Marriott
Marquis no later than 5 pm Pacific Time January 29th, 2024 to obtain the special
ISSCC rates. A limited number of rooms are available at these rates. Once this
limit is reached or after January 29th, the group rates may no longer be
available and reservations will be filled at the best available rate. Changes:
Before the hotel deadline, your reservation can be changed by calling the
telephone numbers above. After the hotel deadline, call the Marriott Marquis at
415-896-1600 (ask for “Reservations”). Have your hotel confirmation number
ready.
IEEE NON-DISCRIMINATION POLICY

IEEE is committed to the principle that all persons shall have equal access to
programs, facilities, services, and employment without regard to personal
characteristics not related to ability, performance, or qualifications as determined
by IEEE policy and/or applicable laws.
EVENT PHOTOGRAPHY
Attendance at, or participation in, this conference constitutes consent to the use
and distribution by IEEE of the attendee’s image or voice for informational,
publicity, promotional and/or reporting purposes in print or electronic
communications media. Video or audio recording by participants or other
attendees during any portion of the conference is not allowed without special
prior written permission of IEEE.
77
TAKING PICTURES,
VIDEOS OR AUDIO RECORDINGS
DURING ANY OF THE SESSIONS
IS NOT PERMITTED
REFERENCE INFORMATION
Conference Website: www.isscc.org
ISSCC Email: [email protected]
Registration questions: [email protected]

Hotel Information: San Francisco Marriott Marquis Phone: 415-896-1600
780 Mission Street
San Francisco, CA 94103
Press Information: Laura C. Fujino Phone: 416-418-3034
University of Toronto
Email: [email protected]
Registration: YesEvents Phone: 800-937-8728
PO Box 3024 Fax: 410-559-2236
Westminster, MD 21158
Email: [email protected]
Hotel Transportation
Visit the ISSCC website “Registration/Transportation from Airport” page for
helpful travel information and links. You can get a map and driving directions
from the hotel website at:
www.marriott.com/hotels/travel/sfodt-san-francisco-marriott-marquis/
Next ISSCC Dates and Location:

ISSCC 2025 will be held on February 16-20, 2025
at the San Francisco Marriott Marquis Hotel.
SUBCOMMITTEE CHAIRS
Analog: Maurits Ortmanns
Data Converters: Jan Westra
Digital Architectures & Systems: Rahul Rao
Digital Circuits: Keith Bowman
Imagers, MEMS, Medical & Displays: Rikky Muller
Memory: Meng-Fan Chang
Power Management: Bernhard Wicht
RF: Brian Ginsburg
Security: Ingrid Verbauwhede
Technology Directions: Ali Hajimiri
Wireless: Chih-Ming Hung
Wireline: Thomas Toifl
Program-Committee Chair: Frank O’Mahony

Program-Committee Vice-Chair: Thomas Burd
Conference Chair: Eugenio Cantatore
78
CONFERENCE SPACE LAYOUT
B2 LEVEL
GOLDEN GATE HALL
LOWER B2 LEVEL
YERBA BUENA BALLROOM
SALON 10
SALON 9
SALON 8
SALON 7
SALON 6
79
445 Hoes Lane
P.O. Box 1331
Piscataway, NJ 08855-1331
USA
ISSCC.org
sscs.ieee.org
ISSCC 2024 ADVANCE PROGRAM

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DRAFT 11-22-2023 IEEE SOLID-STATE CIRCUITS SOCIETY

18, 19, 20, 21, 22

MARRIOTT MARQUIS HOTEL

ICS FOR A BETTER WORLD

CONFERENCE TECHNICAL HIGHLIGHTS

On Thursday, February 22nd, ISSCC offers a choice of ﬁve all-day events:

Need Additional Information? Go to: www.isscc.org

Demonstration Session 1.......................................................................................................21

Conference Timetable ......................................................................................................40-41

The event consists of four 60-minute talks on fundamentals of Circuit Design,

Dynamic ampliﬁers have received increasing interest in state-of-the-art systems

Linear voltage regulators, including low-dropout (LDO) regulators, are a popular

Arijit Raychowdhury is the Steve W. Chaddick School Chair in the School of

Kenny Hsieh is deputy director in TSMC’s Design-Technology-Platform

Power management systems are partitioned across ﬁne-grained power domains

Frank Praemassing received the Dipl.-Ing. degree in electrical engineering from

This tutorial provides a comprehensive overview of continuous-time analog-to-

Shanthi Pavan is the Alexander Chair Professor of Electrical Engineering at the

Meeting the increasing demand for non-volatile memory in a range of critical

Violante Moschiano is a Senior Director and Senior Principal Design Engineer

Domain-speciﬁc accelerators have become a key component in today’s systems-

Sophia Shao is an Assistant Professor of EECS at UC Berkeley. Previously, she

Co-Organizers: Yvain Thonnart, CEA-List, Grenoble, France

Champions: Fatih Hamzaoglu, Intel, Hillsboro, OR

Maturation of 2.xD/3D technologies has triggered a revolution in computing

Co-Organizers: Jae-sun Seo, Cornell Tech, New York, NY

EE1: Student Research Preview (SRP)

SRP ORGANIZING COMMITTEE

Associate Chair: Frank O’Mahoney, Intel, Hillsboro, OR

FORMAL OPENING OF THE CONFERENCE 8:30 AM

1.1 Semiconductor Industry: Present & Future 8:45 AM

1.2 Racing Down the Slopes of Moore’s Law 9:20 AM

ISSCC, SSCS, IEEE AWARD PRESENTATIONS 9:55 AM

1.4 Fueling Semiconductor Innovation 11:15 AM

PRESENTATION TO PLENARY SPEAKERS 11:50 AM

Organizers: Preet Garcha, TI, Dallas, TX

Co-Organizers: Sally Amin, Intel, Hillsboro, OR

Advisors: Anantha Chandrakasan, MIT, Cambridge, MA

Panelists: Xiaolin Lu, TI, Dallas, TX

Co-Organizers: Dilara Caygara, BU, Boston, MA

Advisors: Anantha Chandrakasan, MIT, Cambridge, MA

Moderators: Ulkuhan Guler, WPI, Worcester, MA

Panelists: Xiaolin Lu, TI, Dallas, TX

Co-Organizers: Arijit Raychowdhury, Georgia Institute of Technology,

Moderator: Bryan Black, Chipletz, Spicewood, TX

One of the advantages of chiplets is the ability to integrate chiplets developed

Panelists: Lalitha Immaneni, Intel, Tempe, AZ

2AMD, Fort Collins, CO

3AMD, Markham, Canada

4AMD, Santa Clara, CA

Moderator: Jan Rabaey, University of California, Berkeley, CA

Panelists: Thomas Andersen, Synopsys, Mountain View, CA

EE5: The Legacy of Gordon Moore

Moderator: Thomas Lee, Stanford University, Stanford, CA

Moore’s Law has propelled the semiconductor industry for decades,

Panelists: Chenming Hu, University of California, Berkeley, CA

8:25 AM Introduction by Chair, Daniel Friedman

8:30 AM Introduction to Machine Learning Applications and

10:30 AM Architecture and Design Approaches to ML Hardware Acceleration: