Synchronous Design Style

Latches
D
Latches
D
Q
Q In synchronous digital circuits, inputs to
D Q D
D
Q
Q
Combinational
D
Q
combinational logic blocks come from
Logic

Ck Ck
latches/flipflops and the outputs are fed to
Delay1 Delay2
latches/flipflops.
Jitter1 Jitter2
Global Clock (ideal) These latches/flipflops are clocked by a
common clock.
This architecture is convenient because it isolates different
functional blocks from each other and one can design, test and
verify these blocks independently.
It requires a global clock which should be available over the whole
VLSI chip.
Typically, a common oscillator is used and a clock distribution
network carries the clock signal to all latches/flipflops.

November 1, 2022 1/8

A timing model for Synchronous Circuits

Latches
D
Latches
D
Q
Q Ideally, all latches should receive the
D Q D
D
Q
Q
Combinational
D
Q
active clock edge at the same time.
Logic

Ck In practice, due to clock distribution

Ck

Delay 1 Delay networks which need to cover the whole

2
Jitter Jitter
chip, these edges arrive at different times
1 2

Global Clock (ideal)

at different latches.
Delays in clock distribution network depend on the distance at which
the latch is located.
The delay can be time dependent due to fluctuations in local supply
voltage or due to noise etc.
These delays lead to:
Clock Skew: different delays to latches at different locations and
Clock Jitter: different delays to the same point but at different times.

November 1, 2022 2/8

Skew in Clock Edge arrival times

Since the clock must be routed to all parts of the chip, long wires
must be used to convey the clock to points which are remote from
the point of generation of the clock.
To prevent degradation of the rise and fall times of the clock
signal, buffers need to be inserted in the clock path.
Due to routing delays, the clock edge does not arrive at exactly
the same time at all flip flops.
This difference in arrival times can be due to:
differences in lenghts of connecting paths or
mismatch between delays of buffers used in the clock network.
We define: Skew ≡ |di − dj |max over all i, j.
Here di and dj are delays to nodes i and j for arrival of the same
clock edge. Indices i and j cover all latches in the design.

November 1, 2022 3/8

Jitter in Clock Edge arrival times

Delays in the clock distribution network will not be constant in time.

This is because:
There are local fluctuations in power supply voltage due to
different amount of currents being drawn by funtional modules at
different times. This fluctuation in power supply voltage leads to
fluctuation in delays of buffers in the clock path.
Noise and thermal fluctuations can also introduce time dependent
delays in the clock network.
Time dependent delays in the network result in clock jitter, which is a
measure of change in the clock period from one clock cycle to the next.

November 1, 2022 4/8

Jitter in Clock Edge arrival times

To define jitter, consider the period of the clock signal at a particular

node in successive clock cycles i and i + 1.
Ti Ti+1
Jitter is defined as the maximum change
Voltage at clock node

observed in the time period between

successive clock cycles at a given node.
0
Time Jitter ≡ |Ti − Ti+1 |max over a long time.
This is the value of Jitter at a particular node.
Tnom Jitter
For worst case design, we often take the
Ti

maximum Jitter value over all nodes of the

Clock cycle i circuit.

November 1, 2022 5/8

Timing Constraints in Synchronous Circuits

Consider a synchronous circuit stage. We are concerned about two

extreme cases –
Latches Latches
Q
D D
Q
D Q D
D Q
Combinational
D
Q
When the clock arrives late at the input
Q Logic

Ck Ck
latches and early at the output latches.
Delay1 Delay2
When the clock arrives early at the input
Jitter1 Jitter2
Global Clock (ideal) latches and late at the output latches.
Let us set the zero of time when the i’th edge of the clock is generated
at the clock source.
Let Delay1 , Jitter1 , Delay2 and Jitter2 be the delay and jitter values at
the input and output latches respectively.

November 1, 2022 6/8

Late input clock, Early output clock

Take the case when the input clock is late and the output clock is early.

D
Latches
D
Q D
Latches
D
Q
Q
If J is the worst case peak value of jitter,
Q
D
Q
Q
Combinational
Logic
D
the latest arrival time of the Clock edge at the
Ck Ck input latches will be Delay1 + J.
Delay1 Delay2
while the earliest arrival time of next clock at
Jitter1 Jitter2
Global Clock (ideal) the output latches will be T + Delay2 − J.

Data is applied to combinational logic at:

Clock arrival time + CktoQ delay = Delay1 + J + tCktoQ .
Data is ready at the output of combinational logic block by
Delay1 + J + tCktoQ + tLmax .
Data should be ready at least a set up time before arrival of the
next clock at the output latches. So,
Delay1 + J + tCktoQ + tLmax < T + Delay2 − J − tsu .

November 1, 2022 7/8

Timing Constraints: Minimum clock period

When the input clock is late and the output clock is early, we must have

Delay1 + J + tCktoQ + tLmax < T + Delay2 − J − tsu

So T > Delay1 − Delay2 + 2J + tCktoQ + tLmax + tsu

However, the worst case value of Delay1 − Delay2 is the clock Skew.

So T > Skew + 2J + tCktoQ + tLmax + tsu

This provides the constraint for minimum value of the clock period.
Thus, clock skew and jitter influence the shortest clock period and
hence, the performance of the whole circuit.

November 1, 2022 8/8