Zynq® UltraScale+™ MPSoCs

EG EV
CG Devices Devices
Devices
Dual-core Arm® Cortex®-A53 Quad-core Arm Cortex-A53 Quad-core Arm Cortex-A53
Application Processor MPCore™ up to 1.3GHz MPCore up to 1.5GHz MPCore up to 1.5GHz

Dual-core Arm Cortex-R5F Dual-core ARM Cortex-R5 Dual-core ARM Cortex-R5

Real-Time Processor MPCore up to 533MHz MPCore up to 600MHz MPCore up to 600MHz

Graphics Processor Mali™-400 MP2 Mali™-400 MP2

Video Codec H.264 / H.265

Programmable Logic 81K–600K System Logic Cells 81K–1143K System Logic Cells 192K–504K System Logic Cells

• Sensor Processing & Fusion • Flight Navigation • Situational Awareness

• Motor Control • Missile & Munitions • Surveillance/Reconnaissance
• Low-cost Ultrasound • Military Construction • Smart Vision
• Traffic Engineering • Secure Solutions • Image Manipulation
Applications • Networking • Graphic Overlay
• Cloud Computing Security • Human Machine Interface
• Data Center • Automotive ADAS
• Machine Vision • Video Processing
• Medical Endoscopy • Interactive Display XMP104 (v2.6)

Page 2
 Zynq® UltraScale+™ MPSoCs: CG Devices
Device Name(1) ZU1CG ZU2CG ZU3CG ZU3TCG ZU4CG ZU5CG ZU6CG ZU7CG ZU9CG
Application Processor Core Dual-core Arm® Cortex®-A53 MPCore™ up to 1.3GHz
Processor Unit Memory w/ECC L1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KB
Processing System (PS)

Real-Time Processor Core Dual-core Arm Cortex-R5F MPCore up to 533MHz

Processor Unit Memory w/ECC L1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per core
External Dynamic Memory Interface x16: DDR4 w/o ECC; x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 w/ ECC
Memory Static Memory Interfaces NAND, 2x Quad-SPI
High-Speed Connectivity PCIe® Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet
Connectivity
General Connectivity 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
Power Management Full / Low / PL / Battery Power Domains
Integrated Block
Security RSA, AES, and SHA
Functionality
AMS - System Monitor 10-bit, 1MSPS – Temperature and Voltage Monitor
PS to PL Interface 12 x 32/64/128b AXI Ports
System Logic Cells (K) 81 103 154 157 192 256 469 504 600
Programmable
CLB Flip-Flops (K) 74 94 141 144 176 234 429 461 548
Functionality
CLB LUTs (K) 37 47 71 72 88 117 215 230 274
Distributed RAM (Mb) 1.0 1.2 1.8 2.1 2.6 3.5 6.9 6.2 8.8
Memory Total Block RAM (Mb) 3.8 5.3 7.6 5.1 4.5 5.1 25.1 11.0 32.1
Programmable Logic (PL)

UltraRAM (Mb) - - - 14.0 13.5 18.0 - 27.0 -

Clocking Clock Management Tiles (CMTs) 3 3 3 1 4 4 4 8 4
DSP Slices 216 240 360 576 728 1,248 1,973 1,728 2,520
1x Gen3x16 &
PCI Express® - - - 1x Gen3x8 2x Gen3x8(2) 2x Gen3x8(2) - -
1x Gen3x8
Integrated IP
150G Interlaken - - - - - - - - -
100G Ethernet MAC/PCS w/RS-FEC - - - - - - - - -
AMS - System Monitor 2 2 2 2 2 2 2 2 2
GTH Transceivers(3) - - - 8 16 16 24 24 24
Transceivers
GTY Transceivers - - - - - - - - -
Extended(4) -1 -2 -2L -1 -2 -2L -3
Speed Grades
Industrial -1 -1L -2
Notes:
1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. XMP104 (v2.6)
2. ZU4 and ZU5 also support 1x Gen3x16 based on available GTH.
3.GTH data rates are package dependent:
a) Maximum 12.5Gb/s in SFVC784 and SFVD784
b) Maximum 16.3Gb/s in all other packages
4.-2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview.
 Zynq® UltraScale+™ MPSoCs: EG Devices
Device Name(1) ZU1EG ZU2EG ZU3EG ZU3TEG ZU4EG ZU5EG ZU6EG ZU7EG ZU9EG ZU11EG ZU15EG ZU17EG ZU19EG
Application Processor Core Quad-core Arm® Cortex®-A53 MPCore™ up to 1.5GHz
Processor Unit Memory w/ECC L1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KB
Real-Time Processor Core Dual-core Arm Cortex-R5F MPCore™ up to 600MHz
Processing System (PS)

Processor Unit Memory w/ECC L1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per core
Graphic & Video Graphics Processing Unit Mali™-400 MP2 up to 667MHz
Acceleration Memory L2 Cache 64KB
Dynamic Memory Interface x16: DDR4 w/o ECC; x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 w/ ECC
External Memory
Static Memory Interfaces NAND, 2x Quad-SPI
High-Speed Connectivity PCIe® Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet
Connectivity
General Connectivity 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
Power Management Full / Low / PL / Battery Power Domains
Integrated Block
Security RSA, AES, and SHA
Functionality
AMS - System Monitor 10-bit, 1MSPS – Temperature and Voltage Monitor
PS to PL Interface 12 x 32/64/128b AXI Ports
System Logic Cells (K) 81 103 154 157 192 256 469 504 600 653 747 926 1,143
Programmable
CLB Flip-Flops (K) 74 94 141 144 176 234 429 461 548 597 682 847 1,045
Functionality
CLB LUTs (K) 37 47 71 72 88 117 215 230 274 299 341 423 523
Max. Distributed RAM (Mb) 1.0 1.2 1.8 2.1 2.6 3.5 6.9 6.2 8.8 9.1 11.3 8.0 9.8
Programmable Logic (PL)

Memory Total Block RAM (Mb) 3.8 5.3 7.6 5.1 4.5 5.1 25.1 11.0 32.1 21.1 26.2 28.0 34.6
UltraRAM (Mb) - - - 14.0 13.5 18.0 - 27.0 - 22.5 31.5 28.7 36.0
Clocking Clock Management Tiles (CMTs) 3 3 3 1 4 4 4 8 4 8 4 11 11
DSP Slices 216 240 360 576 728 1,248 1,973 1,728 2,520 2,928 3,528 1,590 1,968
1x Gen3x16 & 2x Gen3x16 & 3x Gen3x16 & 3x Gen3x16 &
PCI Express® - - - 1x Gen3x8 2x Gen3x8(2) 2x Gen3x8(2) - - -
1x Gen3x8(3) 2x Gen3x8(3) 1x Gen3x8(3) 2x Gen3x8(3)
Integrated IP 150G Interlaken - - - - - - - - - 1 - 2 4
100G Ethernet MAC/PCS w/RS-FEC - - - - - - - - - 2 - 2 4
AMS - System Monitor 1 1 1 2 1 1 1 1 1 1 1 1 1
GTH 16.3Gb/s Transceivers - - - 8 16 16 24 24 24 32 24 44 44
Transceivers
GTY 32.75Gb/s Transceivers - - - - - - - - - 16 - 28 28
Extended(4) -1 -2 -2L -1 -2 -2L -3 -1 -2 -2L -3
Speed Grades
Industrial -1 -1L -2
Notes:
1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview.
2. ZU4 and ZU5 also support 1x Gen3x16 based on available GTH.
3. PCIe block configuration dependent on available transceivers.
XMP104 (v2.6)
4. -2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview.
 Zynq® UltraScale+™ MPSoCs: EV Devices
Device Name(1) ZU4EV ZU5EV ZU7EV
Processor Core Quad-core Arm® Cortex®-A53 MPCore™ up to 1.5GHz
Application Processor Unit
Memory w/ECC L1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KB
Processor Core Dual-core Arm Cortex-R5F MPCore™ up to 600MHz
Real-Time Processor Unit
Processing System (PS)

Memory w/ECC L1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per core
Graphic & Video Graphics Processing Unit Mali™-400 MP2 up to 667MHz
Acceleration Memory L2 Cache 64KB
Dynamic Memory Interface x16: DDR4 w/o ECC; x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 w/ ECC
External Memory
Static Memory Interfaces NAND, 2x Quad-SPI
High-Speed Connectivity PCIe® Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet
Connectivity
General Connectivity 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
Power Management Full / Low / PL / Battery Power Domains
Integrated Block
Security RSA, AES, and SHA
Functionality
AMS - System Monitor 10-bit, 1MSPS – Temperature and Voltage Monitor
PS to PL Interface 12 x 32/64/128b AXI Ports
System Logic Cells (K) 192 256 504
Programmable
CLB Flip-Flops (K) 176 234 461
Functionality
CLB LUTs (K) 88 117 230
Max. Distributed RAM (Mb) 2.6 3.5 6.2
Memory Total Block RAM (Mb) 4.5 5.1 11.0
Programmable Logic (PL)

UltraRAM (Mb) 13.5 18.0 27.0

Clocking Clock Management Tiles (CMTs) 4 4 8
DSP Slices 728 1,248 1,728
Video Codec Unit (VCU) 1 1 1
1x Gen3x16 &
PCI Express® Gen 3x16 2x Gen3x8(2) 2x Gen3x8(2) (3)
Integrated IP 1x Gen3x8
150G Interlaken - - -
100G Ethernet MAC/PCS w/RS-FEC - - -
AMS - System Monitor 1 1 1
GTH 16.3Gb/s Transceivers 16 16 24
Transceivers
GTY 32.75Gb/s Transceivers - - -
Extended(4) -1 -2 -2L -3
Speed Grades
Industrial -1 -1L -2

Notes:
1. For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview. 3.PCIe block configuration dependent on available transceivers. XMP104 (v2.6)
2.ZU4 and ZU5 also support 1x Gen3x16 based on available GTH. 4.-2LE (Tj = 0°C to 110°C). For more details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview.
Zynq® UltraScale+™ MPSoCs
PS I/Os(1), 3.3V High-Density (HD) I/O, 1.8V High-Performance (HP) I/Os
PS-GTR 6Gb/s, GTH 16.3Gb/s, GTY 32.75Gb/s
Pkg Dimensions Ball Pitch
Footprint(2,3) (mm) (mm)
ZU1 ZU2 ZU3 ZU3T ZU4 ZU5 ZU6 ZU7 ZU9 ZU11 ZU15 ZU17 ZU19
170, 24, 58 170, 24, 58 170, 24, 58
A484 19x19 0.8 4, 0, 0 4, 0, 0 4, 0, 0

170, 24, 58
A494 9.5x15 0.5 4, 0, 0

170, 24, 58 170, 24, 58

A530 9.5x16 0.5 4, 0, 0 4, 0, 0

170, 24, 156 170, 24, 156 170, 24, 156

A625 21x21 0.8 4, 0, 0 4, 0, 0 4, 0, 0

214, 24, 156, 214, 96, 156 214, 96, 156 214, 72, 52 214, 96, 156 214, 96, 156
C784(4) 23x23 0.8 4, 0, 0 4, 0, 0 4, 0, 0 4, 4, 0 4, 4, 0 4, 4, 0

214, 72, 52
D784(4) 23x23 0.8 4, 8, 0

214, 48, 156 214, 48, 156 214, 48, 156

B900 31x31 1.0 4, 16, 0 4, 16, 0 4, 16, 0

214, 48, 156 214, 48, 156 214, 48, 156

C900 31x31 1.0 4, 16, 0 4, 16, 0 4, 16, 0

214, 120, 208 214, 120, 208 214, 120, 208 Notes:
B1156 35x35 1.0 1. PS I/O is a combination of
4, 24, 0 4, 24, 0 4, 24, 0
PS MIO and PS DDRIO.
2. Packages with the same last
214, 48, 312 214, 48, 312
C1156 35x35 1.0 letter and number sequence,
4, 20, 0 4, 20, 0 e.g., A484, are footprint
compatible with all other
214, 72, 416 214, 72, 572 214, 72, 572 UltraScale devices with the
B1517 40x40 1.0 4, 16, 0 4, 16, 0 4, 16, 0 same sequence.
3. For full part number details,
see the Ordering Information
214, 48, 416 214, 48, 416 section in DS891, Zynq
F1517 40x40 1.0 4, 24, 0 4, 32, 0 UltraScale+ MPSoC
Overview..
4. GTH transceivers in the
214, 96, 416 214, 96, 416 214, 96, 416
C1760 42.5x42.5 1.0 4, 32, 16 4, 32, 16 4, 32, 16
C784 and D784 packages
support data rates up to
12.5Gb/s.
214, 48, 260 214, 48, 260
D1760 42.5x42.5 1.0 4, 44, 28 4, 44, 28 XMP104 (v2.6)

214, 96, 572 214, 96, 572

E1924 Page 6
45x45 1.0 4, 44, 0 4, 44, 0
Zynq® UltraScale+™ MPSoC Device Migration Table

The Zynq UltraScale+ family provides footprint compatibility to enable users to migrate designs from one device to another.
Any two packages with the same footprint identifier code (last letter and number sequence) are footprint compatible.

Zynq® UltraScale+™
CG Devices EG Devices EV Devices
Pkg mm
ZU1CG ZU2CG ZU3CG ZU3TCG ZU4CG ZU5CG ZU6CG ZU7CG ZU9CG ZU1EG ZU2EG ZU3EG ZU3TEG ZU4EG ZU5EG ZU6EG ZU7EG ZU9EG ZU11EG ZU15EG ZU17EG ZU19EG ZU4EV ZU5EV ZU7EV

A484 19      
A494 9.5x15  
A530 9.5x16    
A625 21      
C784 23              
D784 23  
B900 31         
C900 31     
B1156 35     
C1156 35    
B1517 40   
F1517 40    
C1760 42.5   
D1760 42.5  
E1924 45  

XMP104 (v2.6)

Page 7
 Zynq® UltraScale+™ MPSoC Ordering Information

Device Name Device Attributes Footprint

XC ZU # E G -1 F F V A # E
Commercial Zynq Value Processor Engine Type Speed Grade F: Flip-chip F: Lid V: RoHS 6/6 Package Package Temperature
Grade UltraScale + Index* System G: General Purpose -1: Slowest w/ 1.0mm Ball Pitch B: Lidless Designator Pin Count Grade
Identifier V: Video -L1: Low Power S: Flip-chip (E, I)
C: Dual APU -2: Mid w/ 0.8mm Ball Pitch
Dual RPU -L2: Low Power U: InFO
E: Quad APU -3: Fastest w/ 0.5mm Ball Pitch
Dual RPU
Single GPU E = Extended (Tj = 0°C to +100°C)
I = Industrial (Tj = –40°C to +100°C)
Note: -L2E (Tj = 0°C to +110°C). Refer to DS891, Zynq UltraScale+ MPSoC Overview for additional information.

*T in ZU3T value index denotes increase in resources and transceivers vs. ZU3.

XMP104 (v2.6)

Page 8 Important: Verify all data in this document with the device data sheets.
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