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Final Exam Solution - test paper

computer organisation (The University of the South Pacific)

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CS211: Computer Organisation

Faculty of Science, Technology and Environment
School of Computing, Information and Mathematical Sciences

Final Examination
Semester 1 2017

F2F & Blended Mode

Duration of Exam: 3 hours + 10 minutes

Reading Time: 10 minutes

Writing Time: 3 hours

Total Marks: 100

Instructions:

There are three sections in this paper

Answer all questions in the answer booklet provided

This exam is worth 50% of your overall mark

The minimum mark to pass the final exam is 20/50

The total number of pages including this cover sheet is 11

This is a closed book exam

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Section A: Multiple Choice (10 Marks)

1) The circuit used to store one bit of data is known as ________________.

A. Register
B. Encoder
C. Decoder
D. Flip Flop

2) 2FAOC is equivalent to
A. 195 084 in decimal
B. 001011111100011101100
C. Both A and B
D. None of the above

3) In Reverse Polish notation, expression A*B+C*D is written as ________________

A. AB*CD*+
B. A*BCD*+
C. AB*CD+*
D. A*B*CD+

4) A page fault
A. Occurs when there is an error in a specific page.
B. Occurs when a program accesses a page of main memory.
C. Occurs when a program accesses a page not currently in main memory.
D. Occurs when a program accesses a page belonging to another program.

5) If an instruction takes 3 cycles for execution, then how many cycles are needed for executing 4
instructions of the same type in a sequence using a 3-stage pipeline? Assume that there are no
interrupts or exceptions while executing them.
A. 12 cycles
B. 6 cycles
C. 9 cycles
D. 4 cycles

6) Which of the following architecture has the fixed instruction length feature?
A. CISC
B. RISC
C. X86
D. None of the above

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7) How do Direct Addressing Mode instructions compare with respect to the Indirect Addressing
Mode instructions?
A. Faster
B. Slower
C. No difference
D. None of the above

8) The first person who attempted to build a digital computer was _______________
A. Charles Babbage
B. Blaise Pascal
C. Baron Wilhelm
D. Alan Turing

9) Any computer must at least consist of

A. Data bus
B. Address bus
C. Control bus
D. All of the above

10) When you transfer the record from a Big Endian system to a Little Endian system over the
network in order to get the original value, you must:
A. Reverse the byte within a word
B. Reverse the bytes in an integer
C. Reverse the characters in a word
D. There is no simple solution

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Section B: Short Answer and Problem Solving (80 Marks)

1. The truth table for the Boolean expression is given below.

x y z F(x,y,z)
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
a. Write the disjunctive normal form (DNF) for the above truth table. (2 marks)
b. Simplify the DNF form in part a) using Boolean algebra. (3 marks)
c. Draw the logic diagram for the simplified expression in part b). (2 marks)
d. Draw a multiplexor for the above truth table. (3 marks)

2. For the following three questions, assume that memory locations contain the values shown in
the following table:

Location Value
-------- -----
100 150
110 130
120 110
130 100
140 120
150 140
What value will be loaded into the accumulator if the following instructions are encountered? (3
marks)
a. Load immediate 100
b. Load direct 100
c. Load indirect 100

Answer:

1 mark each

a) 100
b) 150
c) 140

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3. Consider the following infix assignment statement:

X = ((A-B)+((C-D)/E))*F

Use this statement to answer the following five questions.

a. Using two-operand instructions and no more than 4 registers (R0-R3), show the instructions
required to implement the statement. Assume that MOVE A,B moves A to B, ADD A,B adds A
to B, SUB A,B subtracts A from B, MUL A,B multiplies A times B, and DIV A,B divides A into B.
In all cases, A or B can be a register or memory address, and the result is always stored in B.
( 2 marks)
b. Assuming each instruction takes 16 bits if only registers are referenced, and 16 additional
bits for each memory reference, how many bytes long is your program? (1 mark)
c. Using 0-operand instructions on a stack-oriented machine, show the instructions required to
implement the statement. Assume that PUSH A pushes the contents of location A onto the
stack, ADD replaces A B with A + B, SUB replaces A B with A - B, MUL replaces A B with A * B,
DIV replaces A B with A / B, SWAP replaces A B with B A, and POP A takes the top item off
the stack and stores it to location A. (In the above, if A B are on the stack, consider B to be
the top of the stack and A to be the one below.) (2 marks)
d. Assuming each instruction takes 8 bits for the opcode and 16 bits for a memory address, if
any, how many bytes long is your program? (1 mark)

Answer:

a)

MOVE A,R0
SUB B,R0
MOVE C,R1
SUB D,R1
DIV E,R1
ADD R0R1
MUL F,R1
MOVE R1,X

b) 7 operands * 2 bytes per operand + 8 instructions * 2 bytes per instruction = 30 bytes.

c)

PUSH A
PUSH B
SUB
PUSH C
PUSH D
SUB
PUSH E
DIV
ADD
PUSH F

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MUL
POP X

d) 7 operands * 2 bytes per operand + 12 instructions * 1 byte per instruction =

26 bytes.
4. A register has contents in hexadecimal of ABC01234. After right arithmetic shift of 8 bits, what
are the contents of the register? Give your answer in hexadecimal. ( 2 marks)

Answer:

1010 1011 1100 0000 0001 0010 0011 0100 ½ mark

1111 1111 1010 1011 1100 0000 0001 0010 1 mark

=> FFABC012 ½ mark

5. Justify whether it is possible to design an expanding opcode to allow the following to be

encoded in a 16-bit instruction? An address is 4 bits. (5 marks)
15 instructions with three addresses
14 instructions with two addresses
31 instructions with one address
16 instructions with 0 address

Answer:
0000 R1 R2 R3
…. 1 mark
1110 R1 R2 R3

1111 0000 r2 r3

& 1 mark

1111 1101 r2 r3

1111 1110 0000 r3

&. 1 mark

1111 1111 1110 r3

1111 1111 1111 0000

&& 1 mark

1111 1111 1111 1111

Therefore, this design is possible. 1 mark

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6. What is one major problem in Clocked SR latch and explain how a clocked D latch solves the
problem? ( 3 marks)
Answer:

An error (ambiguity) occurs in the SR latch when S and R inputs are both 1 (1.5 marks)

It prevents both inputs S and R being 1 at the same time by providing one input D and its
complement (1.5 marks)

7. List three different ways to achieve processor –level parallelism when designing computers.
(3 marks)

Answer:
Array computers
Multi processors
Multi computers

8. For the page references given below, answer the questions that follow.

A, B, C, D, B, E, C, G, D, A, G, D, B, E, C

a. How many page faults will occur if optimal page replacement algorithm is used? Show all
working. [2 marks]
b. How many page faults will occur if LRU page replacement algorithm is used? Show all
working. [2 marks]
c. How many page faults will occur if FIFO page replacement algorithm is used? Show all
working. [2 marks]

Answer:

a) 8 page faults 1 mark. 1 mark for table

b) 11 page faults 1 mark. 1 mark for table

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c) 11 page faults 1 mark. 1 mark for table

9. Assume you have a superscalar CPU with in-order issue and in-order instructions that uses 8
registers (R0-R7). The usual rules include: up to two instructions can be issued in one cycle;
instructions have to complete in the order they are issued; an instruction attempting to write to
a register that is being read by any incomplete instruction cannot be issued until the incomplete
instruction completes; any instruction attempting to read a register that is being written to by
any incomplete instruction cannot be issued until the incomplete instruction retires; no new
instructions can be issued in a cycle when instructions are retiring; multiplication/division
instructions takes 3 cycles to complete while addition/subtraction instructions take only 2
cycles. Suppose you need to run the following four instructions:
1. R3 = R1 + R2
2. R1 = R4 * R5
3. R5 = R2 * R8
4. R6 = R1 + R4

a. How many cycles in total will the CPU take to complete the four instructions above. Use a
scoreboard as shown below to illustrate your answer. (4 marks)

Cycle Instruction # Decoded Issued Retired

1 1 R3 = R1 + R2 1

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b. How many cycles will the CPU take if out-of-order instruction issue and execution is allowed.
Use a scoreboard as shown above to illustrate your answer. (4 marks)

Answer:
a. 11 cycles (0.5 mark)

Cycle Instruction # Decoded Issued Retired Mark

1 1 R3 = R1 + R2 1 1
2 R1 = R4 * R5 -

2
3 1 0.5
4 2 0.5
3 R5 = R2 * R8 -
5
6
7 2 0.5
8 3 0.5
4 R6 = R1 + R4 4
9
10
11 3 0.5
4

b. 5 cycles (0.5 mark)

Cycle Instruction # Decoded Issued Retired Mark

1 1 R3 = R1 + R2 1 1
2 S1 = R4 * R5 2

2 3 S2 = R2 * R8 3 1
4 R6 = R1 + R4 4
3 1 0.5
4 2 1
4
5 3 0.5

10. Suppose you are designing a computer from scratch and that your company’s budget allows a
very small amount of memory bandwidth. Which of the following characteristics would you
choose in the ISA and the microarchitecture? Explain your answer. (6 marks)
a. Variable length or fixed length instructions?
b. Complex instructions or simple instructions?
c. A large cache or a small cache?

Answer:

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a. Variable length =>smaller code therefore less bandwidth to transfer instructions 2 marks
b. Complex instructions => smaller program because each instruction is more powerful
therefore less bandwidth to transfer instructions. 2 marks
c. Large cache => higher cache hit rate which will result in less need to access memory. 2
marks
11. Two processors with different ISA need performance evaluation. The first processor with ISA A
performs at the rate of 10 instructions per cycle where as the second processor with ISA B
performs at the rate of 2 instructions per cycle. The first processor has 500 MHz clock while the
second processor has 600 MHz clock.
a. What is the performance in MIPS of the processor implementing ISA A? (1 mark)
b. What is the performance in MIPS of the processor implementing ISA A? (1 mark)
c. Which is the higher performance processor? Explain your answer. (2 marks)

Answer:
a. 10 IPC X 500 MHz = 5000 MIPS 1 mark
b. 2 IPC X 600 MHz = 1200 MIPS 1 mark
c. Not enough information provided. We don’t know the number of instructions
executed on each processor, so we can’t compare performance. Processor A for
example may have very simple instructions . Processor B could be faster if its
instructions actually accomplish significantly more work than Processor A’s. The
MIPS metric does not take into account number of executed instructions, which also
affects the performance (i.e. execution time) of each processor. 2 marks

12. What would be the code word if you encode the data word 10011010 to allow one bit error
detection and correction using hamming code with even parity? (4 marks)

Answer:
_ _ 1 _ 0 0 1 _ 1 0 1 0 (0.5 mark)

 Position 1 checks bits 1,3,5,7,9,11: (0.75 mark)

? _ 1 _ 0 0 1 _ 1 0 1 0. Even parity so set position 1 to a 0: 0 _ 1 _ 0 0 1 _ 1 0 1 0
 Position 2 checks bits 2,3,6,7,10,11: (0.75 mark)
0 ? 1 _ 0 0 1 _ 1 0 1 0. Odd parity so set position 2 to a 1: 0 1 1 _ 0 0 1 _ 1 0 1 0
 Position 4 checks bits 4,5,6,7,12: (0.75 mark)
0 1 1 ? 0 0 1 _ 1 0 1 0. Odd parity so set position 4 to a 1: 0 1 1 1 0 0 1 _ 1 0 1 0
 Position 8 checks bits 8,9,10,11,12: (0.75 mark)
0 1 1 1 0 0 1 ? 1 0 1 0. Even parity so set position 8 to a 0: 0 1 1 1 0 0 1 0 1 0 1 0
 Code word: 011100101010. (0.5 mark)

13. The instruction execution cycle consists of six steps. The second step is <Increment the program
counter=. Explain the purpose for the second step? (2 marks)
Answer: Program counter points to the next instruction to execute. To make progress in
program execution.

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14. A segmented address space uses paged virtual memory. Each virtual address has a 2 bit segment
number, a 2 bit page number and an 8 bit offset within the page. In the following page tables, a
<-= indicates that the page is not in memory, which has 8 page frames.

segment 0 segment 1 segment 2 segment 3

page frame page frame page frame page frame

0 - 0 - 0 - 0 -
1 1 1 5 1 3 1 4
2 - 2 6 2 2 2 -
3 0 3 - 3 - 3 7

a. What is the lowest hexadecimal virtual address in segment 2 that will cause a page fault?
(2 marks)

b. Find the real memory address (in hexadecimal) if the virtual hexadecimal address is FAA.
(2 marks)

c. Find the virtual address (in decimal) if the real memory decimal address is 1000.
(2 marks)

a. 10 00 00000000 = 800
(1.5 marks) (0.5 mark)

b. C12 = 1111 10101010  Segment 3 Page 3, Frame 7 = 111 10101010 = 7AA

c. 1000= 11 11101000  Frame 3, Segment 2 Page 1= 10 01 11101000 = 1256

15. Which value does this two’s complement binary number 11110100 represents? (2 marks)

Ans: 00001011

+ 1

---------------------

00001100 =>12 (1.5 marks)

-12 (0.5 marks)

16. Suppose the hard disk above has 1024 cylinders, 8 tracks per cylinder, 32 sectors per track and
512 Bytes per sector. The maximum seek time is 450 msec, the time to move between adjacent
cylinders is 10 msec, the rotation time is 14. If the entire disk was full of data stored
consecutively, how much time would it take to read the entire disk if the read/write head is
already positioned on the first sector of the first track of the first cylinder of the disk? (3 marks)

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Answer:
Total time = cylinder read + track switch + track switch wait + cylinder switch/wait
= (8*14)*1024 + (0) + (0) + (1023*14)
= 129010 msec

17. On computer 1, all instructions take 10 nsec to execute. On computer 2, they all take 5 nsec to
execute. Can you say for certain that computer 2 is faster? Explain your answer. (3 marks)

Answer:

You cannot say anything for sure. If computer 1 has a five-stage pipeline, it can issue up to 500 million
instructions/second. If computer 2 is not pipelined, it cannot do any better than 200 million
instructions/sec. Thus without more information, you cannot say which is faster.

18. A machine instruction is needed during execution. The instruction could be in an instruction
cache (with probability 0.65) or in memory (with probability 0.3) or on disk. The access times for
cache and disk are 50 ns and 6000 ns respectively. Assume each instruction source is checked
before a slower one to find the instruction. What minimum memory access time (in ns) will give
an expected access time of 800 ns? (3 marks)

Answer:

Let memory access time = m

[50 x 0.65] + [(50 + m) x 0.3] + [(50 + 6000 + m) x 0.05] = 800
32.5 + 15 + 0.3 m + 302.5 + 0.05 m = 800
0.35 m = 450
m = 1285.71 ns

19. Why do you think John von Neumann’s original basic design of a computer, known as von
Neumann machine, is still the basis for nearly all digital computers? (2 marks)
Answer:

His machine has 5 basic parts (memory, control unti, ALU, input and output) which are still found and
are important components of a digital computer.

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Section C: Assembly Language Programming (10 Marks)

Extend the Wombat 3 accumulator based assembly language to the Wombat 4 addressing modes.
Addressing modes will be used only on STORE and LOAD machine instructions. There are three modes
that can be used: Direct, Indirect and Immediate. For example, LOAD IMM 122 will load the value 122
into the accumulator and STORE IND L2 will store the contents of the accumulator to address stored at
location L2.

Write a complete Wombat 3 assembly language main and subprogram. The main program tests the
subprogram: it reads in exactly one integer, checks that the integer is valid input, calls the subprogram
and writes out the result. The subprogram must compute the function: f(n) = 4 × n × f(n − 1)
where f(0) = 3. The program must be properly commented.

Answer:

L1: read ; read n -> acc

jmpn L1 ; jump to Done if n < 0.
push ; add sum to the acc
call Sub ; call subprogram
main: pop ; pop value returned from subprogram
write ; write the final value
stop ; stop

Sub: pop ; pop n from stack to acc

store DIR m ; store n to loc m
L2: jmpz L3 ; if n = 0, go to L3
store DIR n ; store n to loc n
mult const3; n X 4
push ; push result
load DIR n;
subt const ; n – 1
jmp L2 ; go to loc L2
L3: load IMM 3; acc = 3
push ;push 3 on to stack
load DIR m ; acc = m
L4: jmpn L5 ; if acc < 0, goto loc L5
pop ;
mult storage; acc = acc * storage
store DIR storage; storage = acc
load DIR m ; acc = m
subt const ; acc = acc – 1
store DIR m ; m = acc
jmp L4 ; jump to loc L4
L5: load DIR storage;
push ; push calculated value on stack for main
return main; return to main program
n: .data 2 0 ; storage for n
m: .data 2 0 ; storage for m

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const: .data 2 1 ; storage for constant 1

const2: .data 2 3 ; storage for constant 3
const3: .data 2 4 ; storage for constant 4

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