ECET 215 Lab Manual-V1
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CET 215, Introduction to Digital Logic
E
2020 Fall
William E. Barnes
Professor Emeritus
ECET 215 Lab Manual
TABLE OF CONTENTS
Page
Special Thanks, Introduction and Requirements of the Lab Work 3
LAB # 1, Introduction to Basic DC Circuits
4
I. Pre-Lab and Background Information 4
a. Basic Circuit Components
b. Simple Series Circuits
c. Simple Parallel Circuits
d. Measuring R, V, I with a Multi-meter
II. Procedure 11
LAB # 2, Introduction to Basic Gates
I. Pre-Lab and Background Information 1 5
II. Procedure 17
LAB # 3, Simplification of Boolean Expressions
I. Pre-Lab and Background Information 2 1
II. Procedure 22
LAB # 4, Binary Arithmetic, Exclusive-ORs, and Adders
I. Pre-Lab and Background Information 2 8
II. Procedure 29
LAB # 5, Decoders
I. Pre-Lab and Background Information 3 3
II. Procedure 34
LAB # 6, Multiplexers
3 5
I . Pre-Lab and Background Information 36
II. Procedure
LAB # 7, Introduction to Latches, Flip-Flops and Counters
I. Pre-Lab and Background Information 3 7
II. Procedure 39
LAB # 8, Birthday Display Project
I. Pre-Lab and Background Information 4 2
II. Procedure 45
ppendix A,Resistor Color Code and Examples
A 4 7
Appendix B, A Sample BreadBoard 48
Appendix C, 7-Segment Numeric LED Displays 49
Appendix D, Some Logic Gates From the 7400TTL IC Family 50
Appendix E, Teamwork Report 51
Appendix F, Scoring Rubric for Labs 1-8 52
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ECET 215 Lab Manual
pecial thanks to my student Vadim Ergardt for help in the development of the original edition of the lab
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manual; Additional special thanks to my student Melvin Peralta for help in a major revision of the
manual during the fall of 2013; Additional special thanks to my student Andriy Prochik for help in a
second major revision of the manual during the spring of 2015.
Introduction and Requirements of the Lab Work
Lab Reports and the Implementation of the Labs
ach lab group is required to maintain a laboratory report, which will be kept with the digital trainer
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used by the group. Note that this doesn’t mean individual lab reports but one report for each group of
typically 3 students. The instructor will initial labs as they are completed. The lab reports will be
graded and will comprise a major part of the lab part of the final grade.
he laboratory component of this course is as much about teamwork as it is about learning digital
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electronics, therefore carefully implement the following:
For each new lab exercise the group needs to assign people to three equally important positions:
( 1)Recorder: responsible for entering collectingthe required information for that lab into the Lab
report;
( 2)Leader: responsible for organizing the responsibilitiesof the team members, while making sure
everyone on the team is participating and helping to successfully complete the lab, and is the
spokesperson for that particular lab;
( 3)Checker: responsible for checking that the schematics/pindiagrams are correct, that the test
circuits are consistent with those schematics and proofreading the lab report for completeness and
accuracy. Checker should meet with other team members to discuss consistency of lab report.
I n the report, at the top on the first page of a new lab will be written: title of the lab, materials to be
used, date, names of the Recorder, Checker and Leader. The page number will be shown at the bottom
of every page. The positions of Leader, Checker and Recorder should be rotated through the group so
that each group member will have had experience in each position at least once during the semester.
Suggestions for successful work in the Laboratory
● D
o not expect to complete the labs by only working in the lab; for example, read the labs
ahead of time and complete each pre-lab before the actual lab time. Keep your eye on the
calendar and don’t allow yourselves to get behind- it’s very hard to catch up.
● B
e on-time, don’t be absent except for a health or other important reason. Keep in mind that
accomplishing the work is a team effort and if you are not there or not participating you are
hurting your partners as much as yourself.
● B
esides learning how to build and test circuits, one of the primary purposes of the lab is to
reinforce and clarify the lecture material.
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ECET 215 Lab Manual
Lab 1: Introduction to Basic Circuits (1 week)
* **NOTE: All the problems and questions in the Pre-Lab need to be entered into your
lab report. Do the same for the remaining labs.***
I.Pre-Lab and Background Information for Lab 1
A. Basic circuit components:
Resistance is measured in ohms (symbol: Ω).
Figure 1-1.Symbolic Representation of a Resistor
Voltage is measured in volts. Note the polarity of the voltage source.
Figure 1-2.Symbolic Representation of a DC Power Supplyor Battery
B. A Basic Series Circuit (requires a source, a load, and a closed path):
Three critical parameters: Voltage (in volts), Current (in amps), and Resistance (in ohms)
he resistor (load) and voltage (source) are connected with a conductor (closed path) on both
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ends. Electric current is able to flow along a simple path through the conductor and resistor
circuit that is without any breaks. Conventional current leaves the plus side and enters the
negative side of the source.
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ECET 215 Lab Manual
Figure 1-3.A Resistor In Series With a Voltage Source.
The total resistance ( ) of a series circuit is thesum of all the resistor values. In Figure 3
there is only one, so .
he total voltage ( ) in the circuit in Figure 3 isequal to the voltage of the power supply
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(voltage source).Resistorsin a series circuiteachhave a fraction of the total voltage across
them. All of these portions, when added, always have to equal the voltage source (Kirchhoff’s
Voltage Law, KVL).
he formula shown below (voltage division formula) provides the voltage across a specific
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component in a series circuit:
, where Rx is the resistor of interest (see textor your class notes for a series
circuit with more than one resistor).
In Figure 1-3, the total voltage is 12 volts.
he current (I) of this circuit is determined by the whole load, in this case only one device.
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Ohm’s Law provides a relationship between the circuit current, resistance, and voltage:
This equation can be manipulated to find the current:
What’s the formula for R? R= V/I
* The current of aseriescircuit isthe samethroughall resistors regardless of their position.*
Current is measured in Amperes or Amps (A).
By Ohm’s Law: or 120 mA
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C. Parallel Circuits:
efinition:A parallel circuit contains componentsthat share two common nodes. Current
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flow divides and travels along multiple branches of the circuit. Circuit components that are
parallel to each other have the same voltage. In Figure 1-4 the conventional current comes out
of the battery’s positive terminal splits with some going through R1 and some through R2
(more through R2. Why?) The current recombines at the bottom node and returns to the
negative terminal of the battery.
OTE:The voltage of components in parallel is thesame regardless of resistance. The total
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current is the sum of the individual current through the resistors, Kirchhoff’s Current Law
(KCL).
Figure 1-4.Resistors R1 and R2 Share a Common Node
1 and R2 are in a parallel configuration since they share a common node (seen inside the
R
circle). Actually there are two common nodes- circle the other one.
1 and R2 cannot be added when calculating the total resistance. Resistors in parallel each
R
have a different current flowing thorough them. However, they can be combined into a single
resistance value for the purpose of getting total current.
he general formula for total resistance of components in parallel is calculated by using the
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equation below:
1/RT = 1/R1 + 1/R2 + 1/R3 + . . . NOTE: RT IS THE SAME AS RΣ
For the circuit in Figure 1-4:
=
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ECET 215 Lab Manual
ote: for two (and only two) parallel resistors we can calculate the total resistance as a
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product over a sum; i.e., RT = (R1R2) / (R1 + R2).
hus, the combined resistance of R1 and R2 is 4.8Ω and the equivalent circuit is shown
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below:
Figure 1-5.Parallel Resistances in Figure 4 Combinedinto an Equivalent Resistance
ote: Using the shorthand formula for two, but only two, resistors in parallel is product over
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sum. Try it for the above example:
RT = = _____________
D. Measuring with a multi-meter:
urrent, resistance, and voltage can also be measured in a circuit using an analog or digital
C
multi-meter. This device can be connected to the circuit physically or in simulation using a
program like Multisim.
Figure 1-6. A Representation of a Multi-meter Simulatedin Multisim.
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ECET 215 Lab Manual
(a) Measuring Resistance:
NOTE: Appendix A shows the weights of carbon resistor bands and the color code.
he multi-meter is connectedacrossthe resistor,whichcannotbe in a circuit. Polarity can be
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ignored. In this mode the multi-meter is referred to as an ohmmeter.
I n order to view the measured value, the resistance measurement option must be selected in
the simulation or activated when dealing with the actual device.
Figure 1-7.The Correct Setup For Measuring Resistance.
Exercise 1:
1 . Suppose you wanted to check the actual values of two resistors which are physically
connected in parallel, why must you separate them to get their individual resistances? Show in
a diagram how you only need to separate one node.
2 . Even though it may seem so, resistance is not actually measured directly. How do you think
it is done and how does this relate to the fact that you cannot have the circuit connected to the
power source? Hint: the meter uses its own internal battery to measure resistance.
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ECET 215 Lab Manual
(b) Measuring voltage:
he multi-meter below is connectedacrossthe devicewhose voltage is being measured (the
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“V” button must be selected). It is important to connect the multi-meter according to the
polarity of the device. (not necessary if using a digital meter) The top long horizontal line of
the voltage source symbol is positive. The short bottom line is negative. In this mode the
multi-meter is referred to as a voltmeter (VM).
Figure 1-8.Voltage is Measured Across a Circuit Component
hevoltage dropacross the 100 Ω resistor is theentire 10 V produced by the voltage source
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because it is the only component connected to it.
Exercise 2:Given a 9 V source and three resistorsof 3kΩ each.
a. Draw aseriescircuit and show instrument(s) formeasuring all the voltages in the circuit.
What will those voltages be?
VT = ______; VR1 = ________; VR2 = ________; VR3 =________
Show that KVL is satisfied: ____________________________________________________
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ECET 215 Lab Manual
b . Draw aparallelcircuit using the same values and show instrument(s) for measuring all the
voltages.
What will those voltages be?
VT = ______; VR1 = ________; VR2 = ________; VR3 = ________
Using Ohm’s Law, find IT, and the three branch currents:
Show that KCL is satisfied: __________________________________
(c) Measuring current:
he multi-meter becomes a part of the circuit to force the current to flowthrough it. It is in
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series with the resistor. This provides a current reading when the “A” button is selected. In
this mode the multi-meter is referred to as an ammeter.
(Note:voltageexistsacrossa component(s) whilecurrentflowsthroughthe component(s))
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ECET 215 Lab Manual
Figure 1-9.Current Through a Resistor Is Measured By a Multi-Meter Connected In Series
The measured current is 100 mA or 0.1 A and agrees with the 0.1 A calculated current.
Exercise 3:Given a 9 V source and three resistorsof 3 kΩ each.
a . Draw aseriescircuit and show instrument(s) formeasuring all the currents in the circuit.
What will those currents be?
IT = ______; IR1 = ________;IR2 = ________;IR3 =________
b . Draw aparallelcircuit and show an AM for measuringthe total current, IT, in the circuit.
Using Ohm’s Law find the other currents:
IT = ______; IR1 = ________; IR2 = ________; IR3 = ________
Show that KCL is satisfied: ____________________________________
II. Procedure for Lab #1
* **NOTE: All the problems, questions and collected data in the Procedure need to be
entered into your lab report. Do the same for remaining labs. ***
quipment and Materials Needed:Power Supply, Multi-meter,Digital Trainer (only for
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breadboard use), Resistors (2- 1 kΩ, 2- 2.2kΩ), wires.
>>>>BEFOREBUILDING ANY CIRCUITS EXAMINE and DISCUSSTHE SAMPLE
BREADBOARD IN APPENDIX B >>>>
Important Notes:
A. nom is short for nominal; i.e., the named value. For example the nominal value of a
resistor may be 10 kΩ, while the actual (measured) value might be 9920 Ω
B. Before building circuits, make sure you know how connections are made on the board
(rows, columns, etc.)
C. Call instructor over to check your circuit before making any current measurements.
D. Build your circuits so that they look like the schematics as much as possible.
E. Appendix A shows the weights of carbon resistor bands and the color code.
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ECET 215 Lab Manual
1. Given:
Figure 1-10.Series Circuit With 3 Resistors.
Perform the following in the order given:
a . Calculate and fill in the current and voltages based on the nominal values
b. Measure the resistors to get their actual values
c. Recalculate the current and voltages based on the values from (c) and enter into the
table
d. Build the circuit and make measurements, filling the values in the last two columns
of the table
BEFORE BUILDING CIRCUIT Measured
nom
R Inom Vnom Rmeas Inew new Imeas Vmeas
V
R1 1k 1.2 mA 1.2 V 0.98 k 1.19 1.17 V 1 .209 1.19 V
ohm mA mA
R2 1k 1.2 V 0.99 k 1.18 V 1.197 V
ohm
R3 2.2k 2.64 2.15 k 2.56 V 2.61 V
ohm
otal
T 4.2k 4.12 k
Equiv.
e. Show that Kirchhoff’s Voltage Law (KVL) is satisfied:
+V1 - VR1 - VR2 - VR3 = 0
5.0 - 1.19 - 1.197 - 2.61 = 0.003
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ECET 215 Lab Manual
2. Given:
Figure 1-11.Parallel Circuit With 3 Resistors.
Perform the following in the order given:
1. a . Fill in the calculated and nominal values below
b. Measure the resistors to get their actual values (Hint: when calculating RT, calculate
R2//R3 first. Why?)
c. Calculate the currents and voltages based on the values from (b)
d. Build the circuit (NOTE: use the buses on the circuit board to create the two nodes)
and make measurements, filling them in the table.
EFORE BUILDING CIRCUIT
B easured Results
M
Rnom Rmeas Icalc calc
V Imeas Vmeas
1
R 1.0 k 0.984 k 5 mA 5 V 5.02 mA 5 V
R2 2.2 k 2.19 k 2.27 mA 5 V 2.27 mA 5 V
R3 2.2 k 2.15 k 2.27 mA 5 V 2.31 mA 5 V
otal
T 5.4 k 5.324 k 9.54 mA 15 V 9.6 mA 15 V
Equiv.
f. S
how that Kirchhoff’s Current Law (KCL) is satisfied:
+V1 - VR1 = 0 => 5 - 5 = 0
+VR1 - VR2 = 0 => 5 - 5 = 0
+VR2 - VR3 = 0 => 5 - 5 = 0
g. Q
uestion:Sometimes it’s difficult to get an accuratecurrent measurement, how
can you use Ohm’s Law to deduce the current in a particular resistor?
1- We measure the voltage across the resistor.
2- Determine the resistance of the resistor.
3- Apply Ohm’s law: I = V/R
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ECET 215 Lab Manual
3. Complete the following statements and copy in the lab reportcircling the words you
inserted. (Be sure that everyone in the group agreeswith and understands the answers):
a.In aseries resistive circuitthecurrentis thesame everywhere in the circuit but the
voltagecan be different across each resistor. Ina parallel resistive circuit thevoltageis the
same across each resistor, while the current may bedifferentthrough each resistor.
KCL in a parallel circuit allows us to check the currents by adding each individualcurrent
and the total will equal the totalcurrent. KVLin a series circuit allows us to check the
voltage by adding each individualvoltageand thetotal will equal the sourcevoltage.
b. We can say that aseries circuit is a voltage dividerbecause thevoltageis divided among
the resistors. Due to Ohm’s Law and thecurrentbeingthe same through each resistor, the
resistor with the highest resistance value will have thehighestvoltage drop and the
resistor with the lowest value will have thelowestvoltage drop.
c. We can say aparallel resistive circuit is a currentdividerbecause thecurrentis divided
among the resistors. Due to Ohm’s Law and thevoltage being the same across each
resistor, the resistor with the highest value will have theleastcurrent through it and the
resistor with the lowest value will have themostcurrent.
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ECET 215 Lab Manual
Lab 2: Introduction to Basic Gates (1week)
I.Pre-Lab and Background Information for Lab 2
Basic Gates:
ircuits can be designed to perform multiple operations using logic gates. A logic gate
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is a device whose output depends on the value(s) of its input(s). When combined, these gates
can be used to output solutions for multiple equations. AND, OR, and NOT gates will be used
in various configurations. However, truth tables and drawn schematics are needed before
logical operations are created in a physical circuit form.
AND Gate
Boolean operation performed by an AND gate: Y = A ● B (implemented in Figure 1).
Figure 2-1.A representation of an AND gate.
and B are inputs, Y is the output. An input could be considered “high” or “low”. A high is
A
represented by “1” and a low is represented by a “0”. Thetruth tableis a binary (1 and 0)
representation of all possible input and output combinations.
A B Y
0
0
0
0 1 0
1 0 0
1 1 1
Figure 2- 2.An AND gate truth table shows all thecombinations of the inputs and their
corresponding outputs.
OR Gate
Boolean operation performed by an OR gate: Y = A + B (implemented in Figure 2-3)
Figure 2-3.Representation of an OR gate with twoinputs and one output.
OR gate truth table on next page:
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ECET 215 Lab Manual
A B Y
0
0
0
0 1 1
1 0 1
1 1 1
Figure 2-4.The truth table describing an OR gate’sfunction.
ote: When dealing with unused inputs, be sure to tie the AND gate inputs high and the
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OR gate inputs low. What would happen if you did the opposite?
We would lose the functionality that these gates are supposed to provide
___________________________________________________________________________
CHIP Internal Connection Diagrams:
http://www.fairchildsemi.com/
Figure 2-5.74LS08 Quad 2-Input AND gates
http://www.fairchildsemi.com/
Figure 2-6.The 74LS32 has four OR gates with twoinputs and one output each.
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ECET 215 Lab Manual
Inverter (NOT Gate):
Figure 2-7.7404 chip containing 6 inverters.
II. Procedure for Lab #2
REMINDER:All of the following needs to be in yourlab report
Equipment and Materials Needed:
1 . readboard/Various wire segments
B
2. Logic Probe
3. 7400 or 74LS00 Quad 2-Input NAND gates
4. 7408 or 74LS08 Quad 2-Input AND gates
5. 7432 or 74LS32 Quad 2-Input OR gates
6. 7404 or 74LS04 Six inverters (NOT gates)
7. Built-in (Digital Trainer) LEDs
8. Built-in on/off (one/zero) switches
ote: Keep in mind that all digital chips require power (5V and ground), otherwise they
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will not work.
1. Briefly, what is the difference between power and signal?
Q
Power represents the energy flow, while a signal represents the information conveyed
by that energy.
1. Prove the truth tables for an OR gate and an AND gate using the Digital Trainer.
a. Making use of data sheets (Figures 2-5 and 2-6 above) draw pin diagrams
similar to Figure 2-8 to show how you are wiring the gates for the test. Make
use of the switches on the Digital Trainer for the inputs. Also show how the
LEDs are connected to inputs and outputs. For the AND gate use the gate in
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ECET 215 Lab Manual
the chip whose output is pin 8 and for the OR gate us the gate whose output is
pin 6.
b. B
ased on your measurements, fill in Tables 2-1 and 2-2 below and enter in the
lab report. Note you will enter 1’s and 0’s depending on whether the LED is
on or off.
Figure 2-8. An OR gate showing pin numbersdon’t useword ‘pin’ in your diagrams-
unnecessary!)
OTE: Before turning on the power, show your pin diagram and wire connections to the
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instructor:
OR AND
A B Yle A B Yle
d d
0 0
0
0
0
0
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 1
Table 2-1, OR Gate Test Table 2-2, AND Gate Test
c. Make a table and repeat the above for the inverter, using the 7404 chip.
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NOR NAND
A B Yle A B Yle
d d
0 0
1
0
0
1
0 1 0 0 1 1
1 0 0 1 0 1
1 1 0 1 1 0
2 .
a. Find the data sheet on-line or in your text book for the quadNANDgate (7400) chip and
examine the full chip layout which is similar to the AND gate chip shown in Figure 2-5. We
will not be drawing the chip layouts but will use standard schematic practice of showing the
gates with the pin numbers as in Figure 2-8 and the more interesting diagram in Figure 2-9.
b . Draw the pin out for one of the NAND gates in (a) and test it on the Digital Trainer, filling
in the following table. In the pin diagram show how the inputs and output will be connected to
LEDs on the trainer.
A
B
Y Pin Diagram(don’t use word ‘pin’ in your diagrams-unnecessary!):
0 0 1
0 1 1
1 0 1
1 1 0
c . Given F = A′ + B′, draw this logic using an OR and two inverters. You will need two chips.
Draw a pin diagram similar to Figure 2-9 (except do not write in the word ‘pin’) on next page
but add LEDs for inputs and outputs.Show this diagramto your instructor for a check.
U1: ______________________ Logic/Pin Diagram:
U2: ______________________
d. Build and test your circuit from (c) showing results in the table below.
A
B
F
0 0 0
0 1 1
1 0 1
1 1 1
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e. Briefly compare your results in (d) with the results in (b):
e can see that the truth tables are not identical. While the first three rows match, the last
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row differs. In the theoretical NAND gate truth table, the output is 0 when both inputs are
1, but in the practical test, the output is 1 when both inputs are 1. This discrepancy might
arise due to factors such as noise, component tolerances, or limitations of the testing
equipment.
f. Briefly, what conclusion can you draw from (e)?
rom the comparison in part (e), it can be concluded that while the theoretical behavior of a
F
NAND gate suggests that the output should be 0 when both inputs are 1, the practical
implementation may not always adhere to this expectation. The discrepancy between the
theoretical truth table and the observed results in the circuit test indicates that there may be
real-world factors influencing the behavior of the NAND gate, such as noise, component
tolerances, or limitations of the testing equipment. Therefore, it's important to consider
these practical factors when designing and testing digital circuits.
3. Given the logic diagram in Figure 2-9 below.
a. Write the expression for F: F =(A+R)(A'+R)
b. Complete the truth table
A
B X (pin 3 of U2) Y (pin 6 of U2)
F
0 0 0 0 0
0 1 1 1 1
1 0 1 1 1
1 1 1 1 1
c . Construct the logic on your Digital Trainer using switches for the inputs and
connect LEDs to X, Y, and F. Also, in the space provided for U1, U2 and U3 write
down the chip numbers for the circuit that you will construct.Show the instructor that
your circuit is working and agrees with the truth table above. (see d below).
1:74LS08
U
U2:74LS32
U3:74LS04
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Figure 2-9,Logic for # 3
d . Investigate the use of the Logic Probe andshowthe instructorthat you can use it to
test for 1’s and 0’s.
e . Use Boolean Algebra to reduce the expression in #3a and show that the new
expression gives you the same F output for corresponding inputs.
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ECET 215 Lab Manual
Lab 3: Simplification of Boolean Expressions
(2 Weeks)
IMPORTANT NOTES:
( a) For this lab and all the following labs, you must draw a complete pin diagram for any
logic circuits that you build using Figure 3-1 of this lab as a guide (except don’t use the
word ‘pin’).
(b) All pin diagrams must also show connected LEDs for the output(s) and switches for the
inputs.
I.Pre-Lab and Background Information for Lab #3
oolean logic operations and implementations depend on the amount of variables and
B
conditions that exist. Extra variables increase the number of all possible input combinations.
Unneeded terms in a problem can result in a more complex Boolean expression. As a result,
more logic gates and more connections are used when constructing a circuit. However,
construction becomes straightforward when a Boolean expression is simplified. Ultimately,
the circuit becomes cheaper to produce, easier to troubleshoot and more reliable.
oolean expressions define various logic functions with a given set of variables. A
B
truth table will have every possible combination of all input states and output states. Variables
in a row that correspond to a 1 at the output are AND’ed and considered to beminterms. All
minterms are combined using the OR operation to produce a single output. This format is
called a Sum of Products (SOP).
xample of an SOP:
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Y (A,B,C) = ∑m( 0, 3, 5, 6, 7) = A’B’C’ + A’BC + AB’C + ABC’ + ABC
Another way to implement logic functions is to use a Product of Sums (POS). Truth
table zero outputs are considered in this form. The variables corresponding to a zero are
negated and OR’ed into amaxterm. These combinationsare then AND’ed with each other.
xample of a POS:
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Y(A,B,C) = ΠM(0, 1, 5, 6) = (A + B + C) (A + B + C’) (A’ + B + C’) ( A’ + B’ + C)
Boolean expression can be simplified using Boolean algebra and/or a Karnaugh
A
Map (K-Map). The K-Map groups elements with common functions in a table-like form. The
data in a truth table “maps” into the K-map so that they both contain the same information.
Reference:
Kleitz, Wm.,Digital Electronics: A Practical Approach,Pearson Prentice Hall, 7th edition.
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ECET 215 Lab Manual
II. Procedure for Lab #3
Read the procedure carefully-you do not need to buildall circuits
Materials Needed:
igital Trainer
D
Logic Probe
74LS08 Quad 2-Input AND gates
74LS32 Quad 2-Input OR gates
7404 Hex inverter chip (NOT gates)
7400 Quad 2-Input NAND gates
1. Do NOT buildthe logic in Figure 3-1. You willbe simplifying the expression for Y.
1: 74LS08
U
U2: 74LS32
Figure 3-1. A circuit with three AND gates and two OR gates.
a. Based on the logic, write the Boolean expression for Y:
Y = (BC+AB)(A+C)
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b. Use M, N, R and S (as defined in the table below) to complete this table, including Y.
A
B
C M (pin 3 of U1) N (pin 6 of U1) R (pin 6 of U2) S (pin 3 of U2) Y
0 0 0 0
0
0
0
0
0 0 1 0 0 0 1 0
0 1 0 0 0 0 1 0
0 1 1 0 0 0 1 0
1 0 0 0 0 0 1 0
1 0 1 0 0 0 1 0
1 1 0 0 0 0 1 0
1 1 1 1 1 1 1 1
c . Simplify your expression for Y from (a) using Boolean Algebra, showing all steps and what
theorems you are using. You should end up with only two simple terms.
BC+AB
d . Fill in a new truth table based on your equation from (c) and check that Y agrees with your
truth table in (b).
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
e . Draw a new pin diagram based on (c) Be sure to include switches and LEDs for test
purposes. Show your instructor that it is working properly after you have built and tested the
logic.
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f. Compare the “Cost” (#gates + #inputs) for (a) and (e).
Cost of (a) = 11 Cost of (e) = 6
2 . Given the following Truth Table (DO NOT BUILD THE CIRCUIT FOR THIS PART OF
THE LAB):
A
B
C
Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
a . Using the truth table, produce a Sum of Products expression. Note that this is acanonical
equation becauseevery term contains every variableand it has not been simplified.
Y = (A’⋅B⋅C’)+(A’⋅B⋅C)+(A⋅B’⋅C)+(A⋅B⋅C)
b . Repeat part (a) using a Product of Sums expression (use the zeros!). Keep in mind that each
sum term must equal zero. This expression will also be canonical.
Y = (A+B+C′)⋅(A+B+C)⋅(A′+B+C)⋅(A′+B′+C)
c. Simplify the equation in part (a) using Boolean algebra. Show which theorems you use.
Y = (A’⋅B⋅C’)+(A’⋅B⋅C)+(A⋅B’⋅C)+(A⋅B⋅C)
’B+AC
A
Distributive Law
Complement Law:
Identity law
d. Compare the cost of your new equation in (c) with the canonical equation in (a).
Cost (a) = 10 Cost (c) = 6
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ECET 215 Lab Manual
e. Truth table from 2(a) is rewritten for you below.
A
B
C
Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
f . Use a Karnaugh map to simplify the equation and compare with the equation you developed
in 2(c). (Notice how the columns are labelled using the Grey Code!)
BC
A 00 01 11 10
0
1
Y = _______________________________
Comparison with equation in 2(c):
3. Given F(A, B, C, D) = ∑m (2, 3,5, 6, 7, 13, 15)
a. Complete the truth table:
A
B
C
D F
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
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ECET 215 Lab Manual
1 0 0
1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
b . Derive a simplified SOP using a Karnaugh map (remember to use Grey Code for rows and
columns).
F= __________________________________________
c . Draw two logic diagrams: (1) using AND, OR, NOT gates and (2) using only NANDs.
Which do you think will be easier to build? Convert that logic diagram into a complete pin
diagram including input switches and output LEDs. If you use (2)you will only need 1 chip.
(1) U1 = ________ U2 = _______ U3 = _______ (2) U1____________
4. Given:
D
C
B
A 00 01 1
1 10
00 1 1 1 1
01
11
10 1 1
a. Complete the following canonical expression: F = ∑m ( ________________________ )
b. Produce a simplified SOP expression using the K-Map.
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ECET 215 Lab Manual
F = ____________________________
uestion: Which variable turns out to be irrelevant to F? ______ and, briefly, how do you
Q
know this?
c. Show how it would be implemented with AND, OR, and NOT gates. (Do not build)
d . Now implement with only NANDs and NOTs as a pin diagram and then build and test your
circuit.
U1:___________ U2:__________
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ECET 215 Lab Manual
Lab 4: Binary Arithmetic, Exclusive-ORs, and Adders
(2 Weeks)
Pre-Lab and Background Information for Lab 4
Adding and subtracting binary numbers are key basic operations. They are
implemented to perform various arithmetic processes that also include division and
multiplication. XOR gates are used in the structure of an adder and it is important to
understand their function. There is often a “carry out” that may occur from addition that has to
be handled both as a concept and as an output within a physical circuit.
Materials Needed:
1. Digital Trainer
2. Logic Probe
3. 74LS08 Quad 2-Input AND gates
4. 74LS32 Quad 2-Input OR gates
5. 7404 Six inverters (NOT gates)
6. 7400 Quad 2-Input NAND gates
7. 7483 4 Bit Adder
8. 7486 Quad 2-Input XOR gates
Binary addition is similar to decimal number addition. Adding a ‘1’ and a ‘0’ will
p roduce a ‘1’. But, a ‘1’ added to ‘1’ will produce a ‘0’ as the least significant bit (LSB) and a
‘1’ as the most significant bit (MSB). A specific notation is used when representing a negative
value in binary. This is known as 2’s complement. A binary number is considered positive
when its MSB is zero. An MSB of one will indicate a negative quantity. To create the negative
of a number, we form its two’s complement as follows:
( 1) All the bits of a number must be inverted (1 to 0 and 0 to 1), forming the ones
complement.
(2)Then, a ‘1’ is added to the LSB
XOR gates can be used to construct a circuit that can perform the addition of two
binary numbers and also to create two’s complements of numbers.
Reference:
Kleitz, Wm.,Digital Electronics: A Practical Approach,Pearson Prentice Hall, latest edition.
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ECET 215 Lab Manual
II.Procedure for Lab #4
Number System Practice Problems (Assuming an 8-Bit System)
1. P
erform addition on thesignedbinary numbers listedbelow giving answers in binary,
hex and signed decimal.
A
B
C
0100 0110 0001 0101 00010011
0111 0101 00110100 0001 1111
Bin. ___________ ___________ ___________
Hex. ___________ ___________ ___________
Dec. ___________ ___________ ___________
Which of the problems above gives you an ‘incorrect’ answer? Explain: ______________
___________________________________________________________________________
2. N
egatethe followingsignedbinary numbers showingbinary, hex, and signed decimal
values (first one is done for you):
Binary Hex Decimal
00110011 🡪 ___1100 1101____ _______CD______ ___-51_________
00000111 🡪 ________________ ________________ _______________
01011000🡪 ________________ ________________ _______________
10001001 🡪 ________________ ________________ _______________
3 . Perform subtraction on the signed binary numbers listed below utilizing the 2’s
complement number system and show a check using decimal numbers:
(a) 01010011 – (01100000) (b)10001001 – (00110000) (c)00010011 – (01111001)
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ECET 215 Lab Manual
4. Draw an XOR gate, write its equation, and fill in its truth table.
Symbol: Boolean Equation:
A
B
Y
5. Draw an XNOR gate and fill in its truth table.
A
B
Y
6 . Figure 4-1 is one design of a full adder. Equations for the outputs can be easily derived
from the truth table of the full adder. You willNOTbe building this circuit as given.
Figure 4-1, Full Adder Logic
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ECET 215 Lab Manual
evelop a truth table to prove that the logic in Figure 4-1 implements a full adder. First you
D
should write equations for the two final outputs.
A B Cin Pin 6 of U1 Pin 3 of U3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
b . Determine in Figure 4-1 which output is S and which is Cout and label the shaded areas in
the truth table above.
c . Build and test the full adder.BUT FIRST, ask yourselfhow this whole circuit can be
implemented with only two chips (Hint: look at the SOP part of the logic). Now draw a new
logic/pin diagram, build and test your new adder.
New Logic/Pin Diagram: U1 = _________________ U2 = _________________
Test Results:
A
B Cin Cout S
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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ECET 215 Lab Manual
7 .
a. Draw ablock diagram to represent your full adderof #6.
b . Design a 2-bit adder by interconnecting two full adders (using block diagrams for the full
adders).
8 . (Ref. Chapter 7 in text) Design, build, and test a 4-bit adder/subtractor using a 7483 and a
7486 chip (That’s right, you only need two chips).After having your pin diagram checked,
build and test using the operations shown below entering the answers as 4-bit binary,
and indicate whether the answer is ‘correct’ or not.Keep in mind that you are using the
two’s complement system and there are limits to the signed numbers based on how many bits
you are using- in this case, 4 bits.Question: Whatis the largest positive number and the most
negative number (in decimal) for a 4-bit system?
Pinout for 4-bit adder, 7483 (For further information, students should look up the datasheet):
5 - 3 = _________ 3 - 5 = ________ -2 - 5= ________ -4 - 6= ________ 4 + 6 = ________
Correct? (Y/N) Correct? (Y/N) Correct? (Y/N) Correct? (Y/N) Correct? (Y/N)
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ECET 215 Lab Manual
Lab 5: Decoders
(1 Week)
Materials Needed:
readboard/Various wire segments
B
Logic Probe
74S138 decoder
7420S Dual 4-input NAND Gate
Built-in LEDs
Built-in on/off switches
Pre-Lab and Background Information:
ecoders:A decoder has several inputs active butonly one of several outputs active at any
D
moment. Decoders are often used in memory systems to enable a particular section of
memory while disabling the rest.
or example the 74138, which has three different enablesall of which must be active to
F
enable the chip (two active-low and one active-high), has three active-high data (select)
inputs (A2, A1,A0) and eight active-low data outputs(O0 thru O7) , of which only one can be
active at any time. Below are the chip layout and schematic diagram for the 74LS138 decoder.
E1 and E2 are active low and E3 is active high (it’s not quite clear in the diagram but E1 and
E2 have bars of them and E3 does not).
Figure 5-1.The 74LS138 Decoder.
e can say that the 74LS138 decodes the value of the input; for example, if the input
W
(A2A1A0 ) is 011 then output number O3, pin 12, willbe low (active) and all other outputs will
be high (inactive).
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ECET 215 Lab Manual
II. Procedure:
. Complete the function table for the 74138 decoder by filling in all the shaded areas underSelectand
1
Output. Note that input C is the MSB for Select. Thetable is partially filled in for you. Before
completing the table, carefully reread the information about the chip on the previous page.
Enables S elect Output
hip
C
E1 𝐸2 𝐸3 A
A A
O
O
O O
O
O
O
O
State
2 1 0 0 1 2 3 4 5 6 7
X X 0 X X X
Disable X 1 X 1 1 1 1 1 1 1 1
d 1 X X
0 0 0
0
1
1
1
1
1
1
1
Enabled 0
0 1
1 1 1
Combinational Logic Using Decoders
. Given: a ‘138 Decoder and 4-input NAND gate chip, with F1(R,S,T) = Σm (…) and
2
F2(R,S,T) = Σm (…). Each lab group will be given a set of numbers to use for F1 and F2.
a. Draw a block diagram of the system (just showing inputs and outputs).
b. U
sing the approach discussed in class, draw the logic using the decoder and any appropriate
NAND gates for the outputs (assuming you can have the number of inputs to the NANDs you
need).
c. D
raw a “pin diagram” making use of the available chips (don’t forget the enables for the
decoder). Build and test. Ask yourself what you should do if you have unused NAND gate
inputs.
d. Build and Test, showing your instructor your working circuit.
. Design a logic circuit to control the distribution of a 1 Hz clock signal. You will only need a 74138
3
chip and a 7420 chip. The control signal will be a 3-bit number, ABC, and when its value is 310 or 510
or 710the clock signal will be allowed to pass through.Hint:make use of one of the enable inputs on
the decoder.Note:the decoder is actually being usedas a demulitplexer here.
a. Draw a block diagram and then create and draw the logic as a pin diagram.
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ECET 215 Lab Manual
b. Build, test your circuit, and have it checked by your instructor.
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ECET 215 Lab Manual
Lab 6: Multiplexers
(1 Week)
Materials Needed:
readboard/Various wire segments
B
Logic Probe
74157 Quad 2:1Multiplexer
Built-in LEDs
Built-in on/off switches
. Pre-Lab and Background Information for Lab 6
A
A multiplexer, often used in communications applications, can ‘funnel’ several lines at its
input into a single line at the output. They use select lines to “choose” which input gets
through to the output. Figure 1 below illustrates a 2 to 1 multiplexer.
Figure 6-1:Symbol of one of the 2:1 multiplexersfound inside the 74157 chip.
I n Figure 6-1 above the OE signal isOutputEn ableof the chip (Y1). Since this signal is
active low, a logical zero has to be put on its line for the output to be enabled. When the chip
is disabled, OE =1, the output is driven to logic 0. Also from Figure 6- 1 the select line is
labeled A/B and determines the output at Y1. Finally, A1 and B1 are the two individual input
signals that are selected by the select line A/B (‘0’ at A/B selects input A1 and ‘1’ selects B1).
This select line is also connected to the other three multiplexers inside the 74157 chip as
shown in Figure 6-2.
Figure 6-2:74157 Quad 2:1 multiplexer chip: pin diagramon left and logic on right
his chip contains four 2:1 multiplexers inside. These four multiplexers share the select
T
and Output Enable line. This is therefore a 4 bit channel multiplexer.
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ECET 215 Lab Manual
Procedure for Lab 6
sing a quad 2:1 multiplexer, build a circuit which accepts 4-bit binary numbers as inputs
U
withA=A3 - A0,B= B3 - B0 and has a 4-bit binarynumber for its output,Y= Y3 - Y0.
Operation:Y=AorY=Bwhen the select line is0 or 1, respectively.
1 . Use 4 switches for theAinputs and 4 switchesfor theBinputs. Connect theYoutputs to 4
LEDs. Also, use a wire which you will connect to a '1' or '0' for the select input. Once your
circuit is working properly, connect the input wire to a square wave (using a very slow
frequency) to implement a time multiplexed output which you can see changing. In your lab
report, briefly explain what this means.
I MPORTANT:For your pin diagram, use the logic shownon the right in Figure 6-2 but show
the multiplexers vertically rather than horizontally and don’t forget to show the input
switches, the connection of the clock, the output LEDs and, of course, the correct pin numbers
for the four mux’s.
I t is suggested that you have the switches set with A = 1010 and B = 510 so that it is obvious
the multiplexer is working. To picture what the output will look like, think of a sign
displaying the number the number 5 for a second the number 10 for a second, etc.
Show your logic pin diagram and your working circuit to your instructor for check-off.
2. Based on your circuit designed and built in (1) complete the timing diagram below for Y.
OE 0 0 0 0 0
A(4 bits) 1010 1010 1010 1010 1010
B (4 bits) 0101 0101 0101 0101 0101
A/B (clk) 0 1 0 1 1
Y (4 bits)
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ECET 215 Lab Manual
Lab 7: Introduction to Latches, Flip-Flops and Counters
(2 Weeks)
Pre-Lab and Background Information
Latches and Flip flops are devices comprised of logic gates. However, there is
f eedback from the output back to the input that allows saving (storing) of states. The major
application of a latch or flip-flop is to store a bit. If it stores a ‘1’ the device is said to beset
and if it stores a ‘0’ it is said to beresetorclear.Computer memory such as RAM use many
flip flops to store data. Essentially, flip flops provide digital logic with memory.
Registers are simply groups of flip flops. One type of register is a counter. Counters
are used for many applications. In this lab you will design and build a 3-bit binary up counter.
This counter will repeatedly count from 000 to 111 or, in decimal from 0 to 7. Once you build,
test and trouble shoot your counter do NOT dismantle your logic because you will be using
this counter in the project to be designed and built for the final lab.
Materials Needed:
B
● readboard/Various wire segments
● Logic Probe
● 7447 (BCD to 7-segment decoder/driver)- included in digital trainer and hardwired to seven
segment display
● 7475 (quad D Latch)
● 7474 (dual positive edge triggered D flip-flop)
● 7476 dual negative edge triggered JK flip flop with asynchronous clear and preset
● Built-in LEDs and seven segment display
● Built-in on/off switches
Background:
he ‘D’ latch, the ‘D’ flip flop, the JK flip flop, and the ‘T’ flip flop are the main devices we
T
are interested in for this lab.
he difference between a latch and a flip flop is that the latch is level-triggered and the flip
T
flop is edge triggered. The Q output of a ‘D’latchwill follow the D input as long as the CP
is active, usually active high, and will store the last value at the D input, just before the CP
goes inactive. On the other hand, the Q output of a ‘D’flip flopwill only store what is at ‘D’
for the instant that a clock edge occurs. Flip flops can be negative (falling) edge triggered or
positive (rising) edge triggered.
digital counter is used to produce certain states that appear in a specific order. The counter
A
is comprised of interconnected flip flops with the number of flip flops determining how high
the counter can count; for example a 2 bit up counter, a 3 bit counter, and a 4 bit counter can
count from 0 to 3, 7, and 15 or from 00 to 11, 111, and 1111, respectively. A simple counter
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ECET 215 Lab Manual
h as only one input, referred to as the clock, and the number of outputs depends on how many
flip flops are used in the counter.
Reference
Kleitz, Wm.,Digital Electronics: A Practical Approach,Pearson Prentice Hall, latest editon.
re-lab Exercises: Enter the following into your lab report before beginning
P
the lab procedure.
1. D
raw the symbols with labels and show a function table (only in part (a) should the
clock be shown in the function table) for each of the following:
a. D-Latch with high level CP
b. Positive Edge Triggered D Flip Flop
c. Negative Edge Triggered D Flip Flop
d. Negative Edge Triggered JK Flip Flop:
e. Positive Edge Triggered JK Flip Flop with active lowasynchronousclear and preset:
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ECET 215 Lab Manual
2. S
how how a JK flip flop with negative edge triggering can be converted into a D flip
flop with positive edge triggering:
3. S
how how a positive edge-triggered JK flip flop can be converted into a positive edge
triggered T flip flop (T flip flops toggle if T is ‘1’ and continue to store the last value
of Q if T is ‘0’):
Procedure for Lab #7
I n your lab report show pin diagrams, connections to switches, LEDs,
oscillator, and function tables for all tests and answers to all questions.
Make use of the flip flops listed in the “Materials Needed” Section. Be
careful in the configuration of asynchronous presets and clears!
(Asynchronous means not dependent on the clock or not synchronized.)
1. T
est a 7475 ‘D’latch.
a. Test the D latch showing that you can control what is stored by controlling the CP
and the D input using switches and an LED on Q.
b. Connect a square wave to D and show you can control its output on Q with a switch
at CP.
OTE: You will need a clock edge to test the followingflip-flops. Two possible
N
ways to get an edge using the digital trainer are: (1) use the clk_out which you
should set at 1 Hz or (2) Use the (debounced) pulsers PB1 and PB2 in the digital
trainer for edge triggering of flip flops (see page 10 in the Instruction Manual).
Research Questionsto be answered in the lab report:
A) What does ‘bounce’ mean in regard to flip flops?
B) Why do we need debounced push buttons for testing edge-triggered FFs?
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ECET 215 Lab Manual
2. T
est a 7474 ‘D’flip flop. Using a pulser at the clockinput show that the storage at Q
only occurs on the clock edge and not when no clock edge occurs.
3. T
est a 7476 JK flip flop. Show the instructor it acts like an SR flip flop for JK inputs of
00, 01, 10 and will toggle when the inputs are ’11.’
1. Configure a triggered JK flip flop to act as a ‘D’ flip flop and test it.
1. onfigure a JK flip flop to act as a ‘T’ flip flop and complete the logic diagram below
C
for Q based on four pulses created with the push button, with T held high, assuming Q
starts at 0.
T
Clk
Q
Research Questionto be answered in the lab report:
Looking at the waveforms just completed, while the flip flop is toggling what is the
relationship of the frequency of Q to the frequency of the input clock?
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ECET 215 Lab Manual
2. D
esign, build and test a continuous three bit binary ripple up counter using JK’s
configured as T-flip flops.(D
O NOT DISMANTLE YOURCIRCUITBECAUSE IT WILL
E NEEDED FOR LAB 8, FINAL PROJECT. ALSO, TRY TO BUILD THE CIRCUIT
B
COMPACTLY BECAUSE YOU WILL NEED ROOM ON YOUR BOARD FOR OTHER
CHIPS IN THE PROJECT.)For testing purposes, connectthe FF outputs to LEDs. Also,
onitor the clk_out with another LED. Connect all the asynchronous presets and clears to
m
5V.Q. Why is this necessary? Your pin diagram inthe report will be checked at the
same time the counter is checked that it’s working.
3. R
EAD THE FOLLOWING CAREFULLY AS TO HOW TO MAKE USE OF THE 7447
(chip shown below) that is already hard wired on your trainer. Connect a seven segment
display to your counter in #6. The trainer has a built in 7447 chip (BCD to 7-segment
decoder/driver- see pin-out below) as well as the 7-segment LED display discussed in
Appendix B.VERY IMPORTANT:The 7447 BCD input isDCBA with the ‘D’ input
being the MSB and ‘A’ input being the LSB. Normally you need to use resistors
between the 7447 outputs and the LED inputs of the 7-segment display to avoid burning
out the LEDs but the Digital Trainer has resisters already built in. For this lab, you need
to tie the ‘D’ input of the 7447 to ‘0.’Question:Why?
efore connecting your counter outputs to the 7447 inputs:(1) disconnect the outputs
B
from the LEDs, (2) test the seven segment display by momentarily setting the active low input
𝐿 𝑇 (Light Test) to zero, (3) tie (and leave)the DE input to a ‘1.’
omplete the following block diagram in your lab report before your detailed pin
C
diagram (showing and labelling all inputs and outputs for each block while keeping in
mind the connections between the 7447 and the 7-segment display are hard-wired on the
trainer):
7-segment LED
Counter 7447 Display
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ECET 215 Lab Manual
Lab 8: Birthday Display Project
(3 Weeks)
Awards:
his project has three awards towards the final lab grade associated with it: (1) 5 points for
T
the most professional looking pin diagram (critical to get right for this lab), (2) 5 points for
the most professional looking (working) circuit and (3) 5 points for first working project.
Pre-Lab and Background Information
This lab focuses on the ability to interface different digital logic technologies, mainly
s equential/combinational logic and a display. Each lab group is being asked to display one
student’s birthday on a seven segment display. This task requires a binary counter and
combinational logic that would drive the seven segment display and account for each number
in the birth date. Outputs would be connected to appropriate terminals on the display chip and
the proper display segment would illuminate. However, the students are allowed only one
seven segment display to achieve this goal, therefore the birthday will be displayed
sequentially one digit at a time.
Objective: A birthday date will be displayed in a sequence in order using a single
7 -segment display. In addition, the digit being displayed must be illuminated just long enough
to be read by an observer. Your counter would switch states too fast to be viewed properly if
the frequency of the clock is too high and the seven segment would appear as the number 8 all
the time, so a clock frequency of 1 Hz is recommended.
Materials Needed:
● readboard/Various wire segments
B
● Three bit counter from Lab 7
● Logic Probe
● 7404 Hex Inverters
● 7476 Dual negative-edge-triggered JK flip-flops with asynchronous preset and clear
● 7410 Triple 3-input NANDs
● 7400 Quad 2-input NANDs
● 7420 Dual 4-input NANDs
● Built-in LEDs
● Built-in on/off switches
● Seven segment display plus 7 resistors for current limiting
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ECET 215 Lab Manual
OTE:Unlike in lab 7, here we willNOTuse the built-in7-segment display and the 7447
N
chip because we are displaying not only numbers but other symbols. The state diagram
example below will make this clearer.
Below is an example to follow for this lab:
Let’s say that the birthday is May 15, 1995. Then the display should repeatedly show:
0 🡪 5 🡪 ▬ 🡪 1 🡪 5 🡪 ▬ 🡪 9 🡪 5 and repeat
I ncluding the dashes, this requires eight states which we have with our three bit counter. Note
that there’s no dash between last and first states because that would require nine states.
raw the State Diagram for the encoder using Moore style with state/output inside the
D
circles (to be drawn in class):
Figure 8-1, State Diagram for Example
sing the state diagram, complete a truth table for the logic to create the proper output
U
fot the each count (suggestion: draw a seven segment display to right of the following
table):
Needed Inputs to theactive-low
COUNTER OUTPUT ESIRED
D Inputs of 7-segment display
DISPLAY
ON 7-SEG.
Q2 Q1 Q0 a b c d
e f
g
0 0 0 0 0 0 0 0 0
0 1
0 0 1 5
0 1 0 ▬ 1 1 1 1 1 1 0
0 1 1 1
1 0 0 5
1 0 1 ▬
1 1 0
9
1 1 1 5
Table 8-1: Partially Completed Truth Table for theEncoder logic
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ECET 215 Lab Manual
sing Table 8-1, we will create 7 K-maps to find simplified equations for the encoder logic.
U
The counter outputs three bits requiring three input K-maps and seven K-maps will be needed,
one for each of the seven inputs to the display. We will only develop the first four equations:
Q1Q0
Q2 00 01 11 10
0
1 a=
Q1Q0
Q2 00 01 11 10
0
1 b =
Q1Q0
Q2 00 01 11 10
0
1 c =
Q1Q0
Q2 00 01 11 10
0
1 d =
OTE: outputs e through g are not shown, students should use K-maps to come up with
N
these equation for practice.
Table 8-2, K-Maps for Example
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ECET 215 Lab Manual
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ECET 215 Lab Manual
o remind ourselves of the whole system, draw and label the inputs and outputs for each
T
block of theblock diagrambelow of the example (includecurrent limiting resistors for the
7-segment display):
(This block diagram must be in the lab report)
ignal
S Counter Encoder -segmernt
7
Generator display
(1 Hz ( Either ( designed and
square ripple implemented
wave) counter or with only
7493 chip) combinational
logic)
Draw the logic for the Encoder Block using the equations developed in the K-maps:
Start of logic for Encoder for our Example:
eminder: inputs to the encoder are Q2, Q1, and Q0 from the counter and the seven
R
active-low outputs, a through g, will be the inputs to the seven segment display.
II. Procedure for the Birthday Display Project
s stated in the objective at the beginning of this lab: A birthday date will be displayed in a
A
sequence in order using a single 7-segment display. In addition, the digit being displayed must
be illuminated just long enough to be read by an observer. Your counter will switch states too
fast to be viewed properly if the frequency of the clock is too high and the seven segment
would appear as the number 8 all the time, so a frequency of 1 Hz is recommended.
he block diagram above is the most important concept to understand in this lab- you need to
T
keep it in mind as you create the full design. The main parts of the block diagram that you
will be building are the counter which should still be available from the last lab (or you can
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ECET 215 Lab Manual
u se a 7493 chip) and the encoder. Follow the example in the pre-lab as described on the next
page.
Using the industrial modular approach to the design:
1 . Draw a state diagram of one partner’s birthday employing the Moore approach as used in
the introduction example (State/Output in each circle), Figure 8-1. A state table is not
necessary because it is just the same as a simple counter.
2. Create a truth table similar to Table 8-1 in the Pre-Lab.
3 . Create the seven equations (a through g) needed for the encoder using K-maps and draw
rough diagram of the logic as in Table 8-2. Recommended: use a 7404 chip to create
complements of the Q’s instead of taking them off the flip flops of the counter.
4 . Everything should be in your lab report but draw the block diagram and full schematic (pin
diagram) including the 3-bit counter. If you need to draw across pages make sure you
carefully label all signals. Include Pin numbers and chip key (U1, U2, etc.). MULTISIM can
be used to test and debug circuits. Also, MULTISIM is an easy tool to get all pin numbers and
the chip key.
FINAL IMPORTANT STEPS:
( 1) Test that your counter from the last lab is still working (or that the 7493 is working)
using LEDs at its output before connecting to the new logic.
( 2) Check the encoder before connecting to the counter by using three switches as input
to the encoder logic to check that correct segments are lighting. These switches are very
useful for troubleshooting any segments not properly coming on.
ompletion and Grading of the Project
C
(s ee note regarding award points on first page ofthis project)
ou must have the following items checked and accomplished in order (note the
Y
grading in the parentheses):
_____________1st: (25 %) Full Pin Diagram (neat andreadable) in the lab report
_ ____________2nd: (25 %) The counter (working) fedinto 3 LEDs and using the
clock on the Digital Trainer as input to your counter
_ ____________3rd: (25 %) Encoder combinational Logic(working) connected to
7-segment LED and input by 3 switches (NOT the counter)
_____________4th: (25 %) The whole system working
-49-
ECET 215 Lab Manual
Appendix A
Carbon ResistorColor Codes
esistor Color Codes
R
Significa MultiplieToleranc Failur
Color
nt Digit r e e Rate
Black 0 1 +/- 20% ----
Brown 1 10 +/- 1% 1.0
Red 2 100 +/- 2% 0.1
Orange3 1000 +/- 3% 0.01
Yellow 4 10000 +/- 4% 0.001
Green 5 100000 ---- ----
Blue 6 1000000 ---- ----
Violet 7 10000000 ---- ----
Gray 8 ---- ---- ----
White 9 ---- ---- ----
Gold ---- ---- +/- 5% ----
Silver ---- ---- +/- 10% ----
No
color ---- ---- +/- 20% ----
band
xamples and Problems (neglecting tolerances)
E
1. 100 Ω =brn blk brn 4. 100 k Ω = _______________
2. 2.2 k Ω = red red red 5. yel org grn = ________________ Ω
3. 3.3 M Ω =_______________ 6. Brngrn org = ________________ Ω
-50-
ECET 215 Lab Manual
Appendix B
A Sample BreadBoard
Notes:
1. I t appears there are a total of four separate buses at the top and bottom of the
breadboard but actually there are 8 because each one only goes half way across.
2. D
o not use wires heavier than gauge 22 so that the holes are not made bigger than they
should be.
3. W
ires should not stripped for longer than necessary to avoid having bare wires touching
each other
4. Use of “daisy-chaining” will make your circuits less cluttered.
5. I t is recommended that power be brought to the chips before signal wiring and also the
power wires be a different color to have those wires stand out.
-51-
ECET 215 Lab Manual
Appendix C
7 Segment Numeric LED Displays
wo of the most common 7-segement display configurations are the common Anode and the common
T
Cathode. In our lab we have the common Anode. The internal and external connections for a common
anode display are shown in the figures below.
Note: for a common cathode display the first row in the table would be:abcdefg=111 1110
Pin-out for the Common Anode Seven Segment Display used in lab 7:
-52-
ECET 215 Lab Manual
Appendix D Some Logic Gates From the 74 series TTLIC Family
-53-
ECET 215 Lab Manual
Appendix D Some Logic Gates From the 74 series TTLIC Family Continued
-54-
ECET 215 Lab Manual
Appendix D Some Logic Gates From the 74 series TTLIC Family
Teamwork Report
(Confidential:neither you nor the instructor willshare this with your partner(s))
elow you are analyzing yourself and your partner(s). Be honest in both cases, teamwork
B
problems need to be corrected early!
Your Name:
Circle the appropriate number
Doing my part:
Attendance (Poor) 0 1 2 3 4 5 (Excellent)
On time for labs 0 1 2 3 4 5
In effort extended 0 1 2 3 4 5
In being accessible 0 1 2 3 4 5
My partner ‘A’ is doing his/her part: Initials of partner ‘A’: ________
Attendance 0 1 2 3 4 5
On time for labs 0 1 2 3 4 5
In effort extended 0 1 2 3 4 5
In being accessible 0 1 2 3 4 5
My partner ‘B’ is doing his/her part: Initials of partner ‘B’: ________
Attendance 0 1 2 3 4 5
On time for labs 0 1 2 3 4 5
In effort extended 0 1 2 3 4 5
In being accessible 0 1 2 3 4 5
COMMENTS:
1. What my partner(s) can do to improve?
2. What I can do to improve myself?
3. What can be done to improve the course in terms of teamwork?
4. What can be done to improve the course in general?
-55-
ECET 215 Lab Manual
Appendix F, Scoring Rubric for Labs 1 -8
Group # _____________ Names __________________________ , DATE: _________
LABS COVERED: 1, 2, 3
T of C: ____/ 10
Lab # 1 (Intro to DC 2 (Intro to Basic Gates) (Simplification of
3
Circuits) Boolean Expressions)
eader
L
Recorder
Checker
Schematic for 1
* Pin diagrams and tables for
* ( show all logic diagrams in
* Table in 1d AND, OR, NOT, NAND report)
* KVL for 1e gates *1a, Canonical Expression
* Schematic for 2 * OR with inverted inputs pin * 1b, Truth Table
* Table in 2d diagram and table *1c, Boolean Algebra
* KCL for 2e * Fig 2-9 equation, pin *1d, new Truth Table
diagram, truth table, checked *1e, full pin diagram (incl.
____/12 that it’s working switches and LEDs)
* 3(e) Reduced equation for *1f, Costs
Fig. 2-9 *2a – 2d SOP, POS, algebra
on SOP, Costs
____/12 *2f, K-map and comparison
___/22
_
Q1. Briefly, what is the *3a, truth table
Question for 2f
* difference between power and *3c, pin diagram built and
* Question 3 signal? working
* Briefly compare your *4a, Canonical Expression
____/6 results in 2(d) with the results *4b, K-map and simplified
in 2(b) expression
* Briefly, what conclusion *4d pin diagram, built with
can you draw from 2 (e)? NAND logic, tested and
____/6 checked
____/15
Completion Status
TOTALS _____/18 _____/18 ____/37
INAL TOTAL:
F _____/83 (including T of C)
General Comments
-56-
ECET 215 Lab Manual
Group # _____________ Names __________________________ DATE: _________
LABS COVERED: 4 - 6
T of C: ______/5
Lab # 4 (Adder/Subtractor) 5 (Decoder) 6 (MUX)
eader
L
Recorder
Checker
Arith. Probs. ____/5 Pin Diagram ______/5 Pin Diagram ______/5
Adder Pin Diag, ____/5 Logic Working ______/5 Logic Working _____/5
Adder working ____/5 Waveform ______/3
Add/Sub Pin Diag ___/5
Add/Sub Work’g ___/5
Results Q’s ____/5
Total: ____ /30 Total: ____ /10 Total: ____ /13
FINAL TOTAL ____/58 (including T of C)
General
Comments
-57-
ECET 215 Lab Manual
Group # _____________ Names __________________________ DATE: _________
LABS COVERED: 7 and 8
T of C: ____/5
Lab # 7 (FFs and Counters) 8 (Birthday Project)
eader
L
Recorder
Checker
3-bit ctr pin diag. ____/5 State Diagram ______/5
Ctr working w/LEDs ____/5 State Table ______/10
Ctr. Pin diag w/7447 ____/5 7 K-maps and equations _____/5
Ctr working w/7447 ____/5 Block Diagram _____/5
Q: Why D = 0? ____/5 Full Pin Diagram of Project ____/10
Working Project:
Encoder Portion w/7-segment _ ___/10
Entire project working together ____/10
Total: ____ /25 Total: ____ /55
FINAL TOTAL ____/85 (including T of C)
General OTE: See project (lab 8) for extra points
N
Comments available for this lab.
Total Lab Points: 83 + 58 + 85 = 226
-58-
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