Logical checks (LEC Checks)

Monday, August 21, 2023 3:13 PM

What is sign off?

• Sign off is a process of logical and physical verification of our chip.

Three types of checks done in sign off stage

• Logical Checks
• Physical Checks
• Power Checks

Sign-off Checks

Logical Checks
• LEC ( Logical Equivalence Checks)

• Post Layout STA

Physical Checks
• LVS (Layout vs Schematics)

• DRC (Design Rule Checks)

• ERC (Electrical Rule Check)

• Antenna Check

Power Checks
• Dynamic IR

• EM (Electromigration)

Input Requirements

LEC Checks: — Goldent Netlists (.v) & revised netlist

tools from cadence : conformal lec — Library (.lib and .lef)
— Constraints (.sdc)
synopsis : formality lec
---- .saif (optional)

 It will check the functionality of RTL to Post rout netlist, whether it is same or any
diffrence in any logical functionality.

Ex:

• This function Y=A.B should be same from RTL to Routed netlist

• The functionality shud be maintained through out the process.

In LEC the tool matches the two given netlist with respect to inputs and
outputs ( logic 0 or logic 1)

This can be done in two ways:

1. Functional verification
2. LEC Check

For doing LEC

• We Want
1. {Golden netlist [synthesis netlist or scaned netlist] }
For doing LEC

• We Want
1. {Golden netlist [synthesis netlist or scaned netlist] }

1. { Revised netlist [recent netlist after each stage]}

Y = f(A,B,C) --golden netlist

Y'= F (A,B,C) +g(a,b,c) {extra stuf}

like i.DFT scan
ii.PNR related modification (like adding buffer , optimizing some connections,)

• we are comparing here Y to y' and we don’t wnt tht extra stuff so, we add some contraints to LEC so tht the logic
becomes 0 for== g(a,b,c)

Now,
y'= f( A,b,c) +0

• Now both y and y' are same because of adding some constraints which makes tht extra logic that has been added to the
revised side of the netlist as som logic 0 ..so tht it wont effect to the functionality.

Now,
• We compare y to y' , it make sense for comparision.

Let see how tool will calculate…

i. Tool can do any amount of boolean calculation.

ii. So but flops, latchs, blck boxes cant be written in as a boolean logic.

So what tool does is it wont write seprate boolean expressions for flops …but it will write for the whole path … like 3 flops
and 1 combo logic and FF-1 .

Now it compares with y' …. In y' assume there are two more inputs rather than FF-1 i.e SI and SE.
For tht SI and SE we will add 1 mux ..as shown in above pic
 Formal Verification

— Verify the two representations of circuit design exhibits same behavior

— Checks the behavior of the Combinational Logics by checking the Compare Points

Golden netlist Revised netlist

— Targets implementation errors and not the design errors

Types of Formal Verification

— Gate-level to Gate-level (Logical Equivalence Check after Routing)

• To ensure that some netlist post-processing did not change the functionality of the
circuit

— RTL to Gate-level (after Synthesis)

• To verify that the netlist correctly implements the original RTL code

— RTL to RTL (before Synthesis)

• To verify that two RTL descriptions are logically identical

• Logical Equivalence Check (LEC) will have two stage

— Constrains setup stage
— Logical Equivalence Check stage

 Tool will report equivalent/ non-equivalent/ abort/ not-checked

LVS
Wednesday, August 23, 2023 3:26 PM

LVS (Layout vs Schematics)

• Inputs: .v netlist of the design, GSD-layout database of the design, LVS rule deck (.v
and GDS should be of the same stage).

• LVS rule deck file contains the layer definition to identify the layers used in layout file
and to match it with the location of layer in GDS. It also contains device structure
definitions.

 a schematic is a graphical representation of an electronic circuit,

 while a layout is a physical implementation of the circuit. The schematic shows the logical connections
between the components, while the layout shows the physical placement of the components and their
interconnections.

 The schematic is created first, and then the layout is created based on the schematic.
 The layout process involves placing the components on a chip and connecting them together.
 The layout must be carefully done to ensure that the circuit functions properly and meets all of the design
requirements.

 The schematic provides a high-level view of the circuit, while the layout provides a low-level view of the
circuit.
 Together, they ensure that the circuit is designed correctly and can be fabricated successfully.
 GDSII file

A GDSII (Graphical Design System II) file is a binary file format that is used to store the layout data of an
integrated circuit (IC). It is the de facto industry standard for exchanging layout data between different
electronic design automation (EDA) tools.

A GDSII file contains the following information about the layout of an IC:

• The geometric shapes of the components, such as transistors, wires, and resistors.
• The layer information for each shape, such as the material type and the thickness.
• The connectivity information between the shapes.
• The text labels for the shapes.
• The hierarchical structure of the layout, which allows for complex layouts to be represented in a more
compact way.

LVS flow
 From the design take the netlist(.v) which is in verilog format , convert that netlist to source
netlist (.cdl) with that gather and merge some spice files , like std cells and macros.
 The conversion is done through V2lvs command . Which converts our (.v) netlist to source netlist
which is known as spice netlist in the form of (.cdl)

 Now extract the GDSII file from the design and merge other gds files along with it. This is in the
form of binary formate.
 After taking this GDSII file we wil extract ..during this extraction we will do ERC (electrical rule
check). And we get a report on ERC.
 From the extraction we will get "layout netlist" in the form of (.sp) which is called spice netlist.

▪ Now compare both "source netlist" and "layout netlist" to get the LVS Report

• Comparison:
LVS check includes following comparisons:
○ The extracted layout netlist is then compared to the netlist of the same stage
using the LVS rule deck. In this stage the number of instances, nets and ports • Number of devices in schematic and its layout.
are compared. All the mismatches such as shorts and opens, pin mismatch • Type of devices in schematic and its layout.
etc.. are reported. The tools also checks topology and size mismatch. • Number of nets in schematic and its layout.

Typical errors which can occur during LVS checks are:

• Shorts: Shorts are formed, if two or more wires which should not be connected together are connected.
• Opens: Opens are formed, if the wires or components which should be connected together are left floating or
partially connected.
• Component mismatch: Component mismatch can happen, if components of different types are used (e.g, LVT
cells instead of HVT cells).
• Missing components: Component missing can happen, if an expected component is left out from the layout.
• Parameter mismatch: All components has it’s own properties, LVS tool is configured to compare these
properties with some tolerance. If this tolerance is not met, then it will give parameter mismatch.

 LVS stands for Layout vs Schematic it is used to compare layout and schematic netlist to check
the difference between schematic and layout in terms of connections and number of
transistors.

 We will extract the spice netlist from both layout and source netlist and compare each other if
there is no in-equality then in report it will show as LVS pass.

In this we can check:

 • Opens
• Shorts
• Floating gates
• Pin mismatch
• Parameter mismatch
• Component mismatch
• Incorrect nets
• Missing cells
• Miss spelled text

LVS checks include:

comparision errors:

 incorrect nets
 incorrect ports
 incorrect instances
 component mismatch
 parameter mismatch

extraction errors:
 opens
 shorts
 floating nets
 missing components

LVS check involve three steps

• Extraction:
○ The tool takes GDSII file containing all the layers and uses polygon based approach to determine the
components like transistors, diodes, capacitors and resistors and also connectivity information
between devices presented in the layout by their layers of construction. All the device layers,
terminals of the devices, size of devices, nets, vias and the locations of pins are defined and given an
unique identification.
• Reduction:
○ All the defined information is extracted in the form of netlist.
• Comparison:
○ The extracted layout netlist is then compared to the netlist of the same stage using the LVS rule deck.
In this stage the number of instances, nets and ports are compared. All the mismatches such as shorts
and opens, pin mismatch etc.. are reported. The tools also checks topology and size mismatch.
 DRC Checks
Thursday, August 24, 2023 4:09 PM

• Design rule checks are nothing but physical checks of metal width, pitch and spacing requirement for
the different layers with respect to different manufacturing process.

• If we give physical connection to the components without considering the DRC rules, then it will lead
to failure of functionality of chip, so all DRC violations has to be cleaned up.

• After the completion of physical connection, we check each and every polygon in the design, based on
the design rules and reports all the violations. This whole process is called Design Rule Check.

• Inputs of DRC: a layer map file is a file that maps the layers
in a design to the layers in a physical process.
Tools:
It is used to translate the design from the
1. GDS abstract level of the design tools to the Synopsys IC Validator
2. .lef file physical level of the fabrication process.
3. Pr summary (pnr data base info)
Calibre ,Virtuoso
4. .def file

 Rule deck file • Layermap file

Types of DRC:

1.Base layer DRC[FEOL]

2.Metal layer DRC[BEOL]
3.HV DRC/VD-DRC

 Base layer DRC[FEOL] : [ OD, Poly, N Well , Substrate]

• OD[oxide diffusion] OD-OD spacing

1. corner -corner
2. notches
3. length
4. Width

• Poly related : cut poly layer

1. min length violations

2. area violations
3. poly width
4. poly spacing
5. corner –corner

• N Well :

1. well to well spacing

2. L-notches
  Metal layer DRC[BEOL]:

• Min metal length

• Min metal width
• Metal to metal spacing
• Via to via spacing
• Min enclosed area
• Via enclosure
• Corner to corner spacing of metal.
• Forbidden spacing(means metal should follow the routing track)

HV-DRC:

HV-DRC checks for spacing violations between the metals of two different voltages.

Ex: one metal with 1.8v and another metal with 1.0v must follow some spacing rules Even it passes the normal DRC some
times it may fail in HV-DRC We need to maintain some additional space as per the given rules.

 How to resolve DRCs?

Ans: First we will find the reason where we get the violation. like minimum enclosed area, min width, min spacing
etc., According to the violation we will change the spacing, width, enclosed areas in the tool.

• DRC (design rule check )

=====================

• We know that layout means mask used in fabrication process

• Layout we can’t be perfectly fabricated on the wafer.
• So, for the successful fabrication, foundry provides some set of rules called design rules
• DRC is the process of checking layout against design rules
• Violating design rule might get functional failure or low yield

DRC have two categories

• Base Layer DRC's:_
○ Base layer means, all layers before the metal1
○ Examples :- well spacing , poly spacing , poly width , well continuity
• Metal layer DRC's:-
 ○ Examples :- min and max width , min spacing , via enclosure

• Design rule violations

○ Min and max width violations

• Min and max space violation

• Min and max length violation

• Minimum via cut violation

• Minimum via enclosure violation

• Alignment violations (off grid)

• Input files

• GDSII file => Layout information

• Design rule file => design rule information
• Netlist => connectivity information
• Runset file => It tell to the tool to check layout file against design rule file and the result of DRC store in output file
○ input_layout my_chip.gds
input_drc my_chip.drcf
output_drc_report my_chip.drc
Antenna checks
Tuesday, August 29, 2023 3:04 PM

 If VDD is connected means tht is drain.

 Capacitors has two plates separated by a distance having equal and opp. Charges.

C= A

Distance is inversely
proportional to coupling
capacitors

 Etching :

1. Isotropic :etching is done in equally in both the direction i.e horizontal and vertical.

Ex : square

2. An isotropic : etching is done in un equally in both the direction.

3. wet etching : etching is done using chemicals

4. dry etching : etching is done using inert gases . Ex: plasma.

Front end of lane (FEOL) fabrication : all mosfets are constructed .

{ The FEOL refers to the process of creating the transistors and other active components of the
chip}

Back end of lane (FEOL) fabrication : all the constructed mosfet are interconnected.

{BEOL refers to the process of creating the interconnects that connect the transistors together}

 If the width is less, then the coupling capacitor increases, due to which the
RC parasitics decreases, and improve in the transition time , due to that cell
delay decreases.

Antenna effect :

• The antenna effects mainly due to the excessive accumulation of charges on a metal interconnected and
connected to the gate of the transistior during plasma etching of the metal interconnected.
• The amount of accumulated charge depends on the area of metal interconnected, connected to the gate.

• The excessive accumulated charges get discharged through the thin gate oxide, and it cause permanent
damage to the gate oxide.

{The extra amount of charges passes through the gate oxide , through drainage line, which will damage the gate
oxide ,causing the MOSFET to damage }
 The steps to reduce Antenna effect :

 The first method is to reduce the amount of charge accumulation and this can be achived by reducing the area of
metal interconnect to gate of transistor.

 The second method is to increase the gate area so the ratio (metal area)/(gate area) becomes lesser than the
permitted metal to gate area ratio.

 The third method is to provide alternative path to get discharge the accumulated charges on the gate of the transistor
which is addition of antenna diode.

Antenna Ratio :

• The antenna ratio is calculated as the ratio of the metal area connected to the gate to the total gate area.

• The formula for calculating the antenna ratio is:

• Antenna ratio = (Metal area connected to gate) / (Total gate area)

• For example, if a metal line has a length of 100 micrometers and a width of 1 micrometer, and the gate area is 1
micrometer squared, then the antenna ratio is:

• Antenna ratio = (100 * 1) / 1 = 100

Antenna Rule
file

CALIBER Antenna check

results

Design database/
gds file

 Three basic techniques are to prevent antenna violations are: • Physical verification tools (like Calibre, Assura, IC Validator) varifies the antenna
rule for all the layers for which antenna rule is applicable.
1. Metal hopping
2. Floating gate attachment
3. Antenna diode

Antenna Rules
A process design kit (PDK) comes with some rules deck files. The antenna rule set is a part of the rule deck. All the rule set must be checked before the tapeout. In antenna rules,
the most common rule is the antenna ratio.
• Antenna ratio is the ratio of the metal area connected to the gate to the total area of the gate
• Antenna ratio is defined in the following form:
Antenna area / Gate area < Maximum antenna ratio

Example of antenna rule violation

Consider three cases here:

In case-1 suppose metal-2 has length = 200um as shown in the above figure and width of metal =1um. This metal wire is connected to the gate of a transistor. The transistor is
having gate width = 2um and length = 0.6um.
Therefore, Total metal area = 200×1 = 200um^2

Total gate area = 0.6 x 2 = 1.2um^2

Therefore, antenna ration = 200/1.2 = 166.2

In case-2 suppose the situation is same but the metal-2 is connected to 4 such transistors instead of 1.
Therefore, Total metal area = 200×1 = 200um^2

Total gate area = 0.6 x 2 x 4= 4.8um^2

Therefore, antenna ration = 200/4.8 = 41.66

In case-3 suppose the metal-2 is broken into two parts of 50um each and connected through metal-3 as shown in the figure below. Such a connection is called metal hoping.

Now, Total metal-2 area = (50×1)x2 = 100 um^2

Total gate area = 0.6 x 2 = 1.2 um^2
Therefore, antenna ration = 100/1.2 = 83.33

Suppose the antenna ratio is given 100 in the antenna rule. So out of the three cases above explained, Case 1 is violating the antenna rule and case 2 and case 3 is not violating
the antenna rule.

Fixes of antenna violation :

1. Jumper Insertion or Metal hoping

 Best way to break the lengthy metal into small pieces and using jumpers route them through other metal layers as shown in the above figure.
This process is called jumper insertion of metal hoping.

2. Dummy transistor insertion

 The effective gate area can be increased by inserting dummy transistors as shown in the above figure.
 This will decrease the antenna ratio and help to meet to antenna rule.
 In a practical scenario, we can add a floating inverter/buffer.
 We attach the input of buffer/Inverter to the concerned net and leave the output floating.
 This will increase the effective gate area and help to overcome the antenna violation.
 3. Antenna diode insertion :

• Antenna diode -Reverse biased

• Placement location – Near the gate terminal
• Plasma etching 400-800 degree Celsius
• High Temperature – Diode is thermally unstable
• During plasma etching – Reverse saturation region
• At reverse saturation region – like a resistive path
• Normal operation -40 to 125 degree Celsius
• Standard cell – Antenna diode cell
• Single terminal standard cell, N+ on Psub.

 The antenna diode insertion technique involves inserting a diode in reverse bias between the metal line and the gate
of the transistor. The diode acts as a discharge path for the charges collected by the metal line. This prevents the
charges from discharging suddenly and damaging the gate oxide.

 The antenna diode insertion technique is a simple and effective way to prevent the antenna effect. It is typically
used in conjunction with other techniques, such as metal hopping and dummy transistor insertion.

Here are the steps involved in the antenna diode insertion technique:

1. Identify the metal lines that are susceptible to the antenna effect.
2. Insert a diode in reverse bias between the metal line and the gate of the transistor.
3. Route the diode in such a way that it provides a discharge path for the charges collected by the metal line.
ERC checks
Friday, September 1, 2023 3:44 PM

 ERC stands for electric rule check ERC is mainly used to check the electrical related
connections in the design.

 Inputs for ERC is:

 GDSII & rule deck file.

Tools: Mentor Graphics Calibre, Synopsys Hercules, Cadence Assura, Magma Quartz

ERC checks are run to identify the following errors in layout.

• This process checks the connection of the n-well and p-substrate

• One of the electrical rule checks (ERCs) is to verify that the p-well (in this case p-
substrate) is always connected to ground.

• Further, in this n-well process, if the design contains only digital circuits then the n-
well should be connected to VDD.
From <https://www.vlsifacts.com/checking-erc-well-check/>

 In the ERC the checks which we do are:

 Well and substrate that are properly connected such that there will be proper power and
ground connection.

• Gate terminal shorted to power terminal.

• Signal power shorts.
• Metal with missing connections.
• Metal that is shorted.
• Floating inputs.
• Floating gates.
• Power Ground shorts.
• Power ground opens.

Merlin AI
Issues in vlsi
Thursday, September 7, 2023 11:30 AM

Latch-up issue :

1. What is latch up

In simple form : the formation of direct current path between vdd to ground. Which cause large amount of current to flow from power terminal
to ground terminal.

In technically : latch up is the phenomenon of activation of parasitic BJTs in Cmos circuits, which forms a low impedance path between (vdd to
vss) power supply and ground. This low impedance path , draws large amount of current which heat up the IC and cause permanent damage.

▪ In cmos circuit , two parasitic BTJ get formed and connected in such a way that it forms a PNPN device/SCR/ Thyristor.

▪ A PNPN device is normally in off state with minimal current flow, but once it gets triggerd by gate signal it continue to flow large current,
even if the triggered gate signal is removed . This phenomenon is actually called latchedup

2. Formation of parasitic BJT in cmos:

Cmos inverter
 ▪ Now we can make PNP transistor in Pmos , and NPN transistor in Nmos

▪ Where Emitter is connected to P+ and collector is connected to p-substrate and base is formed in n-well to which forms vertical PNP BJT.
▪ Base is connected to VDD through N+ . N-well is lightly doped it has high resistance of Rw (well resistor) connected with base .

▪ Same way even NPN BJT is formed in Nmos .

▪ A horizontal npn BJT has formed in Nmos with RS (resistance substrate).

▪ Here base is connected to P+ with Rs resistance to ground because to connect the body p-susbstrate.

3. Factors :

▪ This is in the circuit form.

 ▪ Unless SCR is triggerd, there is no low impedance path is formed.
▪ BJT has low current gain , so it require large current spike to activate BJT.
▪ B1B2 < 1
▪ If beta1 and beta 2 is greater than 1, then the BJTs gets Activated.

 Resistance of N-well and P-substrate

 Current gain of BJTs

These are the factors .

▪ The resistance will be low in n-well , we cant increase the resistance . Because if we increase the resistance threshold voltage wil also
increase , cause of tht more delay increases.
▪ So we have to cut down the Current gain of BJTs.

4. Working : (latch-up triggering mechanism)

PNPN device formed inside the CMOS can be triggered by various means. Once the PNPN device is triggered by any means, the latch-up event will
start. Some of the main reasons are as below.

• Noise at the output terminal

• ESD (Electrostatic Discharge) event
• Ionizing radiation

Case I : if Vout >> VDD

▪ If the output voltage is beyond VDD i.e Vout >> VDD due to the noise in Vout.
▪ It will form a forward bias transistor between Drain terminal and N-well of P-mos.
▪ Once this junction is forward bias , P+ will start injecting holes to N-well and these holes will be collected by the body contact of N-mos as it is
connected to GND.
▪ So it will start a current flow from drain of P-mos to body of N-mos.
▪ Due this current flow , there will be a voltage drop between Source terminal of the N-mos and the below substrate .
▪ Because of the voltage drop in N-mos between source terminal of Nmos and below P-substrate
▪ It will forward bias the pn junction between substrate and source in Nmos.
▪ This will again start injecting the electrons from N+ source to the substrate which will be connected by the body terminal of the P-mos wich is
connected to VDD.
▪ So eventually a chain will start and next source terminal of pMOS and nwell will be forward bias. In this way both the BJT has turned on and
latched up.

▪ When pn junction is forward bias in PNP transistor, the holes are injected through emiter , the current will flow from collector to GND , if the
voltage drop Rs is high enough then it wil turn on the NPN transistor .
▪ Due to which the electrons are injected through emiter of NPN transistor and current flowing from collector to VDD.
▪ Thus make a latch up , if one transistor is getting turned on then other transistor also gets turned on because of voltage drop.
 Case II : Vout << VDD

▪ Now , similarly if Vout is less than VDD.

▪ first the junction between the drain of nMOS and substrate will be forward bias, and it will make the junction between the source of pMOS
and nwell forward bias and again this will further make the junction between the source of nMOS and substrate forward bias and both the
BJT will be turned on and latch-up will occur.
▪ Once if latch-up occurred in Cmos design, then large amount of current will flow from VDD to VSS due to which more heat is produced and
cause the failure of the chip.

5. Techniques to prevent latch -up :

▪ Some popular techniques for latch-up prevention are :

▪ Guard ring
▪ Well tap cells
▪ Isolation trench
▪ Epitaxial layer
▪ Retrograde well doping
▪ Combination of epitaxial layer and retrograde well doping
▪ FDSOI Technology
▪ ESD protection techniques

 Guard ring :

▪ When Vout is less than VDD , the diode between drain terminal (N+) and P-substrate become forward bias .
▪ Due to which electrons will get injected from N+ terminal , gets collected by the body of the N-well.
▪ So current starts flowing ,due to which it triggers the transistor in N-well
▪ To avoid this flow of current, to break this chain we have introduced guard rings.
▪ First Implant 2 sets of N+ implant in N-well and P+ implant in P-substrate in between both Nmos and Pmos.
▪ Because of this implantation the electrons coming from N+ drain terminal of Nmos will get stored in N+ terminal of Pmos ,and because of this
 there be no flow of current , which stops triggering the BJT in Pmos.

▪ Now if Vout is greater than VDD, the diode becomes forward bias in Pmos and holes will get injected from (P+ ) drain terminal of Pmos, and holes
gets collected by the body of Nmos, which triggers the BJT in Nmos.
▪ By adding the guard rings , these holes will be collected by the guard rings and stops the formation of latch up.

 Well tap cells:

▪ In tapless standard cell design to prevent the latch-up,

▪ we need to tap the n-well to VDD and p-sub to VSS.

▪ These well tap cells tap the n-well to VDD and p-sub to VSS.

▪ Below figure shows the cross section of tapless cell

 Below figure show the layout of well tap cell and tapless standard cell.

Tapless std cell Well tap cell

 well tap cells are placed in the standard cell row in the regular interval as per the maximum distance rule define in technology library.

 Oxide trench isolation:

 In this technique, nMOS and pMOS have insolated using the buried oxide and oxide trench.
 A horizontal buried oxide created deep inside and vertical oxide trenches are created later and connected both together to separate the n-well
and p-substrate.
 The oxide trenches are isolator in nature so oxide trench stops the formation of the PNPN device.
 A cross-section of oxide trench isolation is shown in the below figure.
IR Drop
Thursday, September 7, 2023 2:21 PM

• IR Drop in VLSI is known as an “Intermediate Resistance Drop” at “Very Large Scale

Integration”.

• It refers to the variation in electrical potential between the two ends of a conducting wire
when current flows through it.

• This potential difference is determined by the voltage drop across a resistance, which can be
calculated by multiplying the current (I) passing through the resistance by its resistance value
(R).

According to Ohm’s Law, the IR Drops formula is:

V (Voltage) = I (Current) X R (Resistance)

The calculation required in IR Drop:

1. Average Current Through Each Strap=Istrapavg=(Itotal)/(2*Nstraps)mA

2. Appropriate IR Drop At The Center Of The Strap=Vdrop or IRdrop

=IstrapAvg*Rs*(W/2)*(1/Wstrap)

3. Number of Straps between Two Power Pads Two most popular tools for IR analysis used in
industry are:
• Nstrappinspace=Dpadspacing/Lspace.
• MIN Ring Width = wring = Ip/Rj Microm • RedHawk of Ansys
• Voltus of Cadence Design System

Power dissipation in cmos:

1. Static Power dissipation: there will be a leakage current when the transistor is in steady state.

There are 3 types of leakage current :

• sub threshold leakage current : Subthreshold leakage current in CMOS is the current that flows between the source and drain of
a CMOS transistor when the gate voltage is below the threshold voltage (Vth) i.e in cutt off region.

cut off region

• gate leakage current : Gate leakage current in CMOS is the current that flows through the gate oxide of a CMOS transistor.
It can happen due to Tunneling : Tunneling: Charge carriers (electrons or holes) can tunnel through the gate oxide, even when the
gate voltage is below the threshold voltage (Vth). This is more likely to happen when the gate oxide is thin.

• junction leakage current : Junction leakage current is the current that flows through a reverse-biased pn junction
 • junction leakage current : Junction leakage current is the current that flows through a reverse-biased pn junction

Diode in reverse bias

some leakage current

Static power dissipation : P = supply voltage x leakage current.

2. Dynamic Power dissipation: there will be a leakage current when the transistor is in function mode/switching mode/operation
mode.

There are 3 types of dynamic power dissipation :

• Switching power dissipation: Switching power dissipation in CMOS is the power that is dissipated when the output of a CMOS
gate switches from one logic state to another. It is caused by the energy required to charge and discharge the load capacitance
of the gate. Due to which some there is leakage current.

(switching means charging and discharging of transistor )

C=1/2 cv^2

• Short circuit power dissipation: Short-circuit power dissipation in CMOS is the power that is dissipated when both the NMOS
and PMOS transistors in a CMOS gate are turned on at the same time. This can happen when the input to the gate is changing
rapidly. Pmos is on
Nmos is off

Pmos on
Nmos on

Pmos is off
Nmos is on

• When both transistors are on, there is a direct path from the supply voltage (VDD) to the ground (GND). This allows a large
current to flow, which dissipates power.

• As the input changes slowly, there will be certain duration of time for which some of the transistor(s) in the pull-up network and
pull-down network are turned ‘ON’ simultaneously, forming a short-circuit path from VDD to GND. The region from (t1 tot2).
• Due to which there will a large number of leakage current.

• Glitch power dissipation: During switching activity of signal there will be a glitch in the signal , due to which the leakage current
is drawn.
 • Glitch power dissipation: During switching activity of signal there will be a glitch in the signal , due to which the leakage current
is drawn.

P = 1/2 (v^2 * C * F * )

• C is the load capacitance

• V is the supply voltage
• f is the operating frequency
• α is the switching activity factor

 IR Drop : (voltage related problem) R= *L * ( sheet resistance Rs)

Thickness * width =a

○ Sheet resistance : It is defined as the resistance of a square sheet of the material with contacts made to two opposite sides of the
square.

Rs = ρ / t

where: 

• Rs is the sheet resistance in ohms per square (Ω/□)

• ρ is the resistivity of the material in ohm-meters
(Ωm)
• t is the thickness of the film in meters (m)

Power Delivery Network (PDN):

The power supply (VDD and VSS) in a chip is uniformly distributed through the metal rails and stripes which is called Power Delivery
Network (PDN) or power grid.

 What is meant by IR Drop

When the current flowing through the PDN (power delivery network) , there will be some part of a voltage drop .Due to which a
lesser amount of voltage will be available for std cells than the amount of voltage applied from the source (port).

(Standard cells or macros sometimes do not get the minimum operating voltage which is required to operate them due to IR drop in
power delivery network even the application of sufficient voltage in the power port. Voltage drop in the power delivery network
 before reaching the standard cells is called IR drop.)

If V1 voltage is applied at the power port and current I is following in a particular net which has total resistance R, then the voltage
available (V2) to the other end for the standard cell will be

V2 = V1 – I.R
V2 = V1 - ir1+1r2+ir3+ir4
V2 = V1- I (r1+r2+r3+r4)

 Types of IR drop :

1. Static IR drop

2. Dynamic IR drop

 Static IR drop : Static IR drop is the voltage drop in the power delivery network (PDN) when there are no inputs switching means the
circuit is in the static stage. Or Off stage.

 Dynamic IR drop : dynamic IR drop is the voltage drop in the power delivery network when the inputs are continuously switching
means the circuit is in a functional state. Dynamic IR drop will depend on the switching rate of instance.

 When the inputs are switching continuously, more current would flow in the instances and also in PDN. So there will be more IR drop
in the PDN. Therefore dynamic IR drop is more than the static IR drop.

 Reasons for IR drop:

• Poor (PDN) lesser metal width.

• Less number of vias in power delivery network / less metal straps.

• Less availability of decap cells.

• High cell density (congestion) therefore high switching activity in particular region.

• High impedance of the PDN. ( the PDN has a high resistance to the flow of electric current).

• Rush current (more flow of current ).

• Insufficient number of voltage sources ( means like vias, more straps to flow the current easily).

• High operating temperature: As the temperature of a conductor increases, its resistance increases.

 Effects of IR drop :

• Cell delay increases;;

Delay of standard cells depends on the available power supply to the cell and if the power supply decreases the delay of cell
 increases.

(cell delay depends on input transition and out put load capacitance.)

 This means if the power supply is less then the transistor will take more time to charge and discharge the capacitor then the out put
load capacitance increases thus, delay increases.

 If the supply voltage is less then the transition time will increase due to which cell delay increases.

• Function of the design failure : Could violate the setup and hold timing

 The increase in delay of a cell could affect the performance of the design. It is also possible that if the available voltage to a standard
cells gets below a particular level, then the cell may stop function completely and could result in functional failure of the design.

• Introduction of power noise in power supply nets :

 Voltage droop
 Ground bounce

 Voltage droop :- The sudden drop in the VDD line if the demand of current increases due to large number of switching activities in a
particular area of the design.

 Ground bounce :- sudden raise the level of ground voltage, if there is more demand of current.

(These are collectively called power noise.)

 Remedies to over come IR Drop:-

• Insert sufficient number of De-cap cells (to boost the power delivery network)

• Increase the width of the metal according to current density (or go to higher metal layers) (this decreases the separation
between them)

• If you cant change width more the max width contraints , then go for metal stacking.
• e
• Spread the std cells (means congestion should not be )

• Add more number of straps ( due to which more number of vias will be added for proper supply voltage).

• Use proper CTS structure.

 • Add buffers if the run length of the wire is too long.

• reduce the toggle rate

• Proper power and ground plane placement (proper PDN)

What is metal stacking

Low power
Monday, November 20, 2023 11:55 AM

Power and energy

• Power is drawn from a voltage source attached to the Vdd pins of chip.

Terminologies:

Graphical representation :

• I.p --> instantaneous power

• Pavg --> the red line
• Enery --> the area under the curve

Types of Power Dissipation :

Broadly three types:-

1. Dynamic power
2. Short-circuit power
3. Static power

 Dynamic power :-

- Dynamic power is required to charge and discharge load capacitances when transistors
switch
- One cycle involves a rising and falling out put.
- On rising output, charge Q=CVdd is required to charge the output node to Vdd.
- On falling output , the load capacitor discharges to GND.
 - Consider above example, of inverter.
- When the wave form of "F" is falling from high to low, then the capacitor is discharging and
Current is flowing from c to GND
- When the wave form is rising from high to low , the capacitor is charging and the current
flowing from Vdd to F.
- Where i= C dv/dt
- When the charging and discharging going on there will current flowing , and the product of
current and voltage will be the power consumption.

- We are considering a time period " T"

- Output "F" will be going up and down as u can see in above pic.
- In the same interval of time the capacitance is charging and discharging many no. of times.
- Fsw = frequency of switching.
- T*Fsw --> no. of switching.

 Calculation of Avg Dynamic power:-

 Fsw --> frequency switching

 So, if we reduce the load capacitance then even dynamic power will be reduced.
 Same way, if we reduce the voltage in Vdd, dynamic power will be reduced.
 And if we reduce the frequency, that also helps in reducing dynamic power.

 So, taking activity factor (alpha) ,

 The dynamic power of the gate can be calculated as :

Pdynamic = CVdd^2 * f
  So, taking activity factor (alpha) ,
 The dynamic power of the gate can be calculated as :

Pdynamic = CVdd^2 * f

Short Circuit Power :

EM Analysis
Friday, September 22, 2023 11:55 AM

 What is Electromigration :

○ The gradually displacement of the metal ions from its original position , in the direction of the electron flow because of high current
density in the metal is called elctromigration .

The connection used changes with the scalability of

the technology node. Initially, pure aluminum was
used as an interconnect, but the industry soon
switched to an Al-Cu alloy, and ultimately to copper
interconnects. Copper interconnects can sustain nearly
five times the current of aluminum interconnects
while meeting the same reliability standards.

○ Consider a phenomenon , A potential difference is applied across a metal interconnect which setups an electric field from anode side
to cathode side as shown.

○ This electric field causes to move the electron in the opposite direction of the electric field.

○ This momentum of electron cause flow of current in the electron.

○ These moving electrons have momentum and when it collides with the metal ions the metal ions feel two forces in the opposite
direction as shown in the figure.

○ One force and due to electric field and other is due to strike of electrons wind. If the current density is high the force due to electron
wind is greater than the force due to the electric field.

 Current density : J = I/A

It is defined as a amount of electric current that passes through unit -cross sectional area of conductor .

 Electromigration is the current related problem.

 Reasons for EM :
• P = c *v^2 * f *

• It depends on voltage supply and operating frequency

• If the temperature increases resistance will also increase in metals

• High current density: The higher the current density, the greater the force exerted on the metal atoms. This is because the current density is
proportional to the number of electrons flowing through a given cross-sectional area.
• High temperature: High temperature increases the diffusion rate of the metal atoms. This means that the metal atoms are more likely to move
away from their original positions.
• Grain boundaries: Grain boundaries are regions where the crystal structure of the metal is not perfect. These regions are more likely to have
defects, which can act as nucleation sites for electromigration.

Effects of Em:

• Once the metal ions get started to shifting from its original position, these will create problems in the interconnect. It could result in an excess of
ions accumulation in a particular location of deficient of ions. So either Hillocks or Void could occur in the metal interconnect.

• When high current is flowing in the metal , the heat increases due to which temperature also increases , which will increase the drift velocity of
electrons ,the electrons start drifting from one place . momentum of current-carrying electrons may get transferred to the metal ions during
the collision between them. Which leads to change there positions and form deposits.and voids.

Void: If the incoming ion flux is lesser than the outgoing ion flux, It will create a void in interconnect. A void can lead a discontinuity in the interconnect and
result an open circuit.
Hillocks: If incoming ion flux is greater than the outgoing ion flux, It will cause the accumulation of ions and create a hillock in the interconnect. A hillock can
increase the width of a metal interconnect and touch the neighbouring metal interconnect which may result in a short circuit.
 Dirft velocity of electrons increase

• With the scaling of the technology node, the interconnect used is also changed. Initially, pure Aluminium was used as interconnect then the
industry started using the Al-Cu alloy and later shifted to Copper interconnects. Copper interconnects can withstand approximately 5 times
more current as compared to Aluminium interconnects while maintaining similar reliability requirements.

Remedies for Em :

• Increase the metal width to reduce the current density ( if u cant increase more thn max. width of metal , then go for higher layers. If u cant go
to higher layers even , then do metal stacking .)

• Reduce the frequency

• Lower the supply voltage

• Keep the wire length short

• Reduce the buffer size in clock lines