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BECE303L

The document discusses the syllabus for a VLSI System Design course and lab. The course covers topics like VLSI design flow, CMOS logic gates, layout design rules, timing analysis, and memory design. The lab focuses on designing and analyzing CMOS circuits and sequential logic using EDA tools.

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KAVIYA DIAS
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60 views3 pages

BECE303L

The document discusses the syllabus for a VLSI System Design course and lab. The course covers topics like VLSI design flow, CMOS logic gates, layout design rules, timing analysis, and memory design. The lab focuses on designing and analyzing CMOS circuits and sequential logic using EDA tools.

Uploaded by

KAVIYA DIAS
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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L T P C

BECE303L VLSI System Design


3 0 0 3
Pre-requisite BECE102L/Digital Systems Design Syllabus version
1.0
Course Objectives :
1. To introduce the basic concepts and techniques of modern integrated circuit design.
2. Describe the fundamental principles underlying digital design using CMOS logic and analyze
the performance characteristics of these digital circuits.
3. Verify that a design meets its functionality, timing constraints, both manually and through the
use of computer-aided design tools.

Course Outcomes :
Students will be able to
1. Analyze the CMOS digital electronics circuits, including logic components and their
interconnect using mathematical methods and circuit analysis models
2. Create models of moderately sized CMOS inverters with specified noise margin and
propagation delay.
3. Apply CMOS technology-specific layout rules in the placement and routing of transistors and
interconnect.
4. Analyse the various logic families and efficient techniques at circuit level for improving power
and speed of combinational and sequential logic.
5. Implement the CMOS digital circuits with the specified timing constraints.
6. Design memories with efficient architectures to improve access times, power
consumption

Module:1 VLSI Design Overview and MOSFET Theory 8 hours


VLSI Design Flow, Design Hierarchy, Concepts of Regularity, Modularity and Locality, VLSI Design
Styles, Design Quality, MOSFET : Device Structure, Electrical behaviour of MOS transistors,
Capacitance- Voltage Characteristics and Non-ideal Effects; Effects of scaling on MOSFETs and
Interconnects.

Module:2 CMOS Logic Gates 8 hours


CMOS Inverter: DC Transfer Characteristics, Static and Dynamic Behaviour, CMOS Basic Gates,
Compound Gates, CMOS Sequential Logic Design – Latches and Flip Flops

Module:3 CMOS Fabrication and Layout 5 hours


CMOS Process Technology N-well, P-well Process, latch up in CMOS technology, Stick Diagram for
Boolean Functions using Euler Theorem, Layout Design Rule

Module:4 CMOS Circuits Performance Analysis 5 hours


Delay Estimation, Logical Effort and Transistor Sizing, Performance Estimation - Static & Dynamic
Power Dissipation.

Module:5 CMOS Logic Families 8 hours


Pass Transistor Logic, Transmission Gates based Logic Design, pseudo NMOS, Cascode Voltage
Switch Logic Dynamic and domino logic, clocked CMOS (C2MOS) logic and np – CMOS logic.

Module:6 Timing Analysis 4 hours


Introduction to Static timing analysis, Setup Time, Hold Time, calculation of critical path, slack, setup
and hold time violations.

Module:7 Semiconductor Memory Design 5 hours


Introduction, Types - Read-Only Memory (ROM) Circuits, Static Read-Write Memory (SRAM) and
Dynamic Read-Write Memory (DRAM) Circuits.

Module:8 Contemporary issues 2 hours


Guest Lecture from Industries and R & D Organizations
Total Lecture Hours: 45 hours
Text Book(s)
1. Neil H.Weste, Harris, A. Banerjee, CMOS VLSI Design, A circuits and System Perspective,
2015, 4th Edition, Pearson Education, Noida, India.
Reference Book
1. Jan M. Rabaey, Anantha Chadrakasan, Borivoje Nikolic, Digital Integrated Circuits: A Design
Perspective Paperback, 2016, 2rd Edition, Pearson Education, India.
2. Sung-Mo Kang, Yusuf Liblebici, Chulwoo Kim, CMOS Digital Integrated Circuits: Analysis and
Design, 2019, Revised 4th Edition, Tata Mc Graw Hill, New Delhi, India.

Mode of Evaluation: Continuous Assessment Test, Digital Assignment, Quiz and Final Assessment
Test
Recommended by Board of Studies 14-05-2022
Approved by Academic Council No. xx Date DD-MM-YYYY
L T P C
BECE303P VLSI System Design Lab
0 0 2 1
Pre-requisite BECE102L/Digital Systems Design Syllabus version
1.0
Course Objectives :
 The objective of this laboratory is to apply the theoretical knowledge and explore various
design style of CMOS Integrated Circuits (IC) design using the latest EDA tools

Course Outcome :
On completion of this lab course the students will be able to
1. Analyze the performance of CMOS Inverter circuits on the basis of their operation and
working.
2. Design the semiconductor memory cell, combinational, sequential and arithmetic circuit
using CMOS design rules.
3. Construct layout of CMOS inverter, universal and basic logic gates.
Indicative Experiments
1 Parameter extraction for basic cell structure (NMOS and PMOS 2 hours
devices).
 Analysis of MOS with width variation, body effect and
estimation of channel length modulation
2 Design and Analysis of CMOS inverter for arbitrary sizing. 4 hours
 Estimation of Power, Delay, Noise Margin.
 Impact of load on performance metrics.

3 Analysis of CMOS inverter for given specification. 2 hours


 Impact of sizing on Power, Delay, Noise Margin
4 Analysis of inverter chains using progressive sizing to improve delay 2 hours
performance.
5 Design and Analysis of Universal gates in static CMOS logic 2 hours
 Effect of input reordering.
6 Design and Analysis of Boolean Expression (Simple Arithmetic Unit) 2 hours
in static CMOS logic.
7 Design and Analysis of Pass transistor and Transmission gate based 4 hours
circuits
8 Design and Analysis of CMOS sequential circuits ( Latches and Flip 4 hours
Flops)
9 Design a CMOS Memory cell (SRAM, DRAM) and verify its 4 hours
operation.
10 Design Layout of CMOS inverter and perform post-layout analysis, 4 hours
DRC, Layout Vs. Schematic, Monte Carlo analysis, Corner analysis
and etc.
Total Laboratory Hours 30 hours
Mode of Assessment: Continuous Assessment and Final Assessment Test
Recommended by Board of Studies 14-05-2022
Approved by Academic Council No. xx Date DD-MM-YYYY

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