UART CONTROLLER AS AMBA APB SLAVE

Roopa M.1,Vani R.M.2,P.V.Hunagund 3

1
Department of Electronics & Communication,Dayananda Sagar College of
Engineering,Bangalore,India,[email protected]
2
University Science Instrumentation Center,Gulbarga University,Gulbarga,India
3
Department of Applied Electronics, Gulbarga University,Gulbarga,India

Abstract -The Advanced Microcontroller Bus (i)To facilitate the right-first-time development of
Architecture (AMBA) specification provides the Embedded Microcontroller Products with one or more
designer a technology independent way to organize the CPUs or signal processors.
different peripherals involved in System on chip design (ii)To be technology-independent and ensure that highly
(SOC) and setup a standard in their interaction and reusable peripheral and system macro cells can be
communication. The Advanced Peripheral Bus (APB) is migrated across a diverse range of IC processes and be
part of the Advanced MicrocontrollerBus appropriate for full-custom, standard cell and gate array
Architecture(AMBA) hierarchy of buses wchich is technologies.
optimized for minimal power consumption and to (iii)To encourage modular system design to improve
reduced interface complexity. The AMBA APB is used processor independence, providing a development road-
to interface many peripherals which are low bandwidth map for advanced cached CPU cores and the
development of peripheral libraries.
and do not require the high performance.
(iv)To minimize the silicon infrastructure required
supporting efficient on-chip and off-chipcommunication
UART Controller as AMBA APB slave is designed to for both operation and manufacturing test.
transmit the data serially. The data can be transmitted The present design of UART slave devices which are
by adding special featurelike endianness. UART compatible with AMBA APB bus protocol can be
controller is designed to transmit or receive the data with plugged in to AMBA bus oriented system, its
two different baud rates. It is also designed to provide functionality and requirement can be used with AMBA
error detection capability to processor and to write one or based systems. The present design is configured with the
two bytes in one cycle, which is configurable by the user. control signals of the AMBA standard specification. The
Different modules are HDL coded, test bench was control of these slave devices can be taken by APB
written and simulated usingModel Simand Synthesis is controller of another AMBA based system when they
performed usingXilinx. are connected to it.

1 Introduction The method adopted for design and verification of all

modules is by using HDL (Hardware Description
The Advanced Microcontroller Bus Architecture Language) for designing the RTL (Register Transfer
(AMBA) is a widely used interconnection standard for Level) code. Synthesis with Simulation is done using
System on Chip (SOC) design [4].In order to support Xilinx and Modelsim
high-speed pipelined data transfers AMBA supports a
rich set of bus signals, making the analysis of AMBA- 2 Overview of Amba Buses
based embedded systems a challenging proposition.
The Advanced Microcontroller Bus Architecture
The AMBA specification [2] has become a de-facto (AMBA) is ARM’s no-cost, open specification, which
standard for the semiconductor industry, it has been defines an on-chip communications
adopted by more than 95% of ARM’s partners and a standardFordesigning high performance Embedded
number of IP providers. This specification has been Microcontrollers. The Three distinct buses are defined
successfully tested in several ASIC designs. Since the within the AMBA specification are :
AMBA interface is processor technology independent, it
helps in enhancing the reusability of Peripheral and
system components across a wide range of applications.

The AMBA specification has been derived to satisfy the

following four key requirements[4].

1
 An AMBA AHB design may contain one or more bus
(i) The Advanced High-performance Bus (AHB) masters typically a system would contain at least the
processor and test interface. However, it would also be
common for a Direct Memory Access (DMA) or Digital
(ii) The Advanced System Bus (ASB)
Signal Processor (DSP) to be included as bus masters.
(iii) The Advanced Peripheral Bus (APB).
The external memory interface, APB Bridge and any
internal memory are the most common AHB slaves. Any
other peripheral in the system could also be included as
an AHB slave. However, low-bandwidth peripherals
typically reside on the APB.

2. Advanced System Bus (ASB)

The AMBA ASB is for high-performance modules. It is
an alternative system bus suitable for use where high-
performances features of AHB are not required.ASB also
supports the efficient connection of processors, on-
chipmemories and off-chip external memory interfaces
with low-power peripheral macro cell functions.

Features of ASB:
Figure 1. AMBA based Simple Microcontroller  Burst transfers
 Pipelined transfer operation
1.Advanced high-performance bus (AHB)  Multiple bus masters.

AHB is a new generation of AMBA bus, which addresses

the requirements of high-performance synthesizable 3. Advanced peripheral bus (APB)
design. In this bus a high-performance system bus that
supports multiple bus masters and provides high- The Advanced Peripheral Bus (APB) is part of the
bandwidth operation. Advanced Microcontroller Bus Architecture (AMBA)
hierarchy [4] of buses and is optimized for minimal
AMBA AHB [4] implements the features required for power consumption and reduced interface complexity.
high-performance, high clock frequency systems
including: The AMBA APB should be used to interface to any
peripherals which are low-bandwidth and do not require
 High performance the high performance of a pipelined bus interface.
 Pipelined operation
 Multiple bus masters The latest revision of the APB ensures that all signal
 Burst transfers transitions are only related to the rising edge of the clock.
 Single-cycle bus master handover This improvement means the APB peripherals can be
 Non-tri state implementation integrated easily into any design flow. Features of APB:
 Wider data bus configurations (64/128bits).
 Low power
Bridging between this higher level of bus and the current  Latched address and control
ASB/APB can be done efficiently to ensure that any  Simple interface
existing designs can be easily integrated.  Suitable for many peripherals

These changes to the APB also make it simpler to

interface it to the new Advanced High-performance Bus
(AHB).

2
 3 OPERATION OF UART CONTROLLER

The APB - UART is a master/slave that enables serial

communication between other UART that is externally
connected. Device states are read by the APB using
status registers that reflect the completion of UART data
transfers. Controller also supports the interrupt pin for
indicating the transaction completion or any error in the
controller. Standard UART protocol consists of start/stop
indicators, data, and parity information. The serial bit
stream uses the following sequence: Start bit, Data bit,
parity bit, stop bit [3].

A bit called the Start Bit is added to the beginning of each

word that is to be transmitted. The Start Bit indicates the
start of the data transmission and it alerts the receiver that Figure 2: UART Signals
a word of data is about to be sent. Upon reception of start
bit the clock in the receiver goes into synchronization with
the clock in the receiver. The individual bits of the word of
data are sent after the start bit. Least Significant Bit (LSB)
is sent first. The transmitter does not know when the
receiver has read at the value of the bit. The transmitter
begins transmitting the next bit of the word on next clock
edge. Parity bit is to be added when the entire data word
has been sent. This bit can be used to detect errors at the
receiver side. Then one or two Stop Bits is sent by the
transmitter to indicate the end of the valid data bits.

Figure 3: UART Block Diagram

Block diagram of the UART controller mainly consist 6

sections.
APB Slave: This section is responsible for converting
the APB master signals to signals which is understood by
UART device.
Register Bank: This section consists of different
registers which are used to configure UART.
Baud Rate Generator: This section generates clock
signals which are required for TX and RX FIFO.
Transceiver Block: This section consists of
Figure 1: UART IO Diagram Transmitter and Receiver blocks which are responsible
for transmitting and receiving the data.
Interrupt Handler: It manages the different interrupts and it stores the received data to be read by APB.
and sends notification to the APB master.

FIFO: There two FIFO in UART Controller. The

Transmitter FIFO is of 32X8 and it is used to store the
data to be transmitted. The Receiver FIFO is of 32X11

3
 The sequence of operations carried out during
reception of data from external device. External device
initiates the process by sending the data to input filter.
UART is configured and valid data from input filter is
shifted to control logic. Errors are checked and
corresponding error interrupts are generated and
erroneous data is stored in receiver FIFO. If there are
no errors, valid data is stored in FIFO. Data from
receiver FIFO is stored into register hold and CPU
reads the data from register hold.

4. Simulation Results

Figure 4: Block Diagram of APB Slave

The above mentioned are the signals from APB slave to

Register Bank.
cs (Chip Select): This signal is used to select the
Register Bank.
wrn (Write/Readn): This is signal is used to write or
read the data from Register Bank. When this signal is
high the data is transferred from APB slave to Register
Bank. When this signal goes low it enables reading
operation, i.e., the data will be read from Register Bank.
addr[3:0]: This bus is used select the different registers
from Register Bank.
wdata[7:0]: This bus is used to write the data into Figure 5: Simulation waveform of APB slave
different registers and FIFO‟s.
rdata[10:0]: This bus is used to read the data from
the RHOLD register of Register Bank. Figure 5 shows how APB signals are asserted to
perform Data write & read through the APB slave to
The sequence of operations Carried out during the UART Controller. In order to write the Data,
transmission of the data to external device. The CPU pwrite must be high. The data will be written into the
initiates the process by reading line status register. It address specified by the addr, obtained from paddr.
checks for UART busy state and if it is not busy, then With presetn low, the slave will not function. The
different registers are configured and data is written outputs cs (chip select),addr (16-bit) and wrn(
onto transmitter FIFO, then to transmitter engine. Data write/read bar) are given to the register bank for
is transmitted to external device and transmission done writing or reading operation respectively.
interrupt is generated.

4
 Figure 8: Transmitter engine simulation.
Figure 6: Simulation waveform of UART

Figure 6 illustrates the sequence of operations

carried out during transmission and reception. Figure 8 shows the simulation waveform of transmitter
engine. Under the transmitter FIFO FIFO_EMPTY)
not empty and transmitter enabled (TX_EN) condition,
the FIFO read (REN) will be enabled. The data (rdata)
will be read from the FIFO and transmitted through the
TX pin.

Figure 7 : Register bank simulation.

Figure 7: shows how APB Slave signals are asserted

to write and read from the Register Bank. When CS
(Chip Select) and wrn (write/read bar) is high, the Figure 9: Receiver engine simulation.
wdata from APB slave will be written into the
corresponding register based on address given.
Figure 9 shows simulation waveform of Receiver
Engine. The clock (clk) signal is a baud clock which is
responsible to clock the Receiver Engine. When
receiver is enabled i.e., RX_EN is high the data on the
RX pin will be sampled. The valid bit 0 (VALID0) and
valid bit 1 (VALID1) are the corresponding to the data
inputs available at the RX pin and it will be store in
receiver FIFO (WDATA) through shift register.

5
 5 Conclusions References

A user configurable UART controller has been [1] Flynn, D. Adv. RISC Machines Ltd.,
designed. APB bus interface is used for Cambridge, “AMBA:enabling reusable on-chip
communication with processor in this UART designs”, IEEE Micro, Publication Date:
controller. The registers of the UART are configurable. Jul/Aug 1997.
Any AMBA based SOC with ARM processor can use [2] NikilDutt, Kaustav Banerjee, Luca Benini,
this UART controller for serial communication. KanishkaLahiri, SudeepPasricha, "Tutorial 5:
SoC Communication Architectures:
A UART Controller as AMBA APB slave is designed Technology, Current Practice, Research, and
to transmit the data serially. The data can be Trends," vlsid, pp.8, 20th International
transmitted by adding special feature like endianness. Conference on VLSI Design held jointly with
Using this UART controller the serial data can be 6th International Conference on Embedded
received with the special feature endianness. Systems (VLSID'07), 2007
[3] “Using formal techniques to Debug the AMBA
System-on-Chip Bus Protocol” Proceedings of
UART controller is designed to transmit or receive the
data with two different baud rates. It is also designed to the Design, Automation and Test in Europe
provide error detection capability to processor; this is Conference and Exhibition, 2003.
designed to write one or two bytes in one cycle, which is [4] AMBA Specification (Rev 2.0).
configurable by the user.