Registers and Counters Registers and Counters Sea SO = Circuits that include flip-flops are usually classified by the function they perform = Registers = Counters = Register is a up of flip-flops. = Each flip-flop is capable of storing one bit of information. = An n-bit register consists of a group of n flip-flops. = Register is a group of binary cells suitable for holding binary information. = A counter is essentially a register that goes through a predetermined sequence of states.Registers SS SES SS SS SIS SIO = Clock= 0 to 1: Input to Dp A information is transferred . to output: |-> A y = Clock = 0 and 1; Output n = A unchanged ke = Clear = 0; Clearing the register to all 0’s prior to cansinie a its clocked operation. = Clear : asynchronous input. Clock Car Fig. 6-1 4-Bit Register Register with Parallel Load ees = Seo » Synchronous digital systems have a master clock generator that supplies a continuous train of clock pulses. = The transfer of new information into a register is referred to as loading the register. = If all the bits of the register are loaded simultaneously with a common clock pulse, we Say that the loading is done in parallel. = The load input determines whether the next pulse will accept new information or leave the information in the register intactRegister with Parallel Load es ee es = Load =1; the | inputs at eae] [ are transferred into the 2) register h —, 2B al “ = Load = 0 ; maintain the = content of the register oS 1 A DP Ay = Because the D flip-flop i fat does not have a “no [ change” t t Le J > As UYJUU|U the Cock Fig 62 4-BitRopster with Parallel Load Shift Registers SS = Capable of shifting its binary information in One or both directions Serial__SI_|D D iD D SO Serial input output Fig 63 4-Bit Shift Register The simplest shift registerShift Registers: Serial Transfer nae (@) Blok diagram Serial-Transfer Example Table 6~1: Serial-Transfer Example Timing pulse Shift register A Shift register Serial output of 8 Initial value 1011 0010 After Ts xs, éo1 0 After Te r110 1100 1 After Ts oT11 0110 0 After Ta 1011 1014 0 Als transferred into 8, while the content of A remains unchangedSerial Addition = For storing sum | — QQperation Shit SY ~ The A register —>augend ek Ty steer — The 6 register —>addend sl] - Cary ->0 a <-] — OThe SO of A and B provide a a so pal of significant bits for the iopet TF sat epteras O Output Q gives the input fia cany at z OThe shift-right control c enables both registers and the cary flip-flop. | OThe sum bit from S enters —4 ) the leftmost flip-flop of A QParallel adder needs more circuits than serial adder Fig 6 Srial Adder State Table for Serial Adder Tablec2 _-=Present value of carry State Tole for Sl er eee eee —- (Next FlipFlop. Inpats State Output Inputs Output carrySecond form of Serial Adder stint s control Shift register A t s CLK >} | serial sr so=y 7 | Clear Fig. 66 Second formof Serial Adder Universal Shift Register as as eS sos If the register has both shifts and parallel load capabilities. it is referred to as a universal shift register. = Acclear control to clear the register to 0. = Acclock input to synchronize the operations. = A shift-right control to enable the shift right operation and the serial input and output lines associated with the shift right. = A shift-left control to enable the shift left operation and the serial input and output lines associated with the shift left. = A parallel-load control to enable a parallel transfer and the Nn input lines associated with the parallel transfer. = 1 parallel output lines = Acontrol state that leaves the information in the register unchanged in the presence of the clock.Universal Shift Register —aow ewes eoss ko om af) a) ed) al) as, 80-2 0, 0 iNNo change cw t a in QS), So-> 0, 1 + Shift right, The serial Input for shift-right is transferred to the A3. OSs, So-> 1, 0 5 Shift left, The serial input for shift-left is transferred to the AO. OS;, Se-> 1, 1 ‘Parallel load ont ‘ei Fay “ee I i | | Se Pag Fig67 sino it ai Universal Shift Register ES ES SS SS II III = Shift register are often used to interface digital systems. Suppose it is necessary to transmit an n-bit quantity between two points. = twill be expensive to use n lines to transmit the n bits in parallel. = _Itis more economical to use a single line and transmit the information serially, one bit at a time. = The transmitter accepts the n-bit data in parallel into a shift register and then transmits the data serially along the common line. = The receiver accapts the data serially into a shift register. = When all n-bits are received, they can be taken from the outouts of the register in parallel. = The transmitter: a paralle!-to-serial conversion of data, the receiver: a serial-to-parallel conversion.Counters = Aregister that goes through a prescribed sequence of states upon the application of input pulses is called a counter. The input pulses may be clock pulses or they may originated from some external source and may occur at a fixed interval of time or at random. = A counter that follows the binary number sequence is called a binary counter. = An n-bit binary counter consists of n flip-flops and can count in binary from 0 through 2%n -1. Counters = Counters in two categories = Ripple counters = Synchronous counters = Ripple counters The flip-flop output transition serves as a source for triggering other flip-flops. The C input some or all flip-flops are triggered not by the common clock pulses, but rather by the transition that occurs in other flip-flop outputs. = Synchronous counters = The C inputs of all flio-flops receive the common clock .Binary Ripple Counters count bey | oust — Series connection of e — Complementing flip-flops “ Ee How about for Cont-down ? + t al ~Positive edge triggered - . i ,, 7Of connected to comp. out Fig 68 4-Rit Binary Rigple Counter Count Sequence for a Binary Ripple Counter os eS SS eo Count sequence Conditions for ‘Aa As Ar As Complementing 0000 ‘Complement Aa 0 0/0\1 ‘Complement Aa ‘Aa will go from 1 to 0 and oo Complement Ao complement A: oo YY Complement A> Aawill go from 1 to 0 and complement A: ; Arwill go from 1 to 0 and 0100 Complement As Awl Soe oroT — ‘Aa will go from 1 to 0 and 0110 Complement Aa complement Ar ort ‘Complement Aa and so on...BCD Ripple Counter @-©-@-©-@ rhe 6-@-6-e-6© |—TTt Fg 69 Sute Diagram of Decimal BCD-Counter BCD Ripple Counter es gs Ss SS st 1. Qt is complemented on the negative edge of every count pulse. 2. Q2 is complemented if Q8=0 and Q1 goes from 1 to 0. Q2 is cleared if Q8=1 and Q1 goes from 1 to 0. 3. Q4_ is complemented when Q2 goes from 1 to 0. 4. Q8 is complemented when Q4Q2=11 and Q1 goes from 1 to 0. Q8 is cleared if either Q4 or Q2 is 0 and Qi goes from 1 to 0Ring Counter ES SESS OS SII = For generating timing WA signal that control the sequence of operations = Acircular shift register with only one flip-flop being set at any particular time: all others are cleared, The single bit is shifted te from one flip-flop to the other. n = 2°n timing signals need 2°n flip-flops coe me Fie 617 Generation of Timing Signals Johnson Counter = Acircular shift register with the complement output of the last flip- flop connected to the input of the first flip- floo. = Ak-bit switch-iail ring counter will go through ()Foursag wih ng counter a sequence of 2k states. = A Johnson counter is a Sweet _Bitepenes an pers k-bit switch-tall ring SS TE counter with 2k 2 10 0 0 AB decoding gates to i tito & provide outouts for 2k sofia Se timing signals. $ eats ao bo ood ce (©) Count equence and required dssoding