DLP 650 Te
DLP 650 Te
DLP 650 Te
1 Features 3 Description
• 0.65-inch diagonal micromirror array The DLP650TE digital micromirror device (DMD) is
– 4-K UHD (3840 × 2160) display resolution a digitally controlled micro-electromechanical system
– 7.6-µm micromirror pitch (MEMS) spatial light modulator (SLM) that enables
– ±12° micromirror tilt (relative to flat surface) bright 4-K UHD display systems. The DLP® Products
– Corner illumination 0.65” 4-K UHD chipset is composed of the DMD,
• High speed serial interface (HSSI) input data bus DLPC7540 display controller, and DLPA100 Power
• Supports 4K UHD at 60 Hz and full HD at 240 Hz and motor driver. The compact physical size of the
• Laser-phosphor, LED, RGB laser, and lamp chipset provides a complete system solution that
operation supported by DLPC7540 display enables small form factor 4-K UHD displays.
controller, DLPA100 power management, and The DMD ecosystem includes established resources
motor driver IC to help the user accelerate the design cycle, which
2 Applications include production ready optical modules, optical
module manufacturers, and design houses.
• Laser TVs
• Smart Projectors Visit the Getting Started with TI DLP display
• Enterprise Projectors technology page to learn more about how to start
designing with the DMD.
(1)
Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)
DLP650TE FYP(149) 32.2 mm × 22.3 mm
LS Interface
12 V
1.8 V
VREG
DMD VDD En
Simplified Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP650TE
DLPS186A – MARCH 2021 – REVISED MAY 2022 www.ti.com
Table of Contents
1 Features............................................................................1 8 Application and Implementation.................................. 27
2 Applications..................................................................... 1 8.1 Application Information............................................. 27
3 Description.......................................................................1 8.2 Typical Application.................................................... 27
4 Revision History.............................................................. 2 8.3 Temperature Sensor Diode....................................... 30
5 Pin Configuration and Functions...................................3 9 Power Supply Recommendations................................32
6 Specifications.................................................................. 6 9.1 Power Supply Sequence Requirements................... 32
6.1 Absolute Maximum Ratings........................................ 6 9.2 DMD Power Supply Power-Up Procedure................ 32
6.2 Storage Conditions..................................................... 6 9.3 DMD Power Supply Power-Down Procedure........... 32
6.3 ESD Ratings............................................................... 7 10 Layout...........................................................................34
6.4 Recommended Operating Conditions.........................7 10.1 Layout Guidelines................................................... 34
6.5 Thermal Information....................................................9 10.2 Impedance Requirements.......................................34
6.6 Electrical Characteristics...........................................10 10.3 Layers..................................................................... 34
6.7 Switching Characteristics.......................................... 11 10.4 Trace Width, Spacing..............................................35
6.8 Timing Requirements................................................ 11 10.5 Power......................................................................35
6.9 System Mounting Interface Loads............................ 15 10.6 Trace Length Matching Recommendations............ 35
6.10 Micromirror Array Physical Characteristics............. 16 11 Device and Documentation Support..........................37
6.11 Micromirror Array Optical Characteristics............... 17 11.1 Third-Party Products Disclaimer............................. 37
6.12 Window Characteristics.......................................... 19 11.2 Device Support........................................................37
6.13 Chipset Component Usage Specification............... 19 11.3 Documentation Support.......................................... 37
7 Detailed Description......................................................19 11.4 Receiving Notification of Documentation Updates.. 38
7.1 Overview................................................................... 19 11.5 Support Resources................................................. 38
7.2 Functional Block Diagram......................................... 20 11.6 Trademarks............................................................. 38
7.3 Feature Description...................................................21 11.7 Electrostatic Discharge Caution.............................. 38
7.4 Device Functional Modes..........................................21 11.8 Glossary.................................................................. 38
7.5 Optical Interface and System Image Quality 12 Mechanical, Packaging, and Orderable
Considerations............................................................ 21 Information.................................................................... 39
7.6 Micromirror Array Temperature Calculation.............. 22 12.1 Package Option Addendum.................................... 40
7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
6 Specifications
6.1 Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those
indicated under Recommended Operating Conditions. Exposure above or below the Recommended Operating Conditions for
extended periods may affect device reliability.
Parameter Name Description MIN MAX UNIT
Supply Voltage
Supply voltage for LVCMOS core logic and LVCMOS low speed interface
VDD –0.5 2.3 V
(LSIF) (1)
VDDA Supply voltage for high speed serial interface (HSSI) receivers (1) –0.3 2.2 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode (1) (2) –0.5 11 V
VBIAS Supply voltage for micromirror electrode (1) –0.5 17 V
VRESET Supply voltage for micromirror electrode (1) –13 0.5 V
| VDDA – VDD | Supply voltage delta (absolute value) (3) 0.3 V
| VBIAS – VOFFSET | Supply voltage delta (absolute value) (4) 11 V
| VBIAS – VRESET | Supply voltage delta (absolute value) (5) 30 V
Input Voltage
Input voltage for other inputs – LSIF and LVCMOS (1) –0.5 2.45 V
Input voltage for other inputs – HSSI (1) (6) –0.2 VDDA V
Low speed interface (LSIF)
fCLOCK LSIF clock frequency (LS_CLK) 130 MHz
| VID | LSIF differential input voltage magnitude (6) 810 mV
IID LSIF differential input current(7) 10 mA
High speed serial interface (HSSI)
fCLOCK HSSI clock frequency (DCLK) 1.65 GHz
| VID | HSSI differential input voltage magnitude Data Lane (6) 700 mV
| VID | HSSI differential input voltage magnitude Clock Lane (6) 700 mV
Environmental
TARRAY Temperature, operating(8) 0 90 °C
TARRAY Temperature, non-operating(8) –40 90 °C
TDP Dew point temperature, operating and non-operating (non-condensing) 81 ºC
(1) All voltage values are with respect to the ground terminals (VSS). The following required power supplies must be connected for proper
DMD operation: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(2) VOFFSET supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable absolute voltage difference between VDDA and VDD may result in excessive current draw.
(4) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. LVDS and HSSI
differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(7) Differential inputs must not exceed the specified limit or damage may result to the internal termination resistors. Specification applies to
both the High speed serial interface (HSSI) and the low speed interface (LSI).
(8) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point
(TP1) shown in Figure 7-1 and the package thermal resistances using the Micromirror Array Temperature Calculation.
(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.
(2) All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are
required to operate the DMD.
(3) All voltage values are with respect to the VSS ground pins.
(4) VOFFSET supply transients must fall within specified max voltages.
(5) To prevent excess current, the supply voltage delta | VDDA – VDD | must be less than specified limit.
(6) To prevent excess current, the supply voltage delta | VBIAS – VOFFSET | must be less than specified limit.
(7) LVCMOS input pin is DMD_DEN_ARSTZ.
(8) See the low speed interface (LSIF) timing requirements in Timing Requirements.
(9) See the high speed serial interface (HSSI) timing requirements in Timing Requirements.
(10) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will
reduce device lifetime.
(11) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point
(TP1) shown in Figure 7-1 and the package thermal resistances using the Micromirror Array Temperature Calculation.
(12) Per Figure 6-1, the maximum operational array temperature should be de-rated based on the micromirror landed duty cycle that the
DMD experiences in the end application. Refer to Micromirror Landed Duty Cycle for a definition of micromirror landed duty cycle.
(13) Long-term is defined as the usable life of the device.
(14) Short-term is the total cumulative time over the useful life of the device.
(15) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(16) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.
(17) The active area of the DMD is surrounded by an aperture on the inside of the DMD window surface that masks structures of the
DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating
the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD.
The illumination optical system should be designed to minimize light flux incident outside the active array. Depending on the
particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may
cause system performance degradation.
(18) Applies to the region in red in Figure 6-2.
70
60
50
40
30
0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
100/0 95/5 90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45 50/50
Micromirror Landed Duty Cycle
10.615 mm
Array Window
Aperture
Window
Window Aperture
Window
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the DMD within the temperature range specified in the Recommend Operating Conditions. The total heat load on the DMD
is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the
window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling
outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
(1) All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are
required to operate the DMD.
(2) All voltage values are with respect to the ground pins (VSS).
(3) To prevent excess current, the supply voltage delta | VDDA – VDD | must be less than specified limit.
(4) To prevent excess current, the supply voltage delta | VBIAS – VOFFSET | must be less than specified limit.
(5) Supply power dissipation based on 3 global resets in 200 µs.
(6) LVCMOS input specifications are for pin DMD_DEN_ARSTZ.
(7) LVCMOS output specification is for pins LS_RDATA_A and LS_RDATA_B.
(8) Refer to Figure 6-12 (1e-12 BER).
(9) Defined in Recommended Operation Conditions.
LS_CLK_P
1 0 1 0 1 0 1 0 1 0
LS_CLK_N
1 period
LS_WDATA_P
Stop (1) Start (0)
LS_WDATA_N
tPD
LS_RDATA_A
BIST_A Acknowledge
(1) See Figure 6-9 and Figure 6-10 LVCMOS Rise, Fall Time SLew Rate Figures. Specification is for DMD_DEN_ARSTZ pin (LVCMOS).
(2) See Figure 6-6 for rise and fall time for LSIF.
(3) See Figure 6-5 for pulse duration high and low time for LSIF.
(4) See Figure 6-5 for setup and hold time for LSIF.
(5) See Figure 6-11 for rise and fall time for HSSI.
(6) See Figure 6-13 for pulse duration high and low and cycle time for HSSI.
1.255 V
VLVDS(max)
VCM VID
VLVDS(min)
0.575 V
1
VLVDS :max ; = VCM :max ; + , × VID:max ; ,
2
(1)
1
VLVDS :min; = VCM :min; F , × VID:max ; ,
2
(2)
tW(L)| tW(H)|
LS_CLK_P
50%
LS_CLK_N
tSU| tH|
LS_WDATA_P
50%
LS_WDATA_N
tWINDOW|
40
30
20
10
0
tr tf
+ (VIP + VIN)
VCM =
± 2 LS_CLK_P,
LS_WDATA_P
VID
LS_CLK_N,
LS_WDATA_N LVDS
Receiver
LS_CLK_P
LS_WDATA_P
ESD Internal
Termination
(ZIN)
LS_CLK_N LVDS
LS_WDATA_N Receiver
ESD
'VT
VT±
VIL
DMD_DEN_ARTZ
Time
DMD_DEN_ARSTZ
100
VDD Voltage (%)
80
VIL(AC)
20
tR tF
Time
tf
VHSSI(max)
VCM VID
VHSSI(min)
tr
1
VHSSI :max ; = VCM :max ; + , × VID:max ; ,
2
(3)
1
VHS SI:min ; = VCM :min ; F , × VID:max ; ,
2
(4)
A2
A1
0V
-A1
-A2
X1 1-X1
X2 1-X2
0 1 UI
Figure 6-12. HSSI Eye Characteristics
tC|
tW(L)| tW(H)|
DCLK_?P
50%
DCLK_?N
(1) The load should be applied uniformly in the corresponding areas shown in Figure 6-14.
M±4
M±3
M±2
M±1
Incident
Illumination
0
1
2
3
Light Path
0
1
2
3
N±4
N±3
N±2
N±1
Off-State
MxP
Light Path
P P
Pond Of Micromirrors (POM) omitted for clarity.
Gray 10 Screen(10)
Bright pixes(s) in POM(11) 1 micromirrors
Image
performance(8)
Dark pixel(s) in active area(12) White Screen 4 micromirrors
Adjacent pixels(13) Any Screen 0 micromirrors
Unstable pixel(s) in active area(14) Any Screen 0 micromirrors
(1) Measured relative to the plane formed by the overall micromirror array.
(2) Represents the landed tilt angle variation relative to the nominal landed tilt angle.
(3) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(4) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations or system contrast variations.
(5) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State
direction. A binary value of 0 results in a micromirror landing in the OFF State direction, see Figure 6-16.
(6) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.
(7) The minimum time between successive transitions of a micromirror.
(8) Conditions of Acceptance: All DMD image performance returns will be evaluated using the following projected image test conditions:
Test set degamma shall be linear
Test set brightness and contrast shall be set to nominal
The diagonal size of the projected image shall be a minimum of 60 inches
The projection screen shall be 1x gain
The projected image shall be inspected from an 8 foot minimum viewing distance
The image shall be in focus during all image performance tests
(9) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter that the surrounding pixels
(10) Gray 10 screen definition: All areas of the screen are colored with the following settings:
Red = 10/255
Green = 10/255
Blue = 10/255
(11) POM definition: Rectangular border of off-state mirror surrounding the active area.
(12) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels.
(13) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster.
(14) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with the parameters loaded into memory. The
unstable pixel appears to be flickering asynchronously with the image.
Incident Light
Direction
Off-State Light
Direction
Landed Corner
Rotation Axis
On-State Off-State
Tilted Mirror Tilted Mirror
A Flat-State
Mirror
Landed Corner
A
Landed Corner
Rotation Axis
Landed Corner
View A-A
Note
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
7 Detailed Description
7.1 Overview
The DMD is a 0.65-inch diagonal spatial light modulator that consists of an array of highly reflective
aluminum micromirrors. The DMD is an electrical input, optical output micro-optical-electrical-mechanical system
(MOEMS). The fast switching speed of the DMD micromirrors combined with advanced DLP image processing
algorithms enables each micromirror to display four distinct pixels on the screen during every frame, resulting
in a full 3840 × 2160 pixel image being displayed. The electrical interface is low voltage differential signaling
(LVDS). The DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is organized in a
grid of M memory cell columns by N memory cell rows. Refer to Section 7.2. The positive or negative deflection
angle of the micromirrors can be individually controlled by changing the address voltage of underlying CMOS
addressing circuitry and micromirror reset signals (MBRST).
The DLP 0.65” 4-K UHD chipset is comprised of the DLP650TE DMD, DLPC7540 display controller, the
DLPA100 power management and motor driver. To ensure reliable operation, the DLP650TE DMD must always
be used with the DLP display controller and the power and motor specified in the chipset.
VOFFSET
VRESET
LOADB
SCTRL
VBIAS
VREF
DATA
DCLK
VDD
TRC
VSS
Channel A Interface
Bit Lines
(0,0)
Word
Voltage Voltages Micromirror Lines
Row
Generators Array
(M-1,N-1)
Bit Lines
Channel B Interface
DRC_STROBE
VRESET
VBIAS
VOFFSET
VDD
VREF
VSS
DRC_OEZ
DRC_BUS
SAC_BUS
SAC_CLK
RESERVED
Array
TP1
4.5
16.1 TP1
Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from
measurement points on the outside of the package, the package thermal resistance, the electrical power, and
the illumination heat load. The relationship between array temperature and the reference ceramic temperature
(thermal test TP1 in Figure 7-1) is provided by the following equations:
where
• TARRAY = Computed array temperature (°C)
• TCERAMIC = Measured ceramic temperature (°C) (TP1 location)
• RARRAY-TO-CERAMIC = Thermal resistance of package specified in Section 6.5 from array to ceramic TP1 (°C/
Watt)
• QARRAY = Total DMD power on the array (W) (electrical + absorbed)
• QELECTRICAL = Nominal electrical power (W)
• All points below this curve represent higher useful life (and the further away from the curve, the higher the
useful life).
In practice, this curve specifies the maximum operating DMD temperature for a given long-term average landed
duty cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
operates under a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the pixel
operates under a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in Table 7-1.
Table 7-1. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE LANDED DUTY CYCLE
0% 0/100
10% 10/90
20% 20/80
30% 30/70
40% 40/60
50% 50/50
60% 60/40
70% 70/30
80% 80/20
90% 90/10
100% 100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given
primary must be displayed in order to achieve the desired white point.
Use this information to calculate the landed duty cycle of a given pixel during a given time period:
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) +
(Blue_Cycle_% × Blue_Scale_Value)
where
• Red_Cycle_%, represents the percentage of the frame time that red is displayed to achieve the desired white
point
• Green_Cycle_% represents the percentage of the frame time that green is displayed to achieve the desired
white point
• Blue_Cycle_%, represents the percentage of the frame time that blue is displayed to achieve the desired
white point
For example, assume that the red, green, and blue color cycle times are 30%, 50%, and 20% respectively (in
order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, blue
color intensities are shown in Table 7-2 and Table 7-3.
0% 0% 0% 0/100
100% 0% 0% 30/70
0% 100% 0% 50/50
0% 0% 100% 20/80
0% 12% 0% 6/94
0% 0% 35% 7/93
60% 0% 0% 18/82
0% 100% 100% 70/30
100% 0% 100% 50/50
100% 100% 0% 80/20
0% 12% 35% 13/87
60% 0% 35% 25/75
60% 12% 0% 24/76
100% 100% 100% 100/0
The last factor to account for in estimating the landed duty cycle is any applied image processing. Within the
DLPC7540 controller, the gamma function affects the landed duty cycle.
Gamma is a power function of the form Output_Level = A × Input_LevelGamma, where A is a scaling factor that is
typically set to 1.
In the DLPC7540 controller, gamma is applied to the incoming image data on a pixel-by-pixel basis. A typical
gamma factor is 2.2, which transforms the incoming data as shown in Figure 7-2.
100
90
80
Output Level (%) 70 Gamma = 2.2
60
50
40
30
20
10
0
0 10 20 30 40 50 60 70 80 90 100
Input Level (%) D002
From Figure 7-2, if the gray scale value of a given input pixel is 40% (before gamma is applied), then gray scale
value is 13% after gamma is applied. Therefore, it can be seen that since gamma has a direct impact displayed
gray scale level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.
Consideration must also be given to any image processing which occurs before the DLPC7540 controllers.
12V
Voltage Reg.
LMR33630C 3.3V
TPS65145
12 V DLPA100
1.21V
(Controller 3.3V
Voltages) 5V
}
DLPC7540
(2)
XPR Drive Data Drive 4-Way XPR
USB 2.0 Electronics Actuator
USB2.0 GPIO
(2)
Mux
DB Drive Data Dynamic Black
USB Actuators (2X)
(2)
DLP Chipset Components Camera
TI Components
12V DLPC7540
Voltage Reg. Ballast
Flash
12 V DLPA100
PMIC and
Motor
1.21V
3.3V
5V
} DLPC7540
1.15V FANS(3x)
1.21V
1.8V CTRL Comparator
3.3V
CW_INDEX1
Vref
HDMI
Front End IC I2C
3840x2160 2-Port HSSI
VbyOneTM LS Interface
@ 60Hz
SPI VOFFSET
TPS65145
DMD VRESET DLP650TE
3.3V
3D L/R DLPC7540 Voltages VBIAS .65" UHD
Controller S451 HSSI
GPIO
1.8V DMD
12V LMR33630C
Tilt (& Roll)
Sensor Temp
3.3V
I2 C TMP411 (2)
IR Rx (2)
USB2.0 OTG
(2) XPR Drive Data Drive 4-Way XPR
Electronics Actuator
USB 2.0
USB2.0 GPIO
(2) DB Drive Data Dynamic Black
Mux
Actuators (2X)
USB
(2)
Camera
DLP Chipset Components
TI Components
0.75
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
Normalized Laser Power norm
Figure 8-3. Normalized Light Output vs Normalized Laser Power for Laser Phosphor Illumination
3.3V
R1 R2 TMP411 DLP650TE
SCL VCC
To DLPC7540 Controller
R3 R5 TEMP_P
SDA D+
ALERT
C1
THERM
R4 R6
GND D-
TEMP_N
GND
CAUTION
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to any of the prescribed power-up and power-down requirements may
affect device reliability. See the DMD power supply sequencing requirements in Figure 9-1.
VBIAS, VDD, VOFFSET, and VRESET power supplies must be coordinated during power-up and power-
down operations. Failure to meet any of the below requirements results in a significant reduction in
the DMD reliability and lifetime. Common ground VSS must also be connected.
Note A Note J
...
VDD and VDDA
Note H VSS
tDELAY3
...
Note B
VOFFSET
Note D V < Specification VSS
tDELAY1
...
VBIAS
VSS
Note C
VRESET V < Specification
Note E VSS
...
Note F
tDELAY2
Note G
...
DMD_EN_ARSTZ
VSS
Time
A. See the Pin Functions table.
B. To prevent excess current, the supply voltage difference |VBIAS – VOFFSET| must be less than the specified limit in Section 6.4.
C. To prevent excess current, the supply difference |VBIAS – VRESET| must be less than the specified limit in Section 6.4.
D. VBIAS must power up after VOFFSET has powered up, per tDELAY1 specification in Section 9.1.
E. VRESET, VOFFSET and VBIAS ramps must start after VDD and VDDA are powered up and stable.
F. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates
DMD_EN_ARSTZ and disables VBIAS, VRESET and VOFFSET.
G. Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware
DMD_EN_ARSTZ goes low.
H. VDD must remain powered on and stable until after VOFFSET, VBIAS, and VRESET are powered off, per tDELAY3 specification in Section 9.1.
I. To prevent excess current, the supply voltage delta |VDDA – VDD| must be less than specified limit in Section 6.4.
J. Not to scale. Details omitted for clarity.
10 Layout
10.1 Layout Guidelines
The DLP650TE DMD is part of a chipset that is controlled by the DLPC7540 display controller in conjunction with
theTPS65145 PMIC and the DLPA100 power and motor controller. These guidelines are targeted at designing
a PCB board with the DLP650TE DMD. The DMD board is a high-speed multi-layer PCB, with primarily high-
speed digital logic including double data rate 3.2 Gbps and 250 Mbps differential data buses run to the DMD. TI
recommends that full or mini power planes are used for VOFFSET, VRESET, and VBIAS. Solid planes are required
for ground (VSS). The target impedance for the PCB is 50 Ω ±10% with exceptions listed in Table 10-1. TI
recommends a 10 layer stack-up as described in Table 10-2. TI recommends manufacturing the PCB with a high
quality FR-4 material.
10.2 Impedance Requirements
TI recommends a target impedance for the PCB of 50 Ω ±10% for all signals. The exceptions are listed in Table
10-1.
Table 10-1. Special Impedance Requirements
SIGNAL TYPE SIGNAL NAME IMPEDANCE (Ω)
DMD_HSSI0_N_(0…7),
DMD_HSSI0_P_(0…7),
DMD_HSSI1_N_(0…7),
DMD_HSSI1_P_(0…7), 100-Ω differential (50-Ω single
DMD High Speed Data Signals
DMD_HSSI0_CLK_N, ended)
DMD_HSSI0_CLK_P,
DMD_HSSI1_CLK_N,
DMD_HSSI1_CLK_P
DMD_LS0_WDATA_N,
DMD Low Speed Interface DMD_LS0_WDATA_P, 100-Ω differential (50-Ω single
Signals DMD_LS0_CLK_N, ended)
DMD_LS0_CLK_P
10.3 Layers
Table 10-2 shows the layer stack-up and copper weight for each layer.
Table 10-2. Layer Stack-Up
LAYER
LAYER NAME COPPER WT. (oz.) COMMENTS
NO.
Side A—DMD, primary DMD and escapes. Two data input connectors. Top components including
0.5 oz. (before
1 components, power mini- power generation and two data input connectors. Low frequency signals
plating)
planes routing. Should have copper fill (GND) plated up to 1 oz.
2 Ground 0.5 Solid ground plane (net GND) reference for signal layers #1, 3
High speed signal layer. High speed differential data busses from input
3 Signal (high frequency) 0.5
connector to DMD
4 Ground 0.5 Solid ground plane (net GND) reference for signal layers #3, #5
5 Power 0.5 Primary split power planes for 1.8 V, 3.3 V, 10 V, -14 V, 18 V
6 Power 0.5 Primary split power planes for 1.8 V, 3.3 V, 10 V, -14 V, 18 V
7 Ground 0.5 Solid ground plane (net GND) reference for signal layer #8
High speed signal layer. High speed differential data buses from input
8 Signal (high frequency) 0.5
connector to DMD
9 Ground 0.5 Solid ground plane (net GND) Reference for signal layers #8, 10
Side B—Secondary
0.5 oz. (before Discrete components if necessary. Low frequency signals routing. Should
10 components, power mini-
plating) be copper fill plated up to 1 oz.
planes
10.5 Power
TI strongly discourages signal routing on power planes or on planes adjacent to power planes. If signals must
be routed on layers adjacent to power planes, they must not cross splits in power planes to prevent EMI and
preserve signal integrity.
Connect all internal digital ground (GND) planes in as many places as possible. Connect all internal ground
planes with a minimum distance between connections of 0.5”. Extra vias may not be required if there are
sufficient ground vias due to normal ground connections of devices.
Connect power and ground pins of each component to the power and ground planes with at least one via for
each pin. Minimize trace lengths for component power and ground pins. (ideally, less than 0.100”).
Ground plane slots are strongly discouraged.
10.6 Trace Length Matching Recommendations
Table 10-4 and Table 10-5 describe recommended signal trace length matching requirements. Follow these
guidelines to avoid routing long traces over large areas of the PCB:
• Match the trace lengths so that longer signals route in a serpentine pattern
• Minimize the number of turns.
• Ensure that the turn angles no sharper than 45 degrees.
Figure 10-1 shows an example of the HSSI signal pair routing.
Signals listed in Table 10-4 are specified for data rate operation at up to 3.2 Gbps. Minimize the layer changes
for these signals. Minimize the number of vias. Avoid sharp turns and layer switching while minimizing the
lengths. When layer changes are necessary, place GND vias around the signal vias to provide a signal return
path. The distance from one pair of differential signals to another must be at least 2 times the distance within the
pair.
DLP650TE xc FYP
Package
TI Internal Numbering
Device Descriptor
(7 characters)
DLP650TE xc FYP
YYYYYY
11.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 24-Mar-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
DLP650TEA0FYP ACTIVE CPGA FYP 149 33 RoHS & Green NI-AU N / A for Pkg Type 0 to 70
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-May-2022
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