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DLP650TE

DLPS186A – MARCH 2021 – REVISED MAY 2022

DLP650TE 0.65 4-K UHD DMD

1 Features 3 Description
• 0.65-inch diagonal micromirror array The DLP650TE digital micromirror device (DMD) is
– 4-K UHD (3840 × 2160) display resolution a digitally controlled micro-electromechanical system
– 7.6-µm micromirror pitch (MEMS) spatial light modulator (SLM) that enables
– ±12° micromirror tilt (relative to flat surface) bright 4-K UHD display systems. The DLP® Products
– Corner illumination 0.65” 4-K UHD chipset is composed of the DMD,
• High speed serial interface (HSSI) input data bus DLPC7540 display controller, and DLPA100 Power
• Supports 4K UHD at 60 Hz and full HD at 240 Hz and motor driver. The compact physical size of the
• Laser-phosphor, LED, RGB laser, and lamp chipset provides a complete system solution that
operation supported by DLPC7540 display enables small form factor 4-K UHD displays.
controller, DLPA100 power management, and The DMD ecosystem includes established resources
motor driver IC to help the user accelerate the design cycle, which
2 Applications include production ready optical modules, optical
module manufacturers, and design houses.
• Laser TVs
• Smart Projectors Visit the Getting Started with TI DLP display
• Enterprise Projectors technology page to learn more about how to start
designing with the DMD.
(1)
Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)
DLP650TE FYP(149) 32.2 mm × 22.3 mm

(1) For all available packages, see the orderable addendum at


the end of the data sheet.

LS Interface

HSSI Macro A Data Pairs


8
DMD DCLKA

HSSI Macro B Data Pairs


8
DMD DCLKB
DLPC7540 DLP650TE
Display Controller DMD Power En VOFFSET HSSI DMD
Power VBIAS
3.3 V Management
VREG TPS65145 VRESET

12 V
1.8 V
VREG
DMD VDD En

I2C TMP411 Temperature


2

Simplified Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP650TE
DLPS186A – MARCH 2021 – REVISED MAY 2022 www.ti.com

Table of Contents
1 Features............................................................................1 8 Application and Implementation.................................. 27
2 Applications..................................................................... 1 8.1 Application Information............................................. 27
3 Description.......................................................................1 8.2 Typical Application.................................................... 27
4 Revision History.............................................................. 2 8.3 Temperature Sensor Diode....................................... 30
5 Pin Configuration and Functions...................................3 9 Power Supply Recommendations................................32
6 Specifications.................................................................. 6 9.1 Power Supply Sequence Requirements................... 32
6.1 Absolute Maximum Ratings........................................ 6 9.2 DMD Power Supply Power-Up Procedure................ 32
6.2 Storage Conditions..................................................... 6 9.3 DMD Power Supply Power-Down Procedure........... 32
6.3 ESD Ratings............................................................... 7 10 Layout...........................................................................34
6.4 Recommended Operating Conditions.........................7 10.1 Layout Guidelines................................................... 34
6.5 Thermal Information....................................................9 10.2 Impedance Requirements.......................................34
6.6 Electrical Characteristics...........................................10 10.3 Layers..................................................................... 34
6.7 Switching Characteristics.......................................... 11 10.4 Trace Width, Spacing..............................................35
6.8 Timing Requirements................................................ 11 10.5 Power......................................................................35
6.9 System Mounting Interface Loads............................ 15 10.6 Trace Length Matching Recommendations............ 35
6.10 Micromirror Array Physical Characteristics............. 16 11 Device and Documentation Support..........................37
6.11 Micromirror Array Optical Characteristics............... 17 11.1 Third-Party Products Disclaimer............................. 37
6.12 Window Characteristics.......................................... 19 11.2 Device Support........................................................37
6.13 Chipset Component Usage Specification............... 19 11.3 Documentation Support.......................................... 37
7 Detailed Description......................................................19 11.4 Receiving Notification of Documentation Updates.. 38
7.1 Overview................................................................... 19 11.5 Support Resources................................................. 38
7.2 Functional Block Diagram......................................... 20 11.6 Trademarks............................................................. 38
7.3 Feature Description...................................................21 11.7 Electrostatic Discharge Caution.............................. 38
7.4 Device Functional Modes..........................................21 11.8 Glossary.................................................................. 38
7.5 Optical Interface and System Image Quality 12 Mechanical, Packaging, and Orderable
Considerations............................................................ 21 Information.................................................................... 39
7.6 Micromirror Array Temperature Calculation.............. 22 12.1 Package Option Addendum.................................... 40
7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 23

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (March 2021) to Revision A (May 2022) Page


• This document is updated per the latest Texas Instruments and industry data sheet standards....................... 1
• Updated DMD Power Supply Requirements ................................................................................................... 32

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5 Pin Configuration and Functions

1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20

T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A

Figure 5-1. FYP Package 149-Pin CPGA Bottom View

Table 5-1. Pin Functions


PIN TRACE
TYPE(1) PIN DESCRIPTION LENGTH
NAME PAD ID (mm)
D_AP(0) J1 I High-speed differential data pair lane A0 18.09088
D_AN(0) H1 I High-speed differential data pair lane A0 18.0916
D_AP(1) G1 I High-speed differential data pair lane A1 18.11696
D_AN(1) F1 I High-speed differential data pair lane A1 18.11641
D_AP(2) A3 I High-speed differential data pair lane A2 11.11822
D_AN(2) A4 I High-speed differential data pair lane A2 11.11745
D_AP(3) D2 I High-speed differential data pair lane A3 12.04461
D_AN(3) C2 I High-speed differential data pair lane A3 12.04491
D_AP(4) F2 I High-speed differential data pair lane A4 15.1345
D_AN(4) E2 I High-speed differential data pair lane A4 15.13457
D_AP(5) A5 I High-speed differential data pair lane A5 12.80888
D_AN(5) A6 I High-speed differential data pair lane A5 12.80825
D_AP(6) A7 I High-speed differential data pair lane A6 6.34763
D_AN(6) A8 I High-speed differential data pair lane A6 6.34706
D_AP(7) A9 I High-speed differential data pair lane A7 4.45653
D_AN(7) A10 I High-speed differential data pair lane A7 4.45875
DCLK_AP C1 I High-speed differential clock A 15.08029
DCLK_AN D1 I High-speed differential clock A 15.07977
D_BP(0) A11 I High-speed differential data pair lane B0 4.06642
D_BN(0) A12 I High-speed differential data pair lane B0 4.06697
D_BP(1) A13 I High-speed differential data pair lane B1 6.42676

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Table 5-1. Pin Functions (continued)


PIN TRACE
TYPE(1) PIN DESCRIPTION LENGTH
NAME PAD ID (mm)
D_BN(1) A14 I High-speed differential data pair lane B1 6.42716
D_BP(2) A15 I High-speed differential data pair lane B2 11.90485
D_BN(2) A16 I High-speed differential data pair lane B2 11.90509
D_BP(3) A18 I High-speed differential data pair lane B3 13.80223
D_BN(3) A19 I High-speed differential data pair lane B3 13.80269
D_BP(4) D19 I High-speed differential data pair lane B4 12.45294
D_BN(4) C19 I High-speed differential data pair lane B4 12.45252
D_BP(5) H20 I High-speed differential data pair lane B5 15.7909
D_BN(5) J20 I High-speed differential data pair lane B5 15.79026
D_BP(6) D20 I High-speed differential data pair lane B6 11.02899
D_BN(6) E20 I High-speed differential data pair lane B6 11.02947
D_BP(7) F20 I High-speed differential data pair lane B7 14.7517
D_BN(7) G20 I High-speed differential data pair lane B7 14.75085
DCLK_BP B17 I High-speed differential clock B 9.17864
DCLK_BN B18 I High-speed differential clock B 9.17821
LS_WDATA_P T10 I LVDS Data 11.27905
LS_WDATA_N R11 I LVDS Data 6.76474
LS_CLK_P R9 I LVDS CLK 13.5461
LS_CLK_N R10 I LVDS CLK 12.56934
LS_RDATA_A_BISTA T13 O LVCMOS Output 3.12045
BIST_B T12 O LVCMOS Output 5.63628
AMUX_OUT B20 O Analog Test Mux 9.3849
DMUX_OUT R14 O Digital Test Mux 3.85333
DMD_DEN_ARSTZ T11 I ARSTZ 5.86593
TEMP_N R8 I Temp Diode N 14.63792
TEMP_P R7 I Temp Diode P 15.93219
B7, B13, C18,
E3, H3, J2,
K3, L2, L19,
M1, M2, N3,
VDD N19, P2, P18, P Digital core supply voltage Plane
R3, R5, R12,
R17, R19, T2,
T4, T6, T8,
T18
B4, B9, B11,
VDDA B16, C20, D3, P HSSI supply voltage Plane
E18, G2, G19
Supply voltage for negative bias of micromirror reset
VRESET B3, R1 P Plane
signal
Supply voltage for positive bias of micromirror reset
VBIAS E1, P1 P Plane
signal
A20, B2, T1, Supply voltage for HVCMOS logic, stepped up logic
VOFFSET P Plane
T20 level

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Table 5-1. Pin Functions (continued)


PIN TRACE
TYPE(1) PIN DESCRIPTION LENGTH
NAME PAD ID (mm)
A17, B6, B10,
B14, D18, F3,
F19, J3, K2,
K19, L1, L3,
M3, N2, N18,
VSS G Ground Plane
N20, P3, P20,
R2, R4, R6,
R13, R20, T5,
T7, T16, T17,
T19
B5, B8, B12,
B15, B19, C3,
E19, G3, H2,
VSSA G Ground Plane
H19, K1, N1,
P19, R18, T3,
T9
R15,T14,T15,
R16,H18,J18,
G18,J19,F18,
N/C No connect
K20,K18,M19,
L20,M18,L18,
M20

(1) I=Input, O=Output, P=Power, G=Ground, NC = No connect

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6 Specifications
6.1 Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those
indicated under Recommended Operating Conditions. Exposure above or below the Recommended Operating Conditions for
extended periods may affect device reliability.
Parameter Name Description MIN MAX UNIT
Supply Voltage
Supply voltage for LVCMOS core logic and LVCMOS low speed interface
VDD –0.5 2.3 V
(LSIF) (1)
VDDA Supply voltage for high speed serial interface (HSSI) receivers (1) –0.3 2.2 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode (1) (2) –0.5 11 V
VBIAS Supply voltage for micromirror electrode (1) –0.5 17 V
VRESET Supply voltage for micromirror electrode (1) –13 0.5 V
| VDDA – VDD | Supply voltage delta (absolute value) (3) 0.3 V
| VBIAS – VOFFSET | Supply voltage delta (absolute value) (4) 11 V
| VBIAS – VRESET | Supply voltage delta (absolute value) (5) 30 V
Input Voltage
Input voltage for other inputs – LSIF and LVCMOS (1) –0.5 2.45 V
Input voltage for other inputs – HSSI (1) (6) –0.2 VDDA V
Low speed interface (LSIF)
fCLOCK LSIF clock frequency (LS_CLK) 130 MHz
| VID | LSIF differential input voltage magnitude (6) 810 mV
IID LSIF differential input current(7) 10 mA
High speed serial interface (HSSI)
fCLOCK HSSI clock frequency (DCLK) 1.65 GHz
| VID | HSSI differential input voltage magnitude Data Lane (6) 700 mV
| VID | HSSI differential input voltage magnitude Clock Lane (6) 700 mV
Environmental
TARRAY Temperature, operating(8) 0 90 °C
TARRAY Temperature, non-operating(8) –40 90 °C
TDP Dew point temperature, operating and non-operating (non-condensing) 81 ºC

(1) All voltage values are with respect to the ground terminals (VSS). The following required power supplies must be connected for proper
DMD operation: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(2) VOFFSET supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable absolute voltage difference between VDDA and VDD may result in excessive current draw.
(4) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. LVDS and HSSI
differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(7) Differential inputs must not exceed the specified limit or damage may result to the internal termination resistors. Specification applies to
both the High speed serial interface (HSSI) and the low speed interface (LSI).
(8) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point
(TP1) shown in Figure 7-1 and the package thermal resistances using the Micromirror Array Temperature Calculation.

6.2 Storage Conditions


Applicable for the DMD as a component or non-operating in a system.
SYMBOL PARAMETER MIN MAX UNIT
TDMD DMD storage temperature –40 80 ºC
TDP-AVG Average dew point temperature (non-condensing) (1) 28 ºC
TDP-ELR Elevated dew point temperature range (non-condensing) (2) 28 36 ºC

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6.2 Storage Conditions (continued)


Applicable for the DMD as a component or non-operating in a system.
SYMBOL PARAMETER MIN MAX UNIT
CTELR Cumulative time in the elevated dew point temperature range 24 Months

(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.

6.3 ESD Ratings


SYMBOL PARAMETER DESCRIPTION VALUE UNIT
Electrostatic
V(ESD) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V
discharge
Electrostatic
V(ESD) Charged device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 V
discharge

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions


Over operating free-air temperature range and supply voltages (unless otherwise noted) (1)
Parameter Name MIN NOM MAX UNIT
Supply Voltages (2) (3)
Supply voltage for LVCMOS core logic and low speed
VDD 1.71 1.8 1.95 V
interface (LSIF)
VDDA Supply voltage for high speed serial interface (HSSI) receivers 1.71 1.8 1.95 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode (4) 9.5 10 10.5 V
VBIAS Supply voltage for micromirror electrode 15.5 16 16.5 V
VRESET Supply voltage for micromirror electrode –12.5 –12 –11.5 V
| VDDA – VDD | Supply voltage delta, absolute value (5) 0.3 V
| VBIAS – VOFFSET | Supply voltage delta, absolute value (6) 10.5 V
| VBIAS – VRESET | Supply voltage delta, absolute value 29 V
LVCMOS Input
VIH High level input voltage (7) 0.7 x VDD V
VIL Low level input voltage (7) 0.3 x VDD V
Low Speed Interface (LSIF)
fCLOCK LSIF clock frequency (LS_CLK) (8) 108 120 130 MHz
DCDIN LSIF duty cycle distortion (LS_CLK) 44% 56%
| VID | LSIF differential input voltage magnitude (8) 150 350 440 mV
VLVDS LSIF voltage. (8) 575 1520 mV
VCM Common mode voltage. (8) 700 900 1300 mV
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ZIN Internal differential termination resistance 80 100 120 Ω
High Speed Serial Interface (HSSI)
fCLOCK HSSI clock frequency (DCLK) (9) 1.2 1.6 GHz
DCDIN HSSI duty cycle distortion (DCLK) 44% 50% 56%
| VID | Data HSSI differential input voltage magnitude Data Lane (9) 100 600 mV
| VID | CLK HSSI differential input voltage magnitude Clock Lane (9) 295 600 mV
VCMDC Data Input common mode voltage (DC) Data Lane (9) 200 600 800 mV
VCMDC CLK Input common mode voltage (DC) Clk Lane (9) 200 600 800 mV

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6.4 Recommended Operating Conditions (continued)


Over operating free-air temperature range and supply voltages (unless otherwise noted) (1)
Parameter Name MIN NOM MAX UNIT
AC peak to peak (ripple) on common mode voltage of Data
VCMACp-p 100 mV
Lane and Clock Lane (9)
ZLINE Line differential impedance (PWB/trace) 100 Ω
ZIN Internal differential termination resistance. ( RXterm ) 80 100 120 Ω
Environmental
Array temperature, long-term operational. (10) (11) (12) (13) 10 40 to 70 °C
TARRAY
Array temperature, short-term operational, 500 hr max. (11) (14) 0 10 °C
TDP-AVG Average dew point temperature (non-condensing)(15) 28 °C
TDP-ELR Elevated dew point temperature range (non-condensing)(16) 28 36 °C
CTELR Cumulative time in elevated dew point temperature range 24 Months
QAP-ILL Window aperture illumination overfill(17) (18) 17 W/cm2
LAMP ILLUMINATION
ILLUV Illumination wavelength < 395 nm (10) 0.68 2 mW/cm2
ILLVIS Illumination wavelengths between 395 nm and 800 nm 29.3 W/cm2
ILLIR Illumination wavelength > 800 nm 10 mW/cm2
SOLID STATE ILLUMINATION
ILLUV Illumination wavelength < 410 nm (10) 3 mW/cm2
ILLVIS Illumination wavelengths between 410 nm and 800 nm 34.7 W/cm2
ILLIR Illumination wavelength > 800 nm 10 mW/cm2

(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.
(2) All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are
required to operate the DMD.
(3) All voltage values are with respect to the VSS ground pins.
(4) VOFFSET supply transients must fall within specified max voltages.
(5) To prevent excess current, the supply voltage delta | VDDA – VDD | must be less than specified limit.
(6) To prevent excess current, the supply voltage delta | VBIAS – VOFFSET | must be less than specified limit.
(7) LVCMOS input pin is DMD_DEN_ARSTZ.
(8) See the low speed interface (LSIF) timing requirements in Timing Requirements.
(9) See the high speed serial interface (HSSI) timing requirements in Timing Requirements.
(10) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will
reduce device lifetime.
(11) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point
(TP1) shown in Figure 7-1 and the package thermal resistances using the Micromirror Array Temperature Calculation.
(12) Per Figure 6-1, the maximum operational array temperature should be de-rated based on the micromirror landed duty cycle that the
DMD experiences in the end application. Refer to Micromirror Landed Duty Cycle for a definition of micromirror landed duty cycle.
(13) Long-term is defined as the usable life of the device.
(14) Short-term is the total cumulative time over the useful life of the device.
(15) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(16) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.
(17) The active area of the DMD is surrounded by an aperture on the inside of the DMD window surface that masks structures of the
DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating
the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD.
The illumination optical system should be designed to minimize light flux incident outside the active array. Depending on the
particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may
cause system performance degradation.
(18) Applies to the region in red in Figure 6-2.

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Maximum Recommended Array Temperature - Operational (¹C)


80

70

60

50

40

30
0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
100/0 95/5 90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45 50/50
Micromirror Landed Duty Cycle

Figure 6-1. Maximum Recommended Array Temperature - Derating Curve

0.50 mm Critical area on aperture

10.615 mm
Array Window
Aperture
Window

Window Aperture
Window

Figure 6-2. Illumination Overfill Diagram - Critical Area

6.5 Thermal Information


DLP650TE
symbol Thermal Metric FYP Package Unit
149 Pins
RARRAY_TO_CERAMIC Thermal resistance, active area to test point 1 (TP1)(1) 0.6 °C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the DMD within the temperature range specified in the Recommend Operating Conditions. The total heat load on the DMD
is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the
window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling
outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

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6.6 Electrical Characteristics


Over operating free-air temperature range and supply voltages (unless otherwise noted)
SYMBOL PARAMETER (1) (2) TEST CONDITIONS (1) MIN TYP MAX UNIT
Current – Typical
IDD Supply current VDD (3) 800 1250 mA
IDDA Supply current VDDA (3) 900 1200 mA
IDDA Supply current VDDA (3) single macro mode 500 600 mA
IOFFSET Supply current VOFFSET (4) (5) 23 35 mA
IBIAS Supply current VBIAS (4) (5) 2.4 3.8 mA
IRESET Supply current VRESET (5) -10.5 -7.7 mA
Power – Typical
PDD Supply power dissipation VDD (3) 1440 2437.5 mW
PDDA Supply power dissipation VDDA (3) 1620 2340 mW
PDDA Supply power dissipation VDDA (3) single macro mode 900 1170 mW
POFFSET Supply power dissipation VOFFSET (4) (5) 230 367.5 mW
PBIAS Supply power dissipation VBIAS (4) (5) 38.4 62.7 mW
PRESET Supply power dissipation VRESET (5) 92.4 131.25 mW
PTOTAL Supply power dissipation Total 3420.8 5338.95 mW
LVCMOS Input
IIL Low level input current (6) VDD = 1.95 V , VI = 0 V –100 nA
IIH High level input current (6) VDD = 1.95 V , VI = 1.95 V 135 µA
LVCMOS Output
VOH DC output high voltage (7) IOH = -2 mA 0.8 x VDD V
VOL DC output low voltage (7) IOL = 2 mA 0.2 x VDD V
Receiver Eye Characteristics
A1 Minimum data eye opening (8) 100 600 mV
A1 Minimum clock eye opening (8) 295 600 mV
A2 Maximum signal swing (8) (9) 600 mV
X1 Maximum eye closure (8) 0.275 UI
X2 Maximum eye closure (8) 0.4 UI
Drift between Clock and Data between
| tDRIFT | 20 ps
Training Patterns
Capacitance
CIN Input capacitance LVCMOS f = 1 MHz 10 pF
Input capacitance LSIF (low speed
CIN f = 1 MHz 20 pF
interface)
Input capacitance HSSI (high speed serial
CIN interface) - Differential - Clock and Data f = 1 MHz 5 pF
pins
COUT Output capacitance f = 1 MHz 10 pF

(1) All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are
required to operate the DMD.
(2) All voltage values are with respect to the ground pins (VSS).
(3) To prevent excess current, the supply voltage delta | VDDA – VDD | must be less than specified limit.
(4) To prevent excess current, the supply voltage delta | VBIAS – VOFFSET | must be less than specified limit.
(5) Supply power dissipation based on 3 global resets in 200 µs.
(6) LVCMOS input specifications are for pin DMD_DEN_ARSTZ.
(7) LVCMOS output specification is for pins LS_RDATA_A and LS_RDATA_B.
(8) Refer to Figure 6-12 (1e-12 BER).
(9) Defined in Recommended Operation Conditions.

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6.7 Switching Characteristics


Over operating free-air temperature range and supply voltages (unless otherwise noted)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output propagation, clock to Q, rising edge of LS_CLK
tpd CL = 5 pF 11.1 ns
(differential clock signal) input to LS_RDATA output. (1)
Output propagation, clock to Q, rising edge of LS_CLK
tpd CL = 10 pF 11.3 ns
(differential clock signal) input to LS_RDATA output. (1)
Slew rate, LS_RDATA 20% to 80%, CL <40p 0.35 V/ns
Output duty cycle distortion, LS_RDATA_A and 50 − (C2Q_rise − C2Q_fall )
40% 60%
LS_RDATA_B x 130e6 x 100

(1) See Figure 6-3.

LS_CLK_P
1 0 1 0 1 0 1 0 1 0
LS_CLK_N
1 period
LS_WDATA_P
Stop (1) Start (0)
LS_WDATA_N
tPD

LS_RDATA_A
BIST_A Acknowledge

Figure 6-3. Switching Characteristics

6.8 Timing Requirements


Over operating free-air temperature range and supply voltages (unless otherwise noted)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVCMOS
tr Rise time (1) 20% to 80% reference points 25 ns
tf Fall time (1) 80% to 20% reference points 25 ns
Low Speed Interface (LSIF)
tr Rise time (2) 20% to 80% reference points 450 ps
tf Fall time (2) 80% to 20% reference points 450 ps
tW(H) Pulse duration high (3) LS_CLK. 50% to 50% reference points 3.1 ns
tW(L) Pulse duration low (3) LS_CLK. 50% to 50% reference points 3.1 ns
LS_WDATA valid before rising edge of LS_CLK
tsu Setup time (4) 1.5 ns
(differential)
LS_WDATA valid after rising edge of LS_CLK
th Hold time (4) 1.5 ns
(differential)
High Speed Serial Interface (HSSI)
tr Rise time(5), Data from -A1 to A1 minimum eye height specification 50 115 ps
tr Rise time(5), Clock from -A1 to A1 minimum eye height specification 50 135 ps
tf Fall time(5), Data from A1 to -A1 minimum eye height specification 50 115 ps
tf Fall time(5), Clock from A1 to -A1 minimum eye height specification 50 135 ps
tW(H) Pulse duration high (6) DCLK. 50% to 50% reference points 0.275 ns
tW(L) Pulse duration low (6) DCLK. 50% to 50% reference points 0.275 ns
tc Cycle time (6) DCLK 0.625 0.833 ns

(1) See Figure 6-9 and Figure 6-10 LVCMOS Rise, Fall Time SLew Rate Figures. Specification is for DMD_DEN_ARSTZ pin (LVCMOS).
(2) See Figure 6-6 for rise and fall time for LSIF.

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(3) See Figure 6-5 for pulse duration high and low time for LSIF.
(4) See Figure 6-5 for setup and hold time for LSIF.
(5) See Figure 6-11 for rise and fall time for HSSI.
(6) See Figure 6-13 for pulse duration high and low and cycle time for HSSI.

1.255 V

VLVDS(max)

VCM VID

VLVDS(min)

0.575 V

A. See Equation 1 and Equation 2

Figure 6-4. LSIF Waveform Requirements

1
VLVDS :max ; = VCM :max ; + , × VID:max ; ,
2
(1)

1
VLVDS :min; = VCM :min; F , × VID:max ; ,
2
(2)

tW(L)| tW(H)|
LS_CLK_P

50%

LS_CLK_N

tSU| tH|
LS_WDATA_P

50%
LS_WDATA_N
tWINDOW|

Figure 6-5. LSIF Timing Requirements

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VLS_CLK_P, VLS_CLK_N, VLS_WDATA_P, VLS_WDATA_N


100
90
80
70

VID Voltage (%)


60
50

40
30

20

10
0
tr tf

Figure 6-6. LSIF Rise, Fall Time Slew Rate

+ (VIP + VIN)
VCM =
± 2 LS_CLK_P,
LS_WDATA_P

VID
LS_CLK_N,
LS_WDATA_N LVDS
Receiver

VCM VIP VIN

Figure 6-7. LSIF Voltage Requirements

LS_CLK_P
LS_WDATA_P
ESD Internal
Termination
(ZIN)
LS_CLK_N LVDS
LS_WDATA_N Receiver

ESD

Figure 6-8. LSIF Equivalent Input

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VDD18 Voltage (%)


VIH
VT+

'VT

VT±
VIL
DMD_DEN_ARTZ

Time

Figure 6-9. LVCMOS Input Hysteresis

DMD_DEN_ARSTZ
100
VDD Voltage (%)

80

VIL(AC)
20

tR tF

Time

Figure 6-10. LVCMOS Rise, Fall Time Slew Rate

tf
VHSSI(max)

VCM VID

VHSSI(min)
tr

A. See Equation 3 and Equation 4

Figure 6-11. HSSI Waveform Requirements

1
VHSSI :max ; = VCM :max ; + , × VID:max ; ,
2
(3)

1
VHS SI:min ; = VCM :min ; F , × VID:max ; ,
2
(4)

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A2

A1

0V

-A1
-A2

X1 1-X1
X2 1-X2
0 1 UI
Figure 6-12. HSSI Eye Characteristics

tC|

tW(L)| tW(H)|
DCLK_?P

50%

DCLK_?N

Figure 6-13. HSSI CLK Characteristics

6.9 System Mounting Interface Loads


PARAMETER MIN TYP MAX UNIT
When loads are applied on both the electrical and thermal interface areas
Maximum load to be applied to the electrical interface area(1) 111 N
Maximum load to be applied to the thermal interface area(1) 111 N
When load is applied on the electrical interface area only
Maximum load to be applied to the electrical interface area(1) 222 N
Maximum load to be applied to the thermal interface area(1) 0 N

(1) The load should be applied uniformly in the corresponding areas shown in Figure 6-14.

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Electrical Interface Area

Thermal Interface Area

Figure 6-14. System Mounting Interface Loads

6.10 Micromirror Array Physical Characteristics


SYMBOL PARAMETER DESCRIPTION MIN TYP MAX UNIT
M Number of active columns(1) 1920 micromirrors
N Number of active rows(1) 1080 micromirrors
P Micromirror (pixel) pitch(1) 7.6 um
Micromirror active array (micromirror pitch) x (number of active
14.592 mm
width(1) columns)
Micromirror active array
(micromirror pitch) x (number of active rows) 8.208 mm
height (1)
Micromirror active border(2) Pond of micromirror (POM) 14 micromirrors/side

(1) See Figure 6-15.


(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.

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M±4
M±3
M±2
M±1
Incident
Illumination

0
1
2
3
Light Path
0
1
2
3

Active Micromirror Array


NxP
M x N Micromirrors

N±4
N±3
N±2
N±1

Off-State
MxP
Light Path

P P
Pond Of Micromirrors (POM) omitted for clarity.

Details omitted for clarity. Not to scale.

Figure 6-15. Micromirror Array Physical Characteristics

6.11 Micromirror Array Optical Characteristics


PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Micromirror tilt angle(1) (2) (3) (4) (5) landed state 11 12 13 °
Micromirror crossover time(6) typical performance 2.5 us
Micromirror switching time(7) typical performance 8 us
Gray 10 Screen(10)
Bright pixels(s) in active area(9) 0 micromirrors

Gray 10 Screen(10)
Bright pixes(s) in POM(11) 1 micromirrors
Image
performance(8)
Dark pixel(s) in active area(12) White Screen 4 micromirrors
Adjacent pixels(13) Any Screen 0 micromirrors
Unstable pixel(s) in active area(14) Any Screen 0 micromirrors

(1) Measured relative to the plane formed by the overall micromirror array.
(2) Represents the landed tilt angle variation relative to the nominal landed tilt angle.
(3) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(4) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations or system contrast variations.

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(5) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State
direction. A binary value of 0 results in a micromirror landing in the OFF State direction, see Figure 6-16.
(6) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.
(7) The minimum time between successive transitions of a micromirror.
(8) Conditions of Acceptance: All DMD image performance returns will be evaluated using the following projected image test conditions:
Test set degamma shall be linear
Test set brightness and contrast shall be set to nominal
The diagonal size of the projected image shall be a minimum of 60 inches
The projection screen shall be 1x gain
The projected image shall be inspected from an 8 foot minimum viewing distance
The image shall be in focus during all image performance tests
(9) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter that the surrounding pixels
(10) Gray 10 screen definition: All areas of the screen are colored with the following settings:
Red = 10/255
Green = 10/255
Blue = 10/255
(11) POM definition: Rectangular border of off-state mirror surrounding the active area.
(12) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels.
(13) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster.
(14) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with the parameters loaded into memory. The
unstable pixel appears to be flickering asynchronously with the image.

Incident Light
Direction

Off-State Light
Direction

Landed Corner
Rotation Axis

On-State Off-State
Tilted Mirror Tilted Mirror

A Flat-State
Mirror

Landed Corner

A
Landed Corner

Rotation Axis

Landed Corner
View A-A

Figure 6-16. Micromirror Landed Orientation and Tilt

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6.12 Window Characteristics


PARAMETER TEST CONDITION MIN TYP MAX UNIT
Window material designation Corning EagleXG
Window refractive index at wavelength 546.1 nm 1.5119
Window transmittance, average over the wavelength
Applies to all angles 0-30 AOI (1) (2) 97.8%
range 420-680 nm
Window transmittance, average over the wavelength
Applies to all angles 30-45 AOI (1) (2) 96.4%
range 420-680 nm

(1) Single-pass-through both surfaces and glass


(2) AOI - angle of incidence is the angle between an incident ray and the normal to a reflecting or refracting surface

6.13 Chipset Component Usage Specification


Reliable function and operation of the DLP650TE DMD requires that it be used in conjunction with the other
components of the applicable DLP chipset, including those components that contain or implement TI DMD
control technology. TI DMD control technology consists of the TI technology and devices used for operating or
controlling a DLP DMD.

Note
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.

7 Detailed Description
7.1 Overview
The DMD is a 0.65-inch diagonal spatial light modulator that consists of an array of highly reflective
aluminum micromirrors. The DMD is an electrical input, optical output micro-optical-electrical-mechanical system
(MOEMS). The fast switching speed of the DMD micromirrors combined with advanced DLP image processing
algorithms enables each micromirror to display four distinct pixels on the screen during every frame, resulting
in a full 3840 × 2160 pixel image being displayed. The electrical interface is low voltage differential signaling
(LVDS). The DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is organized in a
grid of M memory cell columns by N memory cell rows. Refer to Section 7.2. The positive or negative deflection
angle of the micromirrors can be individually controlled by changing the address voltage of underlying CMOS
addressing circuitry and micromirror reset signals (MBRST).
The DLP 0.65” 4-K UHD chipset is comprised of the DLP650TE DMD, DLPC7540 display controller, the
DLPA100 power management and motor driver. To ensure reliable operation, the DLP650TE DMD must always
be used with the DLP display controller and the power and motor specified in the chipset.

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7.2 Functional Block Diagram

VOFFSET
VRESET

LOADB
SCTRL
VBIAS

VREF

DATA
DCLK
VDD

TRC
VSS
Channel A Interface

Control Column Read/Write Control

Bit Lines

(0,0)
Word
Voltage Voltages Micromirror Lines
Row
Generators Array

(M-1,N-1)

Bit Lines

Control Column Read/Write Control

Channel B Interface
DRC_STROBE
VRESET
VBIAS
VOFFSET
VDD
VREF
VSS

DRC_OEZ
DRC_BUS
SAC_BUS
SAC_CLK
RESERVED

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7.3 Feature Description


7.3.1 Power Interface
The DMD requires 4 DC voltages: 1.8 V source, VOFFSET, VRESET, and VBIAS. In a typical configuration, 3.3 V is
created by the DLPA100 power management and motor driver and is used on the DMD board to create the 1.8
V. The TI voltage regulator TPS65145 takes in the 3.3 V and outputs VOFFSET, VRESET, VBIAS.
7.3.2 Timing
The data sheet specifies timing at the device pin. For output timing analysis, the tester pin electronics and
its transmission line effects must be considered. Timing reference loads are not intended to be precise
representations of any particular system environment or depiction of the actual load presented by a production
test. TI recommends that system designers use IBIS or other simulation tools to correlate the timing reference
load to a system environment. Use the specified load capacitance value for characterization and measurement
of AC timing signals only. This load capacitance value does not indicate the maximum load the device is capable
of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC7540 display controller. See the DLPC7540 Display Controller
Data Sheet or contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1 Numerical Aperture and Stray Light Control
TI recommends that the light cone angle defined by the numerical aperture of the illumination optics is the
same as the light cone angle defined by the numerical aperture of the projection optics. This angle must not
exceed the nominal device micromirror tilt angle unless appropriate apertures are added in the illumination and
projection pupils to block out flat-state and stray light from the projection lens. The micromirror tilt angle defines
DMD capability to separate the "ON" optical path from any other light path, including undesirable flat-state
specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD
such as prism or lens surfaces. If the numerical aperture exceeds the micromirror tilt angle, or if the projection
numerical aperture angle is more than two degrees larger than the illumination numerical aperture angle (and
vice versa), contrast degradation and objectionable artifacts in the display border and active area could occur.
7.5.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display border and active area, which may require additional system apertures to control,
especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. Design the illumination optical
system to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the
average flux level in the active area. Depending on the particular system optical architecture, overfill light may
have to be further reduced below the suggested 10% level in order to be acceptable.

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7.6 Micromirror Array Temperature Calculation

Array

Window Edge Window Aperture


(4 surfaces)

TP1

4.5

16.1 TP1

Figure 7-1. DMD Thermal Test Point

Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from
measurement points on the outside of the package, the package thermal resistance, the electrical power, and
the illumination heat load. The relationship between array temperature and the reference ceramic temperature
(thermal test TP1 in Figure 7-1) is provided by the following equations:

TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC) (5)

QARRAY = QELECTRICAL + QILLUMINATION (6)

where
• TARRAY = Computed array temperature (°C)
• TCERAMIC = Measured ceramic temperature (°C) (TP1 location)
• RARRAY-TO-CERAMIC = Thermal resistance of package specified in Section 6.5 from array to ceramic TP1 (°C/
Watt)
• QARRAY = Total DMD power on the array (W) (electrical + absorbed)
• QELECTRICAL = Nominal electrical power (W)

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• QINCIDENT = Incident illumination optical power (W)


• QILLUMINATION = (DMD average thermal absorptivity × QINCIDENT) (W)
• DMD average thermal absorptivity = 0.42
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 3.0 W. The
absorbed power from the illumination source is variable and depends on the operating state of the micromirrors
and the intensity of the light source. The equations shown above are valid for a single chip or multi-chip DMD
system. It assumes an illumination distribution of 83.7% on the active array, and 16.3% on the array border.
The sample calculation for a typical projection application is as follows:

QINCIDENT = 25 W (measured) (7)

TCERAMIC = 55.0°C (measured) (8)

QELECTRICAL = 3.0 W (9)

QARRAY = 3.0W + (0.42 × 25 W) = 13.5 W (10)

TARRAY = 55.0°C + (13.5W × 0.6°C/W) = 63.1°C (11)

7.7 Micromirror Landed-On/Landed-Off Duty Cycle


7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the percentage of time that an
individual micromirror is landed in the ON state versus the amount of time the same micromirror is landed in the
OFF state.
For example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the time
(and in the OFF state 0% of the time); whereas 0/100 indicates that the pixel is in the OFF state 100% of the
time. Likewise, 50/50 indicates that the pixel is ON for 50% of the time (and OFF for 50% of the time).
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD useful life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the
landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example,
a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect DMD useful life, and this interaction can
be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD useful life. This is
quantified in the de-rating curve shown in Figure 6-1. The importance of this curve is that:
• All points along this curve represent the same useful life.
• All points above this curve represent lower useful life (and the further away from the curve, the lower the
useful life).

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• All points below this curve represent higher useful life (and the further away from the curve, the higher the
useful life).
In practice, this curve specifies the maximum operating DMD temperature for a given long-term average landed
duty cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
operates under a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the pixel
operates under a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in Table 7-1.
Table 7-1. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE LANDED DUTY CYCLE
0% 0/100
10% 10/90
20% 20/80
30% 30/70
40% 40/60
50% 50/50
60% 60/40
70% 70/30
80% 80/20
90% 90/10
100% 100/0

Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given
primary must be displayed in order to achieve the desired white point.
Use this information to calculate the landed duty cycle of a given pixel during a given time period:
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) +
(Blue_Cycle_% × Blue_Scale_Value)
where
• Red_Cycle_%, represents the percentage of the frame time that red is displayed to achieve the desired white
point
• Green_Cycle_% represents the percentage of the frame time that green is displayed to achieve the desired
white point
• Blue_Cycle_%, represents the percentage of the frame time that blue is displayed to achieve the desired
white point
For example, assume that the red, green, and blue color cycle times are 30%, 50%, and 20% respectively (in
order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, blue
color intensities are shown in Table 7-2 and Table 7-3.

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Table 7-2. Example Landed Duty Cycle for Full-


Color, Color Percentage
CYCLE PERCENTAGE
RED GREEN BLUE
30% 50% 20%

Table 7-3. Example Landed Duty Cycle for Full-Color


SCALE VALUE LANDED DUTY
RED GREEN BLUE CYCLE

0% 0% 0% 0/100
100% 0% 0% 30/70
0% 100% 0% 50/50
0% 0% 100% 20/80
0% 12% 0% 6/94
0% 0% 35% 7/93
60% 0% 0% 18/82
0% 100% 100% 70/30
100% 0% 100% 50/50
100% 100% 0% 80/20
0% 12% 35% 13/87
60% 0% 35% 25/75
60% 12% 0% 24/76
100% 100% 100% 100/0

The last factor to account for in estimating the landed duty cycle is any applied image processing. Within the
DLPC7540 controller, the gamma function affects the landed duty cycle.
Gamma is a power function of the form Output_Level = A × Input_LevelGamma, where A is a scaling factor that is
typically set to 1.
In the DLPC7540 controller, gamma is applied to the incoming image data on a pixel-by-pixel basis. A typical
gamma factor is 2.2, which transforms the incoming data as shown in Figure 7-2.

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100
90
80
Output Level (%) 70 Gamma = 2.2
60
50
40
30
20
10
0
0 10 20 30 40 50 60 70 80 90 100
Input Level (%) D002

Figure 7-2. Example of Gamma = 2.2

From Figure 7-2, if the gray scale value of a given input pixel is 40% (before gamma is applied), then gray scale
value is 13% after gamma is applied. Therefore, it can be seen that since gamma has a direct impact displayed
gray scale level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.
Consideration must also be given to any image processing which occurs before the DLPC7540 controllers.

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8 Application and Implementation


Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information


DMDs are spatial light modulators, which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into a projection or collection optic. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the DLPC7540
controller. Typical applications using the DLP650TE DMD include Laser TVs, smart projectors, and enterprise
projectors.
DMD power-up and power-down sequencing is strictly controlled by the DLPC7540 through the TPS65145
PMIC. Refer to Section 9 for power-up and power-down specifications. To ensure reliable operation, the
DLP650TE DMD must always be used with DLPC7540 controller, a DLPA100 PMIC/motor driver, and a
TPS65145 PMIC.
8.2 Typical Application
The DLP650TE DMD combined with DLPC7540 digital controller and a power management device provides
full 4-K UHD resolution for bright, colorful display applications. A typical display system using laser phosphor
illumination combines the DLP650TE DMD, DLPC7540 display controller, TPS65145 voltage regulator and
DLPA100 PMIC and motor driver. Figure 8-1 shows a system block diagram for this configuration of the DLP
0.65” 4-K UHD chipset and additional system components needed. See Figure 8-2 for a block diagram showing
the system components needed along with the lamp configuration of the DLP 0.65” 4-K UHD chipset. The
components include DLP650TE DMD, DLPC7540 display controller and DLPA100 PMIC and motor driver and a
TPS65145 PMIC.

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CTRL Signals Laser


Driver
TPS56121 1.15V 1.8V
12V DLPC7540

12V
Voltage Reg.

LMR33630C 3.3V
TPS65145
12 V DLPA100
1.21V
(Controller 3.3V
Voltages) 5V
}
DLPC7540

Voltage Reg. Flash PW Motor


Drive
ADDR DATA CTRL
(23) (16) Fans (3x)
CW Motor Drive
1.15V 12V DLPA100
1.21V Fans (3x)
(Filter wheel)
1.8V
3.3V Comparator
CW_INDEX1
Comparator Vref
HDMI CW_INDEX2
Front End IC I2C Vref
3840x2160
VbyOneTM 2-Port HSSI
@ 60Hz
SPI LS Interface
VOFFSET
TPS65145
3D L/R DLPC7540 DMD VRESET DLP650TE
3.3V
Controller Voltages VBIAS .65" UHD
GPIO
S451 HSSI
Tilt (& Roll) 1.8V DMD
12V LMR33630C
Sensor
3.3V Temp
IR Rx (2) I2C TMP411 (2)

(2)
XPR Drive Data Drive 4-Way XPR
USB 2.0 Electronics Actuator
USB2.0 GPIO
(2)
Mux
DB Drive Data Dynamic Black
USB Actuators (2X)
(2)
DLP Chipset Components Camera

TI Components

3rd Party Components

Figure 8-1. Typical 4K UHD Laser Phosphor Application Diagram

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TPS56121 1.15V CTRL Signals Lamp x

12V DLPC7540
Voltage Reg. Ballast

LMR33630C 3.3V 1.8V


12V
Voltage Reg. TPS65145

Flash
12 V DLPA100
PMIC and
Motor
1.21V
3.3V
5V
} DLPC7540

ADDR DATA Controller CW Motor


(23) (16) Drive

1.15V FANS(3x)
1.21V
1.8V CTRL Comparator
3.3V
CW_INDEX1
Vref
HDMI
Front End IC I2C
3840x2160 2-Port HSSI
VbyOneTM LS Interface
@ 60Hz
SPI VOFFSET
TPS65145
DMD VRESET DLP650TE
3.3V
3D L/R DLPC7540 Voltages VBIAS .65" UHD
Controller S451 HSSI
GPIO
1.8V DMD
12V LMR33630C
Tilt (& Roll)
Sensor Temp
3.3V
I2 C TMP411 (2)
IR Rx (2)
USB2.0 OTG
(2) XPR Drive Data Drive 4-Way XPR
Electronics Actuator
USB 2.0
USB2.0 GPIO
(2) DB Drive Data Dynamic Black
Mux
Actuators (2X)
USB
(2)
Camera
DLP Chipset Components

TI Components

3rd Party Components

Figure 8-2. Typical 4K UHD Lamp Phosphor Application Diagram

8.2.1 Design Requirements


Other core components of the display system include an illumination source, an optical engine for the
illumination and projection optics, other electrical and mechanical components, and software. The type of
illumination used and desired brightness has a major effect on the overall system design and size.
The display system uses the DLP650TE DMD as the core imaging device and contains a 0.65-inch array of
micromirrors. The DLPC7540 controller is the digital interface between the DMD and the rest of the system,
taking digital input from front end receiver and driving the DMD over a high-speed interface. The DLPA100
PMIC serves as a voltage regulator for the controller, and color filter wheel and phosphor wheel motor control.
The TPS65145 provide the DMD reset, offset and bias voltages. The LMR33630C provides 1.8-V power to the
DLP650TE DMD.

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8.2.2 Detailed Design Procedure


For a complete DLP system, an optical module or light engine is required that contains the DLP650TE DMD,
associated illumination sources, optical elements, and necessary mechanical components.
To ensure reliable operation, the DMD must always be used with DLPC7540 display controller and the
TPS65145 PMIC and DLPA100. Refer to the DMD board reference design and DLPC7540 reference design
for layout and design recommendations.
8.2.3 Application Curve
In a typical projector application, the luminous flux on the screen from the DMD depends on the optical design of
the projector. The efficiency and total power of the illumination optical system and the projection optical system
determines the overall light output of the projector. The DMD is inherently a linear spatial light modulator, so its
efficiency just scales the light output. Figure 8-3 describes the relationship of laser input optical power to light
output for a laser-phosphor illumination system, where the phosphor is not at its thermal quenching limit. .
1
0.95
0.9
0.85
0.8
Normalized Light Output

0.75
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
Normalized Laser Power norm

Figure 8-3. Normalized Light Output vs Normalized Laser Power for Laser Phosphor Illumination

8.3 Temperature Sensor Diode


The DMD features a built-in thermal diode that measures the temperature at one corner of the die outside
the micromirror array. The thermal diode can be interfaced with the TMP411 temperature sensor as shown in
Figure 8-4. The software application contains functions to configure the TMP411 to read the DLP650TE DMD
temperature sensor diode. This data can be leveraged by the customer to incorporate additional functionality in
the overall system design such as adjusting illumination, fan speeds, and so on. All communication between the
TMP411 and the DLPC7540 controller happens over the I2C interface. The TMP411 connects to the DMD via
pins outlined in Table 5-1.
Leave TEMP_N and TEMP_P pins unconnected (NC) if the temp sensor is not used.

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3.3V

R1 R2 TMP411 DLP650TE
SCL VCC
To DLPC7540 Controller

R3 R5 TEMP_P
SDA D+

ALERT
C1

THERM

R4 R6
GND D-
TEMP_N

GND

A. Details omitted for clarity.


B. See the TMP411 data sheet for system board layout recommendation.
C. See the TMP411 data sheet for suggested component values for R1, R2, R3, R4, and C1.
D. R5 = 0 Ω. R6 = 0 Ω. Place 0-Ω resistors close to the DMD package pins.

Figure 8-4. TMP411 Sample Schematic

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9 Power Supply Recommendations


The following power supplies are all required to operate the DMD:
• VSS
• VBIAS
• VDD
• VOFFSET
• VRESET
DMD power-up and power-down sequencing is strictly controlled by the DLP display controller.

CAUTION
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to any of the prescribed power-up and power-down requirements may
affect device reliability. See the DMD power supply sequencing requirements in Figure 9-1.
VBIAS, VDD, VOFFSET, and VRESET power supplies must be coordinated during power-up and power-
down operations. Failure to meet any of the below requirements results in a significant reduction in
the DMD reliability and lifetime. Common ground VSS must also be connected.

9.1 Power Supply Sequence Requirements


SYMBOL PARAMETER DESCRIPTION MIN TYP MAX UNIT
tDELAY1 Delay requirement from VOFFSET power up to VBIAS power up 1 2 ms
from VBIAS and VRESET powered on and stable to
tDELAY2 Delay requirement 20 µs
DMD_EN_ARSTZ going high
from VOFFSET, VBIAS and VRESET powered down to
tDELAY3 Delay requirement 50 µs
when VDD and VDDA can power down

9.2 DMD Power Supply Power-Up Procedure


• During power-up, VDD must always start and settle before VOFFSET plus tDELAY1 specified in Section 9.1,
VBIAS, and VRESET voltages are applied to the DMD.
• During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in Section 6.4.
• During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS.
• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements specified in Section 6.1, in Section 6.4, and in Figure 9-1.
• During power-up, LVCMOS input pins must not be driven high until after VDD has settled at operating voltage
listed in Section 6.4.
9.3 DMD Power Supply Power-Down Procedure
• During power-down, VDD must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the
specified limit of ground. See Section 9.1.
• During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in Section 6.4.
• During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.
• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements specified in Section 6.1, in Section 6.4, and in Figure 9-1.
• During power-down, LVCMOS input pins must be less than specified in Section 6.4.

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Note A Note J
...
VDD and VDDA
Note H VSS
tDELAY3
...
Note B
VOFFSET
Note D V < Specification VSS
tDELAY1
...
VBIAS
VSS
Note C
VRESET V < Specification
Note E VSS

...
Note F
tDELAY2
Note G
...
DMD_EN_ARSTZ
VSS

Time
A. See the Pin Functions table.
B. To prevent excess current, the supply voltage difference |VBIAS – VOFFSET| must be less than the specified limit in Section 6.4.
C. To prevent excess current, the supply difference |VBIAS – VRESET| must be less than the specified limit in Section 6.4.
D. VBIAS must power up after VOFFSET has powered up, per tDELAY1 specification in Section 9.1.
E. VRESET, VOFFSET and VBIAS ramps must start after VDD and VDDA are powered up and stable.
F. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates
DMD_EN_ARSTZ and disables VBIAS, VRESET and VOFFSET.
G. Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware
DMD_EN_ARSTZ goes low.
H. VDD must remain powered on and stable until after VOFFSET, VBIAS, and VRESET are powered off, per tDELAY3 specification in Section 9.1.
I. To prevent excess current, the supply voltage delta |VDDA – VDD| must be less than specified limit in Section 6.4.
J. Not to scale. Details omitted for clarity.

Figure 9-1. DMD Power Supply Requirements

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10 Layout
10.1 Layout Guidelines
The DLP650TE DMD is part of a chipset that is controlled by the DLPC7540 display controller in conjunction with
theTPS65145 PMIC and the DLPA100 power and motor controller. These guidelines are targeted at designing
a PCB board with the DLP650TE DMD. The DMD board is a high-speed multi-layer PCB, with primarily high-
speed digital logic including double data rate 3.2 Gbps and 250 Mbps differential data buses run to the DMD. TI
recommends that full or mini power planes are used for VOFFSET, VRESET, and VBIAS. Solid planes are required
for ground (VSS). The target impedance for the PCB is 50 Ω ±10% with exceptions listed in Table 10-1. TI
recommends a 10 layer stack-up as described in Table 10-2. TI recommends manufacturing the PCB with a high
quality FR-4 material.
10.2 Impedance Requirements
TI recommends a target impedance for the PCB of 50 Ω ±10% for all signals. The exceptions are listed in Table
10-1.
Table 10-1. Special Impedance Requirements
SIGNAL TYPE SIGNAL NAME IMPEDANCE (Ω)
DMD_HSSI0_N_(0…7),
DMD_HSSI0_P_(0…7),
DMD_HSSI1_N_(0…7),
DMD_HSSI1_P_(0…7), 100-Ω differential (50-Ω single
DMD High Speed Data Signals
DMD_HSSI0_CLK_N, ended)
DMD_HSSI0_CLK_P,
DMD_HSSI1_CLK_N,
DMD_HSSI1_CLK_P
DMD_LS0_WDATA_N,
DMD Low Speed Interface DMD_LS0_WDATA_P, 100-Ω differential (50-Ω single
Signals DMD_LS0_CLK_N, ended)
DMD_LS0_CLK_P

10.3 Layers
Table 10-2 shows the layer stack-up and copper weight for each layer.
Table 10-2. Layer Stack-Up
LAYER
LAYER NAME COPPER WT. (oz.) COMMENTS
NO.
Side A—DMD, primary DMD and escapes. Two data input connectors. Top components including
0.5 oz. (before
1 components, power mini- power generation and two data input connectors. Low frequency signals
plating)
planes routing. Should have copper fill (GND) plated up to 1 oz.
2 Ground 0.5 Solid ground plane (net GND) reference for signal layers #1, 3
High speed signal layer. High speed differential data busses from input
3 Signal (high frequency) 0.5
connector to DMD
4 Ground 0.5 Solid ground plane (net GND) reference for signal layers #3, #5
5 Power 0.5 Primary split power planes for 1.8 V, 3.3 V, 10 V, -14 V, 18 V
6 Power 0.5 Primary split power planes for 1.8 V, 3.3 V, 10 V, -14 V, 18 V
7 Ground 0.5 Solid ground plane (net GND) reference for signal layer #8
High speed signal layer. High speed differential data buses from input
8 Signal (high frequency) 0.5
connector to DMD
9 Ground 0.5 Solid ground plane (net GND) Reference for signal layers #8, 10
Side B—Secondary
0.5 oz. (before Discrete components if necessary. Low frequency signals routing. Should
10 components, power mini-
plating) be copper fill plated up to 1 oz.
planes

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10.4 Trace Width, Spacing


Unless otherwise specified, TI recommends that all signals follow the 0.005”/0.015” (Trace-Width/Spacing)
design rule. Use an analysis of impedance and stack-up requirements to determine and calculate actual trace
widths.
Maximize the width of all voltage signals as space permits. Follow the width and spacing requirements listed in
Table 10-3.
Table 10-3. Special Trace Widths, Spacing Requirements
MINIMUM TRACE
SIGNAL NAME MINIMUM TRACE SPACING (MIL) LAYOUT REQUIREMENT
WIDTH (MIL)
GND MAXIMIZE 5 Maximize trace width to connecting pin as a minimum.
Create mini planes on layers 1 and 10 as needed. Connect
P3P3V 40 15 to devices on layers 1 and 10 as necessary with multiple
vias.
Create mini planes on layers 1 and 10 as needed. Connect
P1P8V 40 15 to devices on layers 1 and 10 as necessary with multiple
vias.
Create mini planes on layers 1 and 10 as needed. Connect
VOFFSET 40 15
to devices on layers 1 and 10 as necessary.
Create mini planes on layers 1 and 10 as needed. Connect
VRESET 40 15
to devices on layers 1 and 10 as necessary.
Create mini planes on layers 1 and 10 as needed. Connect
VBIAS 40 15
to devices on layers 1 and 10 as necessary.

10.5 Power
TI strongly discourages signal routing on power planes or on planes adjacent to power planes. If signals must
be routed on layers adjacent to power planes, they must not cross splits in power planes to prevent EMI and
preserve signal integrity.
Connect all internal digital ground (GND) planes in as many places as possible. Connect all internal ground
planes with a minimum distance between connections of 0.5”. Extra vias may not be required if there are
sufficient ground vias due to normal ground connections of devices.
Connect power and ground pins of each component to the power and ground planes with at least one via for
each pin. Minimize trace lengths for component power and ground pins. (ideally, less than 0.100”).
Ground plane slots are strongly discouraged.
10.6 Trace Length Matching Recommendations
Table 10-4 and Table 10-5 describe recommended signal trace length matching requirements. Follow these
guidelines to avoid routing long traces over large areas of the PCB:
• Match the trace lengths so that longer signals route in a serpentine pattern
• Minimize the number of turns.
• Ensure that the turn angles no sharper than 45 degrees.
Figure 10-1 shows an example of the HSSI signal pair routing.
Signals listed in Table 10-4 are specified for data rate operation at up to 3.2 Gbps. Minimize the layer changes
for these signals. Minimize the number of vias. Avoid sharp turns and layer switching while minimizing the
lengths. When layer changes are necessary, place GND vias around the signal vias to provide a signal return
path. The distance from one pair of differential signals to another must be at least 2 times the distance within the
pair.

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Table 10-4. HSSI High Speed DMD Data Signals


SIGNAL NAME REFERENCE SIGNAL ROUTING SPECIFICATION UNIT
DMD_HSSI0_N(0...7), DMD_HSSI0_CLK_N,
±0.25 inch
DMD_HSSI0_P(0...7) DMD_HSSI_CLK_P
DMD_HSSI1_N(0...7), DMD_HSSI0_CLK_N,
±0.25 inch
DMD_HSSI1_P(0...7) DMD_HSSI_CLK_P
DMD_HSSI0_CLK_P DMD_HSSI1_CLK_P ±0.05 inch
Intra-pair P Intra-pair N ±0.01 inch

Table 10-5. Other Timing Critical Signals


SIGNAL NAME Constraints Routing Layers
LS_CLK_P, LS_CLK_N Intra-pair (P to N)
LS_WDATA_P, Matched to 0.01 inches
Layers 3, 8
LS_WDATA_N Signal-to-signal
LS_RDATA_A Matched to +/- 0.25 inches

Figure 10-1. Example HSSI PCB Routing

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11 Device and Documentation Support


11.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Device Support
11.2.1 Device Nomenclature

DLP650TE xc FYP
Package

TI Internal Numbering

Device Descriptor

Figure 11-1. Part Number Description

11.2.2 Device Markings


The device marking includes both human-readable information and a 2-dimensional matrix code. The human-
readable information is described in Figure 11-2. The 2-dimensional matrix code is an alpha-numeric string that
contains the DMD part number, Part 1 and Part 2 of the serial number.
Example:
TI Internal Numbering DMD Part Number

Part 2 of Serial Number


GHXXXXX LLLLLLM

(7 characters)
DLP650TE xc FYP
YYYYYY

Part 1 of Serial Number


(7 characters)

2-Dimension Matrix Code


(Part Number and Serial Number)

Figure 11-2. DMD Marking Locations

11.3 Documentation Support


11.3.1 Related Documentation
The following documents contain additional information related to the chipset components used with the DMD.
• DLPC7540 Display Controller Data Sheet
• TPS65145 Data Sheet

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• DLPA100 Power and Motor Driver Data Sheet


11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
TI E2E™ is a trademark of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information


The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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12.1 Package Option Addendum


12.1.1 Packaging Information
Package Package MSL Peak Temp Device Marking(5)
Orderable Device Status (1) Pins Package Qty Eco Plan (2) Lead/Ball Finish(4) (3) Op Temp (°C) (6)
Type Drawing
DLP650TEA0FYP ACTIVE CPGA FYP 149 33 RoHS & Green Call TI Call TI see Figure 11-2

(1) The marketing status values are defined as follows:


ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material)
space
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(4) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided
by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider
certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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PACKAGE OPTION ADDENDUM

www.ti.com 24-Mar-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DLP650TEA0FYP ACTIVE CPGA FYP 149 33 RoHS & Green NI-AU N / A for Pkg Type 0 to 70

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 12-May-2022

TRAY

L - Outer tray length without tabs KO -


Outer
tray
height

W-
Outer
tray
width
Text

P1 - Tray unit pocket pitch


CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal


Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW
Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
DLP650TEA0FYP FYP CPGA 149 33 3 x 11 150 315 135.9 12190 27.5 20 27.45

Pack Materials-Page 1
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