PLECS

dx

DEMO MODEL

Power Supply Compensator Analysis

Last updated in PLECS 4.3.1

www.plexim.com
Request a PLECS trial license

Check the PLECS documentation

 Power Supply Compensator Analysis

1 Overview
This demonstration analyzes the performance of Type 2 and Type 3 analog compensators used in
power supply units (PSUs). The analyzed PSU is a buck converter with modeled-in inductor and ca-
pacitor non-idealities. The role of the capacitor and its effective series resistance (ESR) on the plant
zero and poles is discussed. Furthermore, the compensators’ performance is analyzed with respect
to the phase margin, system bandwidth, and rate of change in gain at the cross-over frequency. This
analysis is based on [1].

Note This model contains model initialization commands that are accessible from:
PLECS Standalone: The menu Simulation + Simulation Parameters... + Initializations
PLECS Blockset: Right click in the Simulink model window + Model Properties + Callbacks +
InitFcn*

2 Model
2.1 Power circuit

GND
d'
V_ref
V_out/V_in +~ d
V_out

Open-Loop/Closed-Loop i_L

Controller
m

Modulator
s

R: R_L L: L
A

FET
R: ESR
V: V_in D R: R_o V ~
C: C_total vo'

Figure 1: Type 2 and type 3 compensator analysis for power supplies (PLECS Standalone)

The analyzed PSU is a simple buck converter where the capacitance and ESR effects are being investi-
gated. The plant transfer function can be simplified to the following:
Ro (Ctotal · ESR · s + 1)
Gplant (s) =
L · Ctotal · s2 (Ro + ESR) + s(L + Ro · Ctotal · ESR) + Ro
where the Laplace operator, “s”, and thus the plant transfer function, varies as a function of the fre-
quency. In Gplant (s), the effects of the inductor resistance are assumed to be minimal on system per-
formance and, thus, ignored. For the buck converter, the system double poles and zero due to the LC-
filter and ESR, respectively, are given by:
1
fLC = √
2 · π · L · Ctotal
1
fESR =
2 · π · Ctotal · ESR

www.plexim.com 1
 Power Supply Compensator Analysis

The voltage controllers are designed to obtain desired open-loop system characteristics by placing the
system poles and zeros.

2.2 Control
The model can be run either as an open-loop or closed-loop controlled system. Double-clicking on the
Manual Switch (“Open-Loop/Closed-Loop”) toggles the model configuration.

GND
ControllerType
GND

V_ref d *
V_ref *
V_out
d

V_out

i_L OverCurrent
Protection

Figure 2: Closed-loop controller schematic

The closed-loop control system consists of a voltage-mode regulator and over-current protection. The
voltage-mode regulator can be configured to operate either with a Type 2 or Type 3 compensator.
The closed-loop system should have the following characteristics to ensure high system dynamics and
stability:
1
• A system bandwidth between 10 and 15 of the switching frequency.
• A -20 dB/decade slope of the gain near the system cross-over frequency.
• A phase margin greater than 45◦ .

Type 2 Compensator

Type 2 compensators are used in systems where the desired cross-over frequency (fx ) is greater than
both fLC and fESR . That is:
fLC < fESR < fx < fsw /2
where fsw /2 is half the switching frequency. We will refer to this as System 1.

V_out V_ref
GND

R: Type2.Rf1
Op-Amp
+
-
V K
R: Type2.Rc1 d
R: Type2.Rf2 K: 1/V_osc

C: Type2.C1

C: Type2.C2

Figure 3: Type 2 compensator circuit

The Type 2 compensator in the model shown above is implemented using an ideal op-amp with finite
gain. The op-amp gain is set to 106 . The positive input terminal is connected to the reference voltage.

www.plexim.com 2
 Power Supply Compensator Analysis

The output voltage of the buck converter is scaled using a resistive divider and connected to the nega-
tive input terminal of the op-amp. Furthermore, the negative input is connected to the op-amp output
via an RC network. The simplified transfer function of the Type 2 compensator (Eq. 9 in [1]) is given
by:
1 + C1 · RC1 · s
HType2 (s) ≈
C1 · R11 · s(1 + C2 · RC1 · s)
The zero and poles of the compensator are given by:
1
fz1 =
2 · π · C1 · RC1
fp1 = 0
1
fp2 =
2 · π · C2 · RC1
To obtain the desired system performance, the resistors and capacitors can be selected to ensure that:
fz1 ≈ 0.75 · fLC
fp2 ≈ fsw /2
Placing the zero and pole at these locations, along with the pole at the origin (fp1 ), causes the open-
loop transfer function of the closed-loop system to exhibit the desired characteristics.

Type 3 Compensator

In systems where fx is less than fESR , the Type 2 compensator may not be able to provide the desired
closed-loop system response and stability. A Type 3 compensator can then be used.

V_out V_ref
GND

R: Type3.Rf3
R: Type3.Rf1
Op-Amp
C: Type3.Cf3 +
-
V K
R: Type3.Rc1 d
R: Type3.Rf2 K: 1/V_osc

C: Type3.C1

C: Type3.C2

Figure 4: Type 3 compensator circuit

As with the Type 2 compensator, the Type 3 compensator is implemented with an ideal, finite-gain op-
amp. The Type 3 compensator configuration is shown above. For systems where:
fLC < fx < fESR < fsw /2
the additional pole and zero of the Type 3 compensator allow for the design of a fast and stable closed-
loop control of this system. We will refer to this as System 2. The simplified transfer function of the
Type 3 compensator (Eq. 22 in [1]) is given by:
(1 + C1 · RC1 · s) · (1 + Cf3 · (Rf1 + Rf3 ))
HType3 (s) ≈
C1 · Rf1 · s(1 + C2 · RC1 · s) · (1 + Cf3 · Rf3 · s)
The zero and poles of the compensator are given by:
1
fz1 =
2 · π · C1 · RC1

www.plexim.com 3
 Power Supply Compensator Analysis

1
fz2 =
2 · π · Cf3 · (Rf1 + Rf3 )
fp1 = 0
1
fp2 =
2 · π · Cf3 · Rf3
1
fp3 =
2 · π · C2 · RC1
To obtain the desired system performance, the resistors and capacitors can be selected to ensure that:
fz1 ≈ 0.75 · fLC
fz2 ≈ fLC
fp2 ≈ fESR
fp3 ≈ fsw /2
Placing the zeros and poles at these locations, along with the pole at the origin (fp1 ) causes the open-
loop transfer function of the closed-loop system to demonstrate the desired characteristics.

Overcurrent protection

u-I_out_max >0 NOT

Monoflop
Duration: 2/(1.5e6)

Figure 5: Overcurrent protection circuit

An IR3840 synchronous buck regulator based over current protection is modeled in this circuit. This
is used to limit the current that is drawn from the input voltage source. As the current through the
inductor reaches the maximum allowable current in the system, the switching modulation index is set
to 0. After a few clock cycles the over current protection system is reset.

3 Simulation
The model has been configured to emulate the two different systems described above. The variable
CapSelector is used to toggle between the two systems. In PLECS Standalone and PLECS Blockset
this variable can be accessed and changed the following way:
• Standalone: Open the Initialization tab under Simulation + Simulation parameters... and set
a value in line #13
• Blockset: Open the Simulink menu File + Model Properties Then in the Callbacks tab choose the
InitFcn* and set a value in line #13

Open-loop control analysis

In the compensator design process, the open-loop plant transfer function is used to verify the analyti-
cal model of the plant. With the model as is, execute the following steps for either PLECS Standalone
or PLECS Blockset:
• Standalone: Select Analysis tools... from the Simulation menu. Run either the Multitone or Im-
pulse Response Analysis for the “Control to Output TF” analysis. This provides the transfer function
for the open-loop system.

www.plexim.com 4
 Power Supply Compensator Analysis

Magnitude
Cap0:Vo/d
Magnitude / dB

20 Cap1:Vo/d

Phase
0
Cap0:Vo/d
Cap1:Vo/d
Phase / °

-50

-100

1000 10000 100000

Frequency / Hz

Figure 6: Plant transfer function with different output capacitors (Cap0: 940 µF, ESR=10 mΩ and Cap1:
220 µF, ESR=8 mΩ)

• Blockset: Double-click on the Impulse Response Analysis or Loop Gain (Multitone) blocks on the
Simulink level to open the respective dialogs and click on the Start analysis button. The progress
of an analysis can be configured for display in the MATLAB Command Window. When the analysis
has finished a new Bode plot will be displayed showing the corresponding transfer function.
Observe the Bode plot generated by the analysis (dashed line). The cross-over frequency is about
40 kHz, and the slope is close to -20 dB/decade. The phase margin is about 95◦ . While the slope and
phase margin are desirable, the cross-over frequency remains lower than 60 kHz, which is 1/10 of the
switching frequency. Thus, the system has a slower dynamic response than desired.
Change the variable CapSelector to 1 as described above. Re-run the previous analysis.
Observe the new Bode plot generated by the analysis (solid line). The cross-over frequency is about
60 kHz and the phase margin is about 50◦ . While the cross-over frequency and phase margin are de-
sirable, the slope of the gain curve around the cross-over frequency is close to -40 dB/decade. This may
result in an unstable system.

Closed-loop control analysis: system 1

Reset the CapSelector to 0 as described above. Double-click on the manual switch “Open-Loop/Closed-
Loop” to configure the model for closed-loop control operation. Run the Loop Gain Analysis (in PLECS
Standalone “System 1 - Loop Gain Analysis”) to obtain the open-loop transfer function of the closed-
loop system.
Analyze the Bode plot generated by the analysis. The cross-over frequency is about 65 kHz, the slope
of the gain is close to -20 dB/decade, and the phase margin is about 65◦ . Thus, the system has the de-
sired stability and dynamics (dashed line in Fig. 7).
Next, in the controller subsystem, change the controller type from Type 2 to Type 3. Re-run the same
analysis. Observe the Bode plot generated by the analysis. The cross-over frequency is about 100 kHz,
the slope of the gain is close to -20 dB/decade, and the phase margin is about 65◦ . Thus, this system
also has the desired stability and dynamics (solid line in Fig. 7).

www.plexim.com 5
 Power Supply Compensator Analysis

Magnitude

40 Sys1Type2:Gain
Magnitude / dB

Sys1Type3:Gain
20

-20
Phase
-60 Sys1Type2:Gain
Sys1Type3:Gain
-80
Phase / °

-100
-120
-140
1000 10000 100000
Frequency / Hz

Figure 7: Loop gain of the closed-loop System 1 with Type 2 and Type 3 controller

Magnitude

40 Sys2Type2:Gain
Magnitude / dB

Sys2Type3:Gain
20

-20
Phase
Sys2Type2:Gain
0 Sys2Type3:Gain
Phase / °

-100

-200
1000 10000 100000
Frequency / Hz

Figure 8: Loop gain of the closed-loop System 2 with Type 2 and Type 3 controller

Closed-loop control analysis: system 2

Next, change the CapSelector to 1 as described above. Run the Loop Gain Analysis (in PLECS Stan-
dalone “System 2 - Loop Gain Analysis”) to obtain the open-loop transfer function of the closed-loop
system. The cross-over frequency is about 75 kHz, the slope of the gain is close to -20 dB/decade, and
the phase margin is about 61◦ . Thus, this system also has the desired stability and dynamics.
Next, in the controller subsystem, change the controller type from Type 3 to Type 2. Re-run the
same analysis. The cross-over frequency is about 92 kHz. However, the slope of the gain is close to -
40 dB/decade, and the phase margin is about 25◦ . Thus, the Type 2 compensator is unable to meet the
system stability requirements for System 2.

www.plexim.com 6
 Power Supply Compensator Analysis

References
[1] A. M. Rahimi, P. Parto, P. Asadi, “Compensator Design Procedure for Buck Converter with
Voltage-Mode Error-Amplifier”, International Rectifier Application Note AN-1162.

www.plexim.com 7
 Revision History:

PLECS 4.3.1 First release

How to Contact Plexim:

% +41 44 533 51 00 Phone

+41 44 533 51 01 Fax
) Plexim GmbH Mail
Technoparkstrasse 1
8005 Zurich
Switzerland
@ [email protected] Email
http://www.plexim.com Web

PLECS Demo Model

© 2002–2022 by Plexim GmbH
The software PLECS described in this document is furnished under a license agreement. The software
may be used or copied only under the terms of the license agreement. No part of this manual may be
photocopied or reproduced in any form without prior written consent from Plexim GmbH.
PLECS is a registered trademark of Plexim GmbH. MATLAB, Simulink and Simulink Coder are regis-
tered trademarks of The MathWorks, Inc. Other product or brand names are trademarks or registered
trademarks of their respective holders.